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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * adv7180.c Analog Devices ADV7180 video decoder driver
0004  * Copyright (c) 2009 Intel Corporation
0005  * Copyright (C) 2013 Cogent Embedded, Inc.
0006  * Copyright (C) 2013 Renesas Solutions Corp.
0007  */
0008 #include <linux/module.h>
0009 #include <linux/init.h>
0010 #include <linux/errno.h>
0011 #include <linux/kernel.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/i2c.h>
0014 #include <linux/slab.h>
0015 #include <linux/of.h>
0016 #include <linux/gpio/consumer.h>
0017 #include <linux/videodev2.h>
0018 #include <media/v4l2-ioctl.h>
0019 #include <media/v4l2-event.h>
0020 #include <media/v4l2-device.h>
0021 #include <media/v4l2-ctrls.h>
0022 #include <linux/mutex.h>
0023 #include <linux/delay.h>
0024 
0025 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM      0x0
0026 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED      0x1
0027 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM       0x2
0028 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM       0x3
0029 #define ADV7180_STD_NTSC_J              0x4
0030 #define ADV7180_STD_NTSC_M              0x5
0031 #define ADV7180_STD_PAL60               0x6
0032 #define ADV7180_STD_NTSC_443                0x7
0033 #define ADV7180_STD_PAL_BG              0x8
0034 #define ADV7180_STD_PAL_N               0x9
0035 #define ADV7180_STD_PAL_M               0xa
0036 #define ADV7180_STD_PAL_M_PED               0xb
0037 #define ADV7180_STD_PAL_COMB_N              0xc
0038 #define ADV7180_STD_PAL_COMB_N_PED          0xd
0039 #define ADV7180_STD_PAL_SECAM               0xe
0040 #define ADV7180_STD_PAL_SECAM_PED           0xf
0041 
0042 #define ADV7180_REG_INPUT_CONTROL           0x0000
0043 #define ADV7180_INPUT_CONTROL_INSEL_MASK        0x0f
0044 
0045 #define ADV7182_REG_INPUT_VIDSEL            0x0002
0046 #define ADV7182_REG_INPUT_RESERVED          BIT(2)
0047 
0048 #define ADV7180_REG_OUTPUT_CONTROL          0x0003
0049 #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL     0x0004
0050 #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS     0xC5
0051 
0052 #define ADV7180_REG_AUTODETECT_ENABLE           0x0007
0053 #define ADV7180_AUTODETECT_DEFAULT          0x7f
0054 /* Contrast */
0055 #define ADV7180_REG_CON     0x0008  /*Unsigned */
0056 #define ADV7180_CON_MIN     0
0057 #define ADV7180_CON_DEF     128
0058 #define ADV7180_CON_MAX     255
0059 /* Brightness*/
0060 #define ADV7180_REG_BRI     0x000a  /*Signed */
0061 #define ADV7180_BRI_MIN     -128
0062 #define ADV7180_BRI_DEF     0
0063 #define ADV7180_BRI_MAX     127
0064 /* Hue */
0065 #define ADV7180_REG_HUE     0x000b  /*Signed, inverted */
0066 #define ADV7180_HUE_MIN     -127
0067 #define ADV7180_HUE_DEF     0
0068 #define ADV7180_HUE_MAX     128
0069 
0070 #define ADV7180_REG_DEF_VALUE_Y 0x000c
0071 #define ADV7180_DEF_VAL_EN      0x1
0072 #define ADV7180_DEF_VAL_AUTO_EN 0x2
0073 #define ADV7180_REG_CTRL        0x000e
0074 #define ADV7180_CTRL_IRQ_SPACE      0x20
0075 
0076 #define ADV7180_REG_PWR_MAN     0x0f
0077 #define ADV7180_PWR_MAN_ON      0x04
0078 #define ADV7180_PWR_MAN_OFF     0x24
0079 #define ADV7180_PWR_MAN_RES     0x80
0080 
0081 #define ADV7180_REG_STATUS1     0x0010
0082 #define ADV7180_STATUS1_IN_LOCK     0x01
0083 #define ADV7180_STATUS1_AUTOD_MASK  0x70
0084 #define ADV7180_STATUS1_AUTOD_NTSM_M_J  0x00
0085 #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
0086 #define ADV7180_STATUS1_AUTOD_PAL_M 0x20
0087 #define ADV7180_STATUS1_AUTOD_PAL_60    0x30
0088 #define ADV7180_STATUS1_AUTOD_PAL_B_G   0x40
0089 #define ADV7180_STATUS1_AUTOD_SECAM 0x50
0090 #define ADV7180_STATUS1_AUTOD_PAL_COMB  0x60
0091 #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70
0092 
0093 #define ADV7180_REG_IDENT 0x0011
0094 #define ADV7180_ID_7180 0x18
0095 
0096 #define ADV7180_REG_STATUS3     0x0013
0097 #define ADV7180_REG_ANALOG_CLAMP_CTL    0x0014
0098 #define ADV7180_REG_SHAP_FILTER_CTL_1   0x0017
0099 #define ADV7180_REG_CTRL_2      0x001d
0100 #define ADV7180_REG_VSYNC_FIELD_CTL_1   0x0031
0101 #define ADV7180_VSYNC_FIELD_CTL_1_NEWAV 0x12
0102 #define ADV7180_REG_MANUAL_WIN_CTL_1    0x003d
0103 #define ADV7180_REG_MANUAL_WIN_CTL_2    0x003e
0104 #define ADV7180_REG_MANUAL_WIN_CTL_3    0x003f
0105 #define ADV7180_REG_LOCK_CNT        0x0051
0106 #define ADV7180_REG_CVBS_TRIM       0x0052
0107 #define ADV7180_REG_CLAMP_ADJ       0x005a
0108 #define ADV7180_REG_RES_CIR     0x005f
0109 #define ADV7180_REG_DIFF_MODE       0x0060
0110 
0111 #define ADV7180_REG_ICONF1      0x2040
0112 #define ADV7180_ICONF1_ACTIVE_LOW   0x01
0113 #define ADV7180_ICONF1_PSYNC_ONLY   0x10
0114 #define ADV7180_ICONF1_ACTIVE_TO_CLR    0xC0
0115 /* Saturation */
0116 #define ADV7180_REG_SD_SAT_CB   0x00e3  /*Unsigned */
0117 #define ADV7180_REG_SD_SAT_CR   0x00e4  /*Unsigned */
0118 #define ADV7180_SAT_MIN     0
0119 #define ADV7180_SAT_DEF     128
0120 #define ADV7180_SAT_MAX     255
0121 
0122 #define ADV7180_IRQ1_LOCK   0x01
0123 #define ADV7180_IRQ1_UNLOCK 0x02
0124 #define ADV7180_REG_ISR1    0x2042
0125 #define ADV7180_REG_ICR1    0x2043
0126 #define ADV7180_REG_IMR1    0x2044
0127 #define ADV7180_REG_IMR2    0x2048
0128 #define ADV7180_IRQ3_AD_CHANGE  0x08
0129 #define ADV7180_REG_ISR3    0x204A
0130 #define ADV7180_REG_ICR3    0x204B
0131 #define ADV7180_REG_IMR3    0x204C
0132 #define ADV7180_REG_IMR4    0x2050
0133 
0134 #define ADV7180_REG_NTSC_V_BIT_END  0x00E6
0135 #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F
0136 
0137 #define ADV7180_REG_VPP_SLAVE_ADDR  0xFD
0138 #define ADV7180_REG_CSI_SLAVE_ADDR  0xFE
0139 
0140 #define ADV7180_REG_ACE_CTRL1       0x4080
0141 #define ADV7180_REG_ACE_CTRL5       0x4084
0142 #define ADV7180_REG_FLCONTROL       0x40e0
0143 #define ADV7180_FLCONTROL_FL_ENABLE 0x1
0144 
0145 #define ADV7180_REG_RST_CLAMP   0x809c
0146 #define ADV7180_REG_AGC_ADJ1    0x80b6
0147 #define ADV7180_REG_AGC_ADJ2    0x80c0
0148 
0149 #define ADV7180_CSI_REG_PWRDN   0x00
0150 #define ADV7180_CSI_PWRDN   0x80
0151 
0152 #define ADV7180_INPUT_CVBS_AIN1 0x00
0153 #define ADV7180_INPUT_CVBS_AIN2 0x01
0154 #define ADV7180_INPUT_CVBS_AIN3 0x02
0155 #define ADV7180_INPUT_CVBS_AIN4 0x03
0156 #define ADV7180_INPUT_CVBS_AIN5 0x04
0157 #define ADV7180_INPUT_CVBS_AIN6 0x05
0158 #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
0159 #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
0160 #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
0161 #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
0162 #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
0163 
0164 #define ADV7182_INPUT_CVBS_AIN1 0x00
0165 #define ADV7182_INPUT_CVBS_AIN2 0x01
0166 #define ADV7182_INPUT_CVBS_AIN3 0x02
0167 #define ADV7182_INPUT_CVBS_AIN4 0x03
0168 #define ADV7182_INPUT_CVBS_AIN5 0x04
0169 #define ADV7182_INPUT_CVBS_AIN6 0x05
0170 #define ADV7182_INPUT_CVBS_AIN7 0x06
0171 #define ADV7182_INPUT_CVBS_AIN8 0x07
0172 #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
0173 #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
0174 #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
0175 #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
0176 #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
0177 #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
0178 #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
0179 #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
0180 #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
0181 #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
0182 
0183 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
0184 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
0185 
0186 #define V4L2_CID_ADV_FAST_SWITCH    (V4L2_CID_USER_ADV7180_BASE + 0x00)
0187 
0188 /* Initial number of frames to skip to avoid possible garbage */
0189 #define ADV7180_NUM_OF_SKIP_FRAMES       2
0190 
0191 struct adv7180_state;
0192 
0193 #define ADV7180_FLAG_RESET_POWERED  BIT(0)
0194 #define ADV7180_FLAG_V2         BIT(1)
0195 #define ADV7180_FLAG_MIPI_CSI2      BIT(2)
0196 #define ADV7180_FLAG_I2P        BIT(3)
0197 
0198 struct adv7180_chip_info {
0199     unsigned int flags;
0200     unsigned int valid_input_mask;
0201     int (*set_std)(struct adv7180_state *st, unsigned int std);
0202     int (*select_input)(struct adv7180_state *st, unsigned int input);
0203     int (*init)(struct adv7180_state *state);
0204 };
0205 
0206 struct adv7180_state {
0207     struct v4l2_ctrl_handler ctrl_hdl;
0208     struct v4l2_subdev  sd;
0209     struct media_pad    pad;
0210     struct mutex        mutex; /* mutual excl. when accessing chip */
0211     int         irq;
0212     struct gpio_desc    *pwdn_gpio;
0213     struct gpio_desc    *rst_gpio;
0214     v4l2_std_id     curr_norm;
0215     bool            powered;
0216     bool            streaming;
0217     u8          input;
0218 
0219     struct i2c_client   *client;
0220     unsigned int        register_page;
0221     struct i2c_client   *csi_client;
0222     struct i2c_client   *vpp_client;
0223     const struct adv7180_chip_info *chip_info;
0224     enum v4l2_field     field;
0225     bool            force_bt656_4;
0226 };
0227 #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler,     \
0228                         struct adv7180_state,   \
0229                         ctrl_hdl)->sd)
0230 
0231 static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
0232 {
0233     if (state->register_page != page) {
0234         i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
0235             page);
0236         state->register_page = page;
0237     }
0238 
0239     return 0;
0240 }
0241 
0242 static int adv7180_write(struct adv7180_state *state, unsigned int reg,
0243     unsigned int value)
0244 {
0245     lockdep_assert_held(&state->mutex);
0246     adv7180_select_page(state, reg >> 8);
0247     return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
0248 }
0249 
0250 static int adv7180_read(struct adv7180_state *state, unsigned int reg)
0251 {
0252     lockdep_assert_held(&state->mutex);
0253     adv7180_select_page(state, reg >> 8);
0254     return i2c_smbus_read_byte_data(state->client, reg & 0xff);
0255 }
0256 
0257 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
0258     unsigned int value)
0259 {
0260     return i2c_smbus_write_byte_data(state->csi_client, reg, value);
0261 }
0262 
0263 static int adv7180_set_video_standard(struct adv7180_state *state,
0264     unsigned int std)
0265 {
0266     return state->chip_info->set_std(state, std);
0267 }
0268 
0269 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
0270     unsigned int value)
0271 {
0272     return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
0273 }
0274 
0275 static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
0276 {
0277     /* in case V4L2_IN_ST_NO_SIGNAL */
0278     if (!(status1 & ADV7180_STATUS1_IN_LOCK))
0279         return V4L2_STD_UNKNOWN;
0280 
0281     switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
0282     case ADV7180_STATUS1_AUTOD_NTSM_M_J:
0283         return V4L2_STD_NTSC;
0284     case ADV7180_STATUS1_AUTOD_NTSC_4_43:
0285         return V4L2_STD_NTSC_443;
0286     case ADV7180_STATUS1_AUTOD_PAL_M:
0287         return V4L2_STD_PAL_M;
0288     case ADV7180_STATUS1_AUTOD_PAL_60:
0289         return V4L2_STD_PAL_60;
0290     case ADV7180_STATUS1_AUTOD_PAL_B_G:
0291         return V4L2_STD_PAL;
0292     case ADV7180_STATUS1_AUTOD_SECAM:
0293         return V4L2_STD_SECAM;
0294     case ADV7180_STATUS1_AUTOD_PAL_COMB:
0295         return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
0296     case ADV7180_STATUS1_AUTOD_SECAM_525:
0297         return V4L2_STD_SECAM;
0298     default:
0299         return V4L2_STD_UNKNOWN;
0300     }
0301 }
0302 
0303 static int v4l2_std_to_adv7180(v4l2_std_id std)
0304 {
0305     if (std == V4L2_STD_PAL_60)
0306         return ADV7180_STD_PAL60;
0307     if (std == V4L2_STD_NTSC_443)
0308         return ADV7180_STD_NTSC_443;
0309     if (std == V4L2_STD_PAL_N)
0310         return ADV7180_STD_PAL_N;
0311     if (std == V4L2_STD_PAL_M)
0312         return ADV7180_STD_PAL_M;
0313     if (std == V4L2_STD_PAL_Nc)
0314         return ADV7180_STD_PAL_COMB_N;
0315 
0316     if (std & V4L2_STD_PAL)
0317         return ADV7180_STD_PAL_BG;
0318     if (std & V4L2_STD_NTSC)
0319         return ADV7180_STD_NTSC_M;
0320     if (std & V4L2_STD_SECAM)
0321         return ADV7180_STD_PAL_SECAM;
0322 
0323     return -EINVAL;
0324 }
0325 
0326 static u32 adv7180_status_to_v4l2(u8 status1)
0327 {
0328     if (!(status1 & ADV7180_STATUS1_IN_LOCK))
0329         return V4L2_IN_ST_NO_SIGNAL;
0330 
0331     return 0;
0332 }
0333 
0334 static int __adv7180_status(struct adv7180_state *state, u32 *status,
0335                 v4l2_std_id *std)
0336 {
0337     int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
0338 
0339     if (status1 < 0)
0340         return status1;
0341 
0342     if (status)
0343         *status = adv7180_status_to_v4l2(status1);
0344     if (std)
0345         *std = adv7180_std_to_v4l2(status1);
0346 
0347     return 0;
0348 }
0349 
0350 static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
0351 {
0352     return container_of(sd, struct adv7180_state, sd);
0353 }
0354 
0355 static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
0356 {
0357     struct adv7180_state *state = to_state(sd);
0358     int err = mutex_lock_interruptible(&state->mutex);
0359     if (err)
0360         return err;
0361 
0362     if (state->streaming) {
0363         err = -EBUSY;
0364         goto unlock;
0365     }
0366 
0367     err = adv7180_set_video_standard(state,
0368             ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
0369     if (err)
0370         goto unlock;
0371 
0372     msleep(100);
0373     __adv7180_status(state, NULL, std);
0374 
0375     err = v4l2_std_to_adv7180(state->curr_norm);
0376     if (err < 0)
0377         goto unlock;
0378 
0379     err = adv7180_set_video_standard(state, err);
0380 
0381 unlock:
0382     mutex_unlock(&state->mutex);
0383     return err;
0384 }
0385 
0386 static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
0387                  u32 output, u32 config)
0388 {
0389     struct adv7180_state *state = to_state(sd);
0390     int ret = mutex_lock_interruptible(&state->mutex);
0391 
0392     if (ret)
0393         return ret;
0394 
0395     if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
0396         ret = -EINVAL;
0397         goto out;
0398     }
0399 
0400     ret = state->chip_info->select_input(state, input);
0401 
0402     if (ret == 0)
0403         state->input = input;
0404 out:
0405     mutex_unlock(&state->mutex);
0406     return ret;
0407 }
0408 
0409 static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
0410 {
0411     struct adv7180_state *state = to_state(sd);
0412     int ret = mutex_lock_interruptible(&state->mutex);
0413     if (ret)
0414         return ret;
0415 
0416     ret = __adv7180_status(state, status, NULL);
0417     mutex_unlock(&state->mutex);
0418     return ret;
0419 }
0420 
0421 static int adv7180_program_std(struct adv7180_state *state)
0422 {
0423     int ret;
0424 
0425     ret = v4l2_std_to_adv7180(state->curr_norm);
0426     if (ret < 0)
0427         return ret;
0428 
0429     ret = adv7180_set_video_standard(state, ret);
0430     if (ret < 0)
0431         return ret;
0432     return 0;
0433 }
0434 
0435 static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
0436 {
0437     struct adv7180_state *state = to_state(sd);
0438     int ret = mutex_lock_interruptible(&state->mutex);
0439 
0440     if (ret)
0441         return ret;
0442 
0443     /* Make sure we can support this std */
0444     ret = v4l2_std_to_adv7180(std);
0445     if (ret < 0)
0446         goto out;
0447 
0448     state->curr_norm = std;
0449 
0450     ret = adv7180_program_std(state);
0451 out:
0452     mutex_unlock(&state->mutex);
0453     return ret;
0454 }
0455 
0456 static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
0457 {
0458     struct adv7180_state *state = to_state(sd);
0459 
0460     *norm = state->curr_norm;
0461 
0462     return 0;
0463 }
0464 
0465 static int adv7180_g_frame_interval(struct v4l2_subdev *sd,
0466                     struct v4l2_subdev_frame_interval *fi)
0467 {
0468     struct adv7180_state *state = to_state(sd);
0469 
0470     if (state->curr_norm & V4L2_STD_525_60) {
0471         fi->interval.numerator = 1001;
0472         fi->interval.denominator = 30000;
0473     } else {
0474         fi->interval.numerator = 1;
0475         fi->interval.denominator = 25;
0476     }
0477 
0478     return 0;
0479 }
0480 
0481 static void adv7180_set_power_pin(struct adv7180_state *state, bool on)
0482 {
0483     if (!state->pwdn_gpio)
0484         return;
0485 
0486     if (on) {
0487         gpiod_set_value_cansleep(state->pwdn_gpio, 0);
0488         usleep_range(5000, 10000);
0489     } else {
0490         gpiod_set_value_cansleep(state->pwdn_gpio, 1);
0491     }
0492 }
0493 
0494 static void adv7180_set_reset_pin(struct adv7180_state *state, bool on)
0495 {
0496     if (!state->rst_gpio)
0497         return;
0498 
0499     if (on) {
0500         gpiod_set_value_cansleep(state->rst_gpio, 1);
0501     } else {
0502         gpiod_set_value_cansleep(state->rst_gpio, 0);
0503         usleep_range(5000, 10000);
0504     }
0505 }
0506 
0507 static int adv7180_set_power(struct adv7180_state *state, bool on)
0508 {
0509     u8 val;
0510     int ret;
0511 
0512     if (on)
0513         val = ADV7180_PWR_MAN_ON;
0514     else
0515         val = ADV7180_PWR_MAN_OFF;
0516 
0517     ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
0518     if (ret)
0519         return ret;
0520 
0521     if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
0522         if (on) {
0523             adv7180_csi_write(state, 0xDE, 0x02);
0524             adv7180_csi_write(state, 0xD2, 0xF7);
0525             adv7180_csi_write(state, 0xD8, 0x65);
0526             adv7180_csi_write(state, 0xE0, 0x09);
0527             adv7180_csi_write(state, 0x2C, 0x00);
0528             if (state->field == V4L2_FIELD_NONE)
0529                 adv7180_csi_write(state, 0x1D, 0x80);
0530             adv7180_csi_write(state, 0x00, 0x00);
0531         } else {
0532             adv7180_csi_write(state, 0x00, 0x80);
0533         }
0534     }
0535 
0536     return 0;
0537 }
0538 
0539 static int adv7180_s_power(struct v4l2_subdev *sd, int on)
0540 {
0541     struct adv7180_state *state = to_state(sd);
0542     int ret;
0543 
0544     ret = mutex_lock_interruptible(&state->mutex);
0545     if (ret)
0546         return ret;
0547 
0548     ret = adv7180_set_power(state, on);
0549     if (ret == 0)
0550         state->powered = on;
0551 
0552     mutex_unlock(&state->mutex);
0553     return ret;
0554 }
0555 
0556 static const char * const test_pattern_menu[] = {
0557     "Single color",
0558     "Color bars",
0559     "Luma ramp",
0560     "Boundary box",
0561     "Disable",
0562 };
0563 
0564 static int adv7180_test_pattern(struct adv7180_state *state, int value)
0565 {
0566     unsigned int reg = 0;
0567 
0568     /* Map menu value into register value */
0569     if (value < 3)
0570         reg = value;
0571     if (value == 3)
0572         reg = 5;
0573 
0574     adv7180_write(state, ADV7180_REG_ANALOG_CLAMP_CTL, reg);
0575 
0576     if (value == ARRAY_SIZE(test_pattern_menu) - 1) {
0577         reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);
0578         reg &= ~ADV7180_DEF_VAL_EN;
0579         adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
0580         return 0;
0581     }
0582 
0583     reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);
0584     reg |= ADV7180_DEF_VAL_EN | ADV7180_DEF_VAL_AUTO_EN;
0585     adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
0586 
0587     return 0;
0588 }
0589 
0590 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
0591 {
0592     struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
0593     struct adv7180_state *state = to_state(sd);
0594     int ret = mutex_lock_interruptible(&state->mutex);
0595     int val;
0596 
0597     if (ret)
0598         return ret;
0599     val = ctrl->val;
0600     switch (ctrl->id) {
0601     case V4L2_CID_BRIGHTNESS:
0602         ret = adv7180_write(state, ADV7180_REG_BRI, val);
0603         break;
0604     case V4L2_CID_HUE:
0605         /*Hue is inverted according to HSL chart */
0606         ret = adv7180_write(state, ADV7180_REG_HUE, -val);
0607         break;
0608     case V4L2_CID_CONTRAST:
0609         ret = adv7180_write(state, ADV7180_REG_CON, val);
0610         break;
0611     case V4L2_CID_SATURATION:
0612         /*
0613          *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
0614          *Let's not confuse the user, everybody understands saturation
0615          */
0616         ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
0617         if (ret < 0)
0618             break;
0619         ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
0620         break;
0621     case V4L2_CID_ADV_FAST_SWITCH:
0622         if (ctrl->val) {
0623             /* ADI required write */
0624             adv7180_write(state, 0x80d9, 0x44);
0625             adv7180_write(state, ADV7180_REG_FLCONTROL,
0626                 ADV7180_FLCONTROL_FL_ENABLE);
0627         } else {
0628             /* ADI required write */
0629             adv7180_write(state, 0x80d9, 0xc4);
0630             adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
0631         }
0632         break;
0633     case V4L2_CID_TEST_PATTERN:
0634         ret = adv7180_test_pattern(state, val);
0635         break;
0636     default:
0637         ret = -EINVAL;
0638     }
0639 
0640     mutex_unlock(&state->mutex);
0641     return ret;
0642 }
0643 
0644 static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
0645     .s_ctrl = adv7180_s_ctrl,
0646 };
0647 
0648 static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
0649     .ops = &adv7180_ctrl_ops,
0650     .id = V4L2_CID_ADV_FAST_SWITCH,
0651     .name = "Fast Switching",
0652     .type = V4L2_CTRL_TYPE_BOOLEAN,
0653     .min = 0,
0654     .max = 1,
0655     .step = 1,
0656 };
0657 
0658 static int adv7180_init_controls(struct adv7180_state *state)
0659 {
0660     v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
0661 
0662     v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
0663               V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
0664               ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
0665     v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
0666               V4L2_CID_CONTRAST, ADV7180_CON_MIN,
0667               ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
0668     v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
0669               V4L2_CID_SATURATION, ADV7180_SAT_MIN,
0670               ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
0671     v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
0672               V4L2_CID_HUE, ADV7180_HUE_MIN,
0673               ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
0674     v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
0675 
0676     v4l2_ctrl_new_std_menu_items(&state->ctrl_hdl, &adv7180_ctrl_ops,
0677                       V4L2_CID_TEST_PATTERN,
0678                       ARRAY_SIZE(test_pattern_menu) - 1,
0679                       0, ARRAY_SIZE(test_pattern_menu) - 1,
0680                       test_pattern_menu);
0681 
0682     state->sd.ctrl_handler = &state->ctrl_hdl;
0683     if (state->ctrl_hdl.error) {
0684         int err = state->ctrl_hdl.error;
0685 
0686         v4l2_ctrl_handler_free(&state->ctrl_hdl);
0687         return err;
0688     }
0689     v4l2_ctrl_handler_setup(&state->ctrl_hdl);
0690 
0691     return 0;
0692 }
0693 static void adv7180_exit_controls(struct adv7180_state *state)
0694 {
0695     v4l2_ctrl_handler_free(&state->ctrl_hdl);
0696 }
0697 
0698 static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
0699                   struct v4l2_subdev_state *sd_state,
0700                   struct v4l2_subdev_mbus_code_enum *code)
0701 {
0702     if (code->index != 0)
0703         return -EINVAL;
0704 
0705     code->code = MEDIA_BUS_FMT_UYVY8_2X8;
0706 
0707     return 0;
0708 }
0709 
0710 static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
0711                 struct v4l2_mbus_framefmt *fmt)
0712 {
0713     struct adv7180_state *state = to_state(sd);
0714 
0715     fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
0716     fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
0717     fmt->width = 720;
0718     fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
0719 
0720     if (state->field == V4L2_FIELD_ALTERNATE)
0721         fmt->height /= 2;
0722 
0723     return 0;
0724 }
0725 
0726 static int adv7180_set_field_mode(struct adv7180_state *state)
0727 {
0728     if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
0729         return 0;
0730 
0731     if (state->field == V4L2_FIELD_NONE) {
0732         if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
0733             adv7180_csi_write(state, 0x01, 0x20);
0734             adv7180_csi_write(state, 0x02, 0x28);
0735             adv7180_csi_write(state, 0x03, 0x38);
0736             adv7180_csi_write(state, 0x04, 0x30);
0737             adv7180_csi_write(state, 0x05, 0x30);
0738             adv7180_csi_write(state, 0x06, 0x80);
0739             adv7180_csi_write(state, 0x07, 0x70);
0740             adv7180_csi_write(state, 0x08, 0x50);
0741         }
0742         adv7180_vpp_write(state, 0xa3, 0x00);
0743         adv7180_vpp_write(state, 0x5b, 0x00);
0744         adv7180_vpp_write(state, 0x55, 0x80);
0745     } else {
0746         if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
0747             adv7180_csi_write(state, 0x01, 0x18);
0748             adv7180_csi_write(state, 0x02, 0x18);
0749             adv7180_csi_write(state, 0x03, 0x30);
0750             adv7180_csi_write(state, 0x04, 0x20);
0751             adv7180_csi_write(state, 0x05, 0x28);
0752             adv7180_csi_write(state, 0x06, 0x40);
0753             adv7180_csi_write(state, 0x07, 0x58);
0754             adv7180_csi_write(state, 0x08, 0x30);
0755         }
0756         adv7180_vpp_write(state, 0xa3, 0x70);
0757         adv7180_vpp_write(state, 0x5b, 0x80);
0758         adv7180_vpp_write(state, 0x55, 0x00);
0759     }
0760 
0761     return 0;
0762 }
0763 
0764 static int adv7180_get_pad_format(struct v4l2_subdev *sd,
0765                   struct v4l2_subdev_state *sd_state,
0766                   struct v4l2_subdev_format *format)
0767 {
0768     struct adv7180_state *state = to_state(sd);
0769 
0770     if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
0771         format->format = *v4l2_subdev_get_try_format(sd, sd_state, 0);
0772     } else {
0773         adv7180_mbus_fmt(sd, &format->format);
0774         format->format.field = state->field;
0775     }
0776 
0777     return 0;
0778 }
0779 
0780 static int adv7180_set_pad_format(struct v4l2_subdev *sd,
0781                   struct v4l2_subdev_state *sd_state,
0782                   struct v4l2_subdev_format *format)
0783 {
0784     struct adv7180_state *state = to_state(sd);
0785     struct v4l2_mbus_framefmt *framefmt;
0786     int ret;
0787 
0788     switch (format->format.field) {
0789     case V4L2_FIELD_NONE:
0790         if (state->chip_info->flags & ADV7180_FLAG_I2P)
0791             break;
0792         fallthrough;
0793     default:
0794         format->format.field = V4L2_FIELD_ALTERNATE;
0795         break;
0796     }
0797 
0798     ret = adv7180_mbus_fmt(sd,  &format->format);
0799 
0800     if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
0801         if (state->field != format->format.field) {
0802             state->field = format->format.field;
0803             adv7180_set_power(state, false);
0804             adv7180_set_field_mode(state);
0805             adv7180_set_power(state, true);
0806         }
0807     } else {
0808         framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0);
0809         *framefmt = format->format;
0810     }
0811 
0812     return ret;
0813 }
0814 
0815 static int adv7180_init_cfg(struct v4l2_subdev *sd,
0816                 struct v4l2_subdev_state *sd_state)
0817 {
0818     struct v4l2_subdev_format fmt = {
0819         .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY
0820         : V4L2_SUBDEV_FORMAT_ACTIVE,
0821     };
0822 
0823     return adv7180_set_pad_format(sd, sd_state, &fmt);
0824 }
0825 
0826 static int adv7180_get_mbus_config(struct v4l2_subdev *sd,
0827                    unsigned int pad,
0828                    struct v4l2_mbus_config *cfg)
0829 {
0830     struct adv7180_state *state = to_state(sd);
0831 
0832     if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
0833         cfg->type = V4L2_MBUS_CSI2_DPHY;
0834         cfg->bus.mipi_csi2.num_data_lanes = 1;
0835         cfg->bus.mipi_csi2.flags = 0;
0836     } else {
0837         /*
0838          * The ADV7180 sensor supports BT.601/656 output modes.
0839          * The BT.656 is default and not yet configurable by s/w.
0840          */
0841         cfg->bus.parallel.flags = V4L2_MBUS_MASTER |
0842                       V4L2_MBUS_PCLK_SAMPLE_RISING |
0843                       V4L2_MBUS_DATA_ACTIVE_HIGH;
0844         cfg->type = V4L2_MBUS_BT656;
0845     }
0846 
0847     return 0;
0848 }
0849 
0850 static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
0851 {
0852     *frames = ADV7180_NUM_OF_SKIP_FRAMES;
0853 
0854     return 0;
0855 }
0856 
0857 static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect)
0858 {
0859     struct adv7180_state *state = to_state(sd);
0860 
0861     if (state->curr_norm & V4L2_STD_525_60) {
0862         aspect->numerator = 11;
0863         aspect->denominator = 10;
0864     } else {
0865         aspect->numerator = 54;
0866         aspect->denominator = 59;
0867     }
0868 
0869     return 0;
0870 }
0871 
0872 static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
0873 {
0874     *norm = V4L2_STD_ALL;
0875     return 0;
0876 }
0877 
0878 static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
0879 {
0880     struct adv7180_state *state = to_state(sd);
0881     int ret;
0882 
0883     /* It's always safe to stop streaming, no need to take the lock */
0884     if (!enable) {
0885         state->streaming = enable;
0886         return 0;
0887     }
0888 
0889     /* Must wait until querystd released the lock */
0890     ret = mutex_lock_interruptible(&state->mutex);
0891     if (ret)
0892         return ret;
0893     state->streaming = enable;
0894     mutex_unlock(&state->mutex);
0895     return 0;
0896 }
0897 
0898 static int adv7180_subscribe_event(struct v4l2_subdev *sd,
0899                    struct v4l2_fh *fh,
0900                    struct v4l2_event_subscription *sub)
0901 {
0902     switch (sub->type) {
0903     case V4L2_EVENT_SOURCE_CHANGE:
0904         return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
0905     case V4L2_EVENT_CTRL:
0906         return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
0907     default:
0908         return -EINVAL;
0909     }
0910 }
0911 
0912 static const struct v4l2_subdev_video_ops adv7180_video_ops = {
0913     .s_std = adv7180_s_std,
0914     .g_std = adv7180_g_std,
0915     .g_frame_interval = adv7180_g_frame_interval,
0916     .querystd = adv7180_querystd,
0917     .g_input_status = adv7180_g_input_status,
0918     .s_routing = adv7180_s_routing,
0919     .g_pixelaspect = adv7180_g_pixelaspect,
0920     .g_tvnorms = adv7180_g_tvnorms,
0921     .s_stream = adv7180_s_stream,
0922 };
0923 
0924 static const struct v4l2_subdev_core_ops adv7180_core_ops = {
0925     .s_power = adv7180_s_power,
0926     .subscribe_event = adv7180_subscribe_event,
0927     .unsubscribe_event = v4l2_event_subdev_unsubscribe,
0928 };
0929 
0930 static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
0931     .init_cfg = adv7180_init_cfg,
0932     .enum_mbus_code = adv7180_enum_mbus_code,
0933     .set_fmt = adv7180_set_pad_format,
0934     .get_fmt = adv7180_get_pad_format,
0935     .get_mbus_config = adv7180_get_mbus_config,
0936 };
0937 
0938 static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = {
0939     .g_skip_frames = adv7180_get_skip_frames,
0940 };
0941 
0942 static const struct v4l2_subdev_ops adv7180_ops = {
0943     .core = &adv7180_core_ops,
0944     .video = &adv7180_video_ops,
0945     .pad = &adv7180_pad_ops,
0946     .sensor = &adv7180_sensor_ops,
0947 };
0948 
0949 static irqreturn_t adv7180_irq(int irq, void *devid)
0950 {
0951     struct adv7180_state *state = devid;
0952     u8 isr3;
0953 
0954     mutex_lock(&state->mutex);
0955     isr3 = adv7180_read(state, ADV7180_REG_ISR3);
0956     /* clear */
0957     adv7180_write(state, ADV7180_REG_ICR3, isr3);
0958 
0959     if (isr3 & ADV7180_IRQ3_AD_CHANGE) {
0960         static const struct v4l2_event src_ch = {
0961             .type = V4L2_EVENT_SOURCE_CHANGE,
0962             .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
0963         };
0964 
0965         v4l2_subdev_notify_event(&state->sd, &src_ch);
0966     }
0967     mutex_unlock(&state->mutex);
0968 
0969     return IRQ_HANDLED;
0970 }
0971 
0972 static int adv7180_init(struct adv7180_state *state)
0973 {
0974     int ret;
0975 
0976     /* ITU-R BT.656-4 compatible */
0977     ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
0978             ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
0979     if (ret < 0)
0980         return ret;
0981 
0982     /* Manually set V bit end position in NTSC mode */
0983     return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
0984                     ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
0985 }
0986 
0987 static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
0988 {
0989     return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
0990         (std << 4) | state->input);
0991 }
0992 
0993 static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
0994 {
0995     int ret;
0996 
0997     ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
0998     if (ret < 0)
0999         return ret;
1000 
1001     ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
1002     ret |= input;
1003     return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
1004 }
1005 
1006 static int adv7182_init(struct adv7180_state *state)
1007 {
1008     if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
1009         adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
1010             ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
1011 
1012     if (state->chip_info->flags & ADV7180_FLAG_I2P)
1013         adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
1014             ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
1015 
1016     if (state->chip_info->flags & ADV7180_FLAG_V2) {
1017         /* ADI recommended writes for improved video quality */
1018         adv7180_write(state, 0x0080, 0x51);
1019         adv7180_write(state, 0x0081, 0x51);
1020         adv7180_write(state, 0x0082, 0x68);
1021     }
1022 
1023     /* ADI required writes */
1024     if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1025         adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);
1026         adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
1027         adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
1028     } else {
1029         if (state->chip_info->flags & ADV7180_FLAG_V2) {
1030             if (state->force_bt656_4) {
1031                 /* ITU-R BT.656-4 compatible */
1032                 adv7180_write(state,
1033                           ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1034                           ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
1035                 /* Manually set NEWAVMODE */
1036                 adv7180_write(state,
1037                           ADV7180_REG_VSYNC_FIELD_CTL_1,
1038                           ADV7180_VSYNC_FIELD_CTL_1_NEWAV);
1039                 /* Manually set V bit end position in NTSC mode */
1040                 adv7180_write(state,
1041                           ADV7180_REG_NTSC_V_BIT_END,
1042                           ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
1043             } else {
1044                 adv7180_write(state,
1045                           ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1046                           0x17);
1047             }
1048         }
1049         else
1050             adv7180_write(state,
1051                       ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1052                       0x07);
1053         adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);
1054         adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);
1055     }
1056 
1057     adv7180_write(state, 0x0013, 0x00);
1058 
1059     return 0;
1060 }
1061 
1062 static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
1063 {
1064     /* Failing to set the reserved bit can result in increased video noise */
1065     return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL,
1066                  (std << 4) | ADV7182_REG_INPUT_RESERVED);
1067 }
1068 
1069 enum adv7182_input_type {
1070     ADV7182_INPUT_TYPE_CVBS,
1071     ADV7182_INPUT_TYPE_DIFF_CVBS,
1072     ADV7182_INPUT_TYPE_SVIDEO,
1073     ADV7182_INPUT_TYPE_YPBPR,
1074 };
1075 
1076 static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
1077 {
1078     switch (input) {
1079     case ADV7182_INPUT_CVBS_AIN1:
1080     case ADV7182_INPUT_CVBS_AIN2:
1081     case ADV7182_INPUT_CVBS_AIN3:
1082     case ADV7182_INPUT_CVBS_AIN4:
1083     case ADV7182_INPUT_CVBS_AIN5:
1084     case ADV7182_INPUT_CVBS_AIN6:
1085     case ADV7182_INPUT_CVBS_AIN7:
1086     case ADV7182_INPUT_CVBS_AIN8:
1087         return ADV7182_INPUT_TYPE_CVBS;
1088     case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
1089     case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
1090     case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
1091     case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
1092         return ADV7182_INPUT_TYPE_SVIDEO;
1093     case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
1094     case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
1095         return ADV7182_INPUT_TYPE_YPBPR;
1096     case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
1097     case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
1098     case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
1099     case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
1100         return ADV7182_INPUT_TYPE_DIFF_CVBS;
1101     default: /* Will never happen */
1102         return 0;
1103     }
1104 }
1105 
1106 /* ADI recommended writes to registers 0x52, 0x53, 0x54 */
1107 static unsigned int adv7182_lbias_settings[][3] = {
1108     [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
1109     [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1110     [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1111     [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1112 };
1113 
1114 static unsigned int adv7280_lbias_settings[][3] = {
1115     [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
1116     [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1117     [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1118     [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1119 };
1120 
1121 static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
1122 {
1123     enum adv7182_input_type input_type;
1124     unsigned int *lbias;
1125     unsigned int i;
1126     int ret;
1127 
1128     ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
1129     if (ret)
1130         return ret;
1131 
1132     /* Reset clamp circuitry - ADI recommended writes */
1133     adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);
1134     adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);
1135 
1136     input_type = adv7182_get_input_type(input);
1137 
1138     switch (input_type) {
1139     case ADV7182_INPUT_TYPE_CVBS:
1140     case ADV7182_INPUT_TYPE_DIFF_CVBS:
1141         /* ADI recommends to use the SH1 filter */
1142         adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);
1143         break;
1144     default:
1145         adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);
1146         break;
1147     }
1148 
1149     if (state->chip_info->flags & ADV7180_FLAG_V2)
1150         lbias = adv7280_lbias_settings[input_type];
1151     else
1152         lbias = adv7182_lbias_settings[input_type];
1153 
1154     for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
1155         adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
1156 
1157     if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
1158         /* ADI required writes to make differential CVBS work */
1159         adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
1160         adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
1161         adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
1162         adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
1163         adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
1164     } else {
1165         adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
1166         adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
1167         adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
1168         adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);
1169         adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);
1170     }
1171 
1172     return 0;
1173 }
1174 
1175 static const struct adv7180_chip_info adv7180_info = {
1176     .flags = ADV7180_FLAG_RESET_POWERED,
1177     /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
1178      * all inputs and let the card driver take care of validation
1179      */
1180     .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
1181         BIT(ADV7180_INPUT_CVBS_AIN2) |
1182         BIT(ADV7180_INPUT_CVBS_AIN3) |
1183         BIT(ADV7180_INPUT_CVBS_AIN4) |
1184         BIT(ADV7180_INPUT_CVBS_AIN5) |
1185         BIT(ADV7180_INPUT_CVBS_AIN6) |
1186         BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
1187         BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
1188         BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
1189         BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1190         BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
1191     .init = adv7180_init,
1192     .set_std = adv7180_set_std,
1193     .select_input = adv7180_select_input,
1194 };
1195 
1196 static const struct adv7180_chip_info adv7182_info = {
1197     .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1198         BIT(ADV7182_INPUT_CVBS_AIN2) |
1199         BIT(ADV7182_INPUT_CVBS_AIN3) |
1200         BIT(ADV7182_INPUT_CVBS_AIN4) |
1201         BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1202         BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1203         BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1204         BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1205         BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
1206     .init = adv7182_init,
1207     .set_std = adv7182_set_std,
1208     .select_input = adv7182_select_input,
1209 };
1210 
1211 static const struct adv7180_chip_info adv7280_info = {
1212     .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
1213     .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1214         BIT(ADV7182_INPUT_CVBS_AIN2) |
1215         BIT(ADV7182_INPUT_CVBS_AIN3) |
1216         BIT(ADV7182_INPUT_CVBS_AIN4) |
1217         BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1218         BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1219         BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
1220     .init = adv7182_init,
1221     .set_std = adv7182_set_std,
1222     .select_input = adv7182_select_input,
1223 };
1224 
1225 static const struct adv7180_chip_info adv7280_m_info = {
1226     .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
1227     .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1228         BIT(ADV7182_INPUT_CVBS_AIN2) |
1229         BIT(ADV7182_INPUT_CVBS_AIN3) |
1230         BIT(ADV7182_INPUT_CVBS_AIN4) |
1231         BIT(ADV7182_INPUT_CVBS_AIN5) |
1232         BIT(ADV7182_INPUT_CVBS_AIN6) |
1233         BIT(ADV7182_INPUT_CVBS_AIN7) |
1234         BIT(ADV7182_INPUT_CVBS_AIN8) |
1235         BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1236         BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1237         BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1238         BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1239         BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1240         BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
1241     .init = adv7182_init,
1242     .set_std = adv7182_set_std,
1243     .select_input = adv7182_select_input,
1244 };
1245 
1246 static const struct adv7180_chip_info adv7281_info = {
1247     .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
1248     .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1249         BIT(ADV7182_INPUT_CVBS_AIN2) |
1250         BIT(ADV7182_INPUT_CVBS_AIN7) |
1251         BIT(ADV7182_INPUT_CVBS_AIN8) |
1252         BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1253         BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1254         BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1255         BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1256     .init = adv7182_init,
1257     .set_std = adv7182_set_std,
1258     .select_input = adv7182_select_input,
1259 };
1260 
1261 static const struct adv7180_chip_info adv7281_m_info = {
1262     .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
1263     .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1264         BIT(ADV7182_INPUT_CVBS_AIN2) |
1265         BIT(ADV7182_INPUT_CVBS_AIN3) |
1266         BIT(ADV7182_INPUT_CVBS_AIN4) |
1267         BIT(ADV7182_INPUT_CVBS_AIN7) |
1268         BIT(ADV7182_INPUT_CVBS_AIN8) |
1269         BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1270         BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1271         BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1272         BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1273         BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1274         BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1275         BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1276     .init = adv7182_init,
1277     .set_std = adv7182_set_std,
1278     .select_input = adv7182_select_input,
1279 };
1280 
1281 static const struct adv7180_chip_info adv7281_ma_info = {
1282     .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
1283     .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1284         BIT(ADV7182_INPUT_CVBS_AIN2) |
1285         BIT(ADV7182_INPUT_CVBS_AIN3) |
1286         BIT(ADV7182_INPUT_CVBS_AIN4) |
1287         BIT(ADV7182_INPUT_CVBS_AIN5) |
1288         BIT(ADV7182_INPUT_CVBS_AIN6) |
1289         BIT(ADV7182_INPUT_CVBS_AIN7) |
1290         BIT(ADV7182_INPUT_CVBS_AIN8) |
1291         BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1292         BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1293         BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1294         BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1295         BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1296         BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
1297         BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1298         BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1299         BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
1300         BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1301     .init = adv7182_init,
1302     .set_std = adv7182_set_std,
1303     .select_input = adv7182_select_input,
1304 };
1305 
1306 static const struct adv7180_chip_info adv7282_info = {
1307     .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
1308     .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1309         BIT(ADV7182_INPUT_CVBS_AIN2) |
1310         BIT(ADV7182_INPUT_CVBS_AIN7) |
1311         BIT(ADV7182_INPUT_CVBS_AIN8) |
1312         BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1313         BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1314         BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1315         BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1316     .init = adv7182_init,
1317     .set_std = adv7182_set_std,
1318     .select_input = adv7182_select_input,
1319 };
1320 
1321 static const struct adv7180_chip_info adv7282_m_info = {
1322     .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
1323     .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1324         BIT(ADV7182_INPUT_CVBS_AIN2) |
1325         BIT(ADV7182_INPUT_CVBS_AIN3) |
1326         BIT(ADV7182_INPUT_CVBS_AIN4) |
1327         BIT(ADV7182_INPUT_CVBS_AIN7) |
1328         BIT(ADV7182_INPUT_CVBS_AIN8) |
1329         BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1330         BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1331         BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1332         BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1333         BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1334         BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1335     .init = adv7182_init,
1336     .set_std = adv7182_set_std,
1337     .select_input = adv7182_select_input,
1338 };
1339 
1340 static int init_device(struct adv7180_state *state)
1341 {
1342     int ret;
1343 
1344     mutex_lock(&state->mutex);
1345 
1346     adv7180_set_power_pin(state, true);
1347     adv7180_set_reset_pin(state, false);
1348 
1349     adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
1350     usleep_range(5000, 10000);
1351 
1352     ret = state->chip_info->init(state);
1353     if (ret)
1354         goto out_unlock;
1355 
1356     ret = adv7180_program_std(state);
1357     if (ret)
1358         goto out_unlock;
1359 
1360     adv7180_set_field_mode(state);
1361 
1362     /* register for interrupts */
1363     if (state->irq > 0) {
1364         /* config the Interrupt pin to be active low */
1365         ret = adv7180_write(state, ADV7180_REG_ICONF1,
1366                         ADV7180_ICONF1_ACTIVE_LOW |
1367                         ADV7180_ICONF1_PSYNC_ONLY);
1368         if (ret < 0)
1369             goto out_unlock;
1370 
1371         ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
1372         if (ret < 0)
1373             goto out_unlock;
1374 
1375         ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
1376         if (ret < 0)
1377             goto out_unlock;
1378 
1379         /* enable AD change interrupts interrupts */
1380         ret = adv7180_write(state, ADV7180_REG_IMR3,
1381                         ADV7180_IRQ3_AD_CHANGE);
1382         if (ret < 0)
1383             goto out_unlock;
1384 
1385         ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
1386         if (ret < 0)
1387             goto out_unlock;
1388     }
1389 
1390 out_unlock:
1391     mutex_unlock(&state->mutex);
1392 
1393     return ret;
1394 }
1395 
1396 static int adv7180_probe(struct i2c_client *client,
1397              const struct i2c_device_id *id)
1398 {
1399     struct device_node *np = client->dev.of_node;
1400     struct adv7180_state *state;
1401     struct v4l2_subdev *sd;
1402     int ret;
1403 
1404     /* Check if the adapter supports the needed features */
1405     if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1406         return -EIO;
1407 
1408     state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1409     if (state == NULL)
1410         return -ENOMEM;
1411 
1412     state->client = client;
1413     state->field = V4L2_FIELD_ALTERNATE;
1414     state->chip_info = (struct adv7180_chip_info *)id->driver_data;
1415 
1416     state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1417                            GPIOD_OUT_HIGH);
1418     if (IS_ERR(state->pwdn_gpio)) {
1419         ret = PTR_ERR(state->pwdn_gpio);
1420         v4l_err(client, "request for power pin failed: %d\n", ret);
1421         return ret;
1422     }
1423 
1424     state->rst_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1425                           GPIOD_OUT_HIGH);
1426     if (IS_ERR(state->rst_gpio)) {
1427         ret = PTR_ERR(state->rst_gpio);
1428         v4l_err(client, "request for reset pin failed: %d\n", ret);
1429         return ret;
1430     }
1431 
1432     if (of_property_read_bool(np, "adv,force-bt656-4"))
1433         state->force_bt656_4 = true;
1434 
1435     if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1436         state->csi_client = i2c_new_dummy_device(client->adapter,
1437                 ADV7180_DEFAULT_CSI_I2C_ADDR);
1438         if (IS_ERR(state->csi_client))
1439             return PTR_ERR(state->csi_client);
1440     }
1441 
1442     if (state->chip_info->flags & ADV7180_FLAG_I2P) {
1443         state->vpp_client = i2c_new_dummy_device(client->adapter,
1444                 ADV7180_DEFAULT_VPP_I2C_ADDR);
1445         if (IS_ERR(state->vpp_client)) {
1446             ret = PTR_ERR(state->vpp_client);
1447             goto err_unregister_csi_client;
1448         }
1449     }
1450 
1451     state->irq = client->irq;
1452     mutex_init(&state->mutex);
1453     state->curr_norm = V4L2_STD_NTSC;
1454     if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
1455         state->powered = true;
1456     else
1457         state->powered = false;
1458     state->input = 0;
1459     sd = &state->sd;
1460     v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
1461     sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1462 
1463     ret = adv7180_init_controls(state);
1464     if (ret)
1465         goto err_unregister_vpp_client;
1466 
1467     state->pad.flags = MEDIA_PAD_FL_SOURCE;
1468     sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
1469     ret = media_entity_pads_init(&sd->entity, 1, &state->pad);
1470     if (ret)
1471         goto err_free_ctrl;
1472 
1473     ret = init_device(state);
1474     if (ret)
1475         goto err_media_entity_cleanup;
1476 
1477     if (state->irq) {
1478         ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
1479                        IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
1480                        KBUILD_MODNAME, state);
1481         if (ret)
1482             goto err_media_entity_cleanup;
1483     }
1484 
1485     ret = v4l2_async_register_subdev(sd);
1486     if (ret)
1487         goto err_free_irq;
1488 
1489     mutex_lock(&state->mutex);
1490     ret = adv7180_read(state, ADV7180_REG_IDENT);
1491     mutex_unlock(&state->mutex);
1492     if (ret < 0)
1493         goto err_v4l2_async_unregister;
1494 
1495     v4l_info(client, "chip id 0x%x found @ 0x%02x (%s)\n",
1496          ret, client->addr, client->adapter->name);
1497 
1498     return 0;
1499 
1500 err_v4l2_async_unregister:
1501     v4l2_async_unregister_subdev(sd);
1502 err_free_irq:
1503     if (state->irq > 0)
1504         free_irq(client->irq, state);
1505 err_media_entity_cleanup:
1506     media_entity_cleanup(&sd->entity);
1507 err_free_ctrl:
1508     adv7180_exit_controls(state);
1509 err_unregister_vpp_client:
1510     i2c_unregister_device(state->vpp_client);
1511 err_unregister_csi_client:
1512     i2c_unregister_device(state->csi_client);
1513     mutex_destroy(&state->mutex);
1514     return ret;
1515 }
1516 
1517 static int adv7180_remove(struct i2c_client *client)
1518 {
1519     struct v4l2_subdev *sd = i2c_get_clientdata(client);
1520     struct adv7180_state *state = to_state(sd);
1521 
1522     v4l2_async_unregister_subdev(sd);
1523 
1524     if (state->irq > 0)
1525         free_irq(client->irq, state);
1526 
1527     media_entity_cleanup(&sd->entity);
1528     adv7180_exit_controls(state);
1529 
1530     i2c_unregister_device(state->vpp_client);
1531     i2c_unregister_device(state->csi_client);
1532 
1533     adv7180_set_reset_pin(state, true);
1534     adv7180_set_power_pin(state, false);
1535 
1536     mutex_destroy(&state->mutex);
1537 
1538     return 0;
1539 }
1540 
1541 static const struct i2c_device_id adv7180_id[] = {
1542     { "adv7180", (kernel_ulong_t)&adv7180_info },
1543     { "adv7180cp", (kernel_ulong_t)&adv7180_info },
1544     { "adv7180st", (kernel_ulong_t)&adv7180_info },
1545     { "adv7182", (kernel_ulong_t)&adv7182_info },
1546     { "adv7280", (kernel_ulong_t)&adv7280_info },
1547     { "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
1548     { "adv7281", (kernel_ulong_t)&adv7281_info },
1549     { "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
1550     { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
1551     { "adv7282", (kernel_ulong_t)&adv7282_info },
1552     { "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
1553     {},
1554 };
1555 MODULE_DEVICE_TABLE(i2c, adv7180_id);
1556 
1557 #ifdef CONFIG_PM_SLEEP
1558 static int adv7180_suspend(struct device *dev)
1559 {
1560     struct v4l2_subdev *sd = dev_get_drvdata(dev);
1561     struct adv7180_state *state = to_state(sd);
1562 
1563     return adv7180_set_power(state, false);
1564 }
1565 
1566 static int adv7180_resume(struct device *dev)
1567 {
1568     struct v4l2_subdev *sd = dev_get_drvdata(dev);
1569     struct adv7180_state *state = to_state(sd);
1570     int ret;
1571 
1572     ret = init_device(state);
1573     if (ret < 0)
1574         return ret;
1575 
1576     ret = adv7180_set_power(state, state->powered);
1577     if (ret)
1578         return ret;
1579 
1580     return 0;
1581 }
1582 
1583 static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
1584 #define ADV7180_PM_OPS (&adv7180_pm_ops)
1585 
1586 #else
1587 #define ADV7180_PM_OPS NULL
1588 #endif
1589 
1590 #ifdef CONFIG_OF
1591 static const struct of_device_id adv7180_of_id[] = {
1592     { .compatible = "adi,adv7180", },
1593     { .compatible = "adi,adv7180cp", },
1594     { .compatible = "adi,adv7180st", },
1595     { .compatible = "adi,adv7182", },
1596     { .compatible = "adi,adv7280", },
1597     { .compatible = "adi,adv7280-m", },
1598     { .compatible = "adi,adv7281", },
1599     { .compatible = "adi,adv7281-m", },
1600     { .compatible = "adi,adv7281-ma", },
1601     { .compatible = "adi,adv7282", },
1602     { .compatible = "adi,adv7282-m", },
1603     { },
1604 };
1605 
1606 MODULE_DEVICE_TABLE(of, adv7180_of_id);
1607 #endif
1608 
1609 static struct i2c_driver adv7180_driver = {
1610     .driver = {
1611            .name = KBUILD_MODNAME,
1612            .pm = ADV7180_PM_OPS,
1613            .of_match_table = of_match_ptr(adv7180_of_id),
1614            },
1615     .probe = adv7180_probe,
1616     .remove = adv7180_remove,
1617     .id_table = adv7180_id,
1618 };
1619 
1620 module_i2c_driver(adv7180_driver);
1621 
1622 MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
1623 MODULE_AUTHOR("Mocean Laboratories");
1624 MODULE_LICENSE("GPL v2");
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