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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Analog Devices AD9389B/AD9889B video encoder driver
0004  *
0005  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
0006  */
0007 
0008 /*
0009  * References (c = chapter, p = page):
0010  * REF_01 - Analog Devices, Programming Guide, AD9889B/AD9389B,
0011  * HDMI Transitter, Rev. A, October 2010
0012  */
0013 
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/slab.h>
0017 #include <linux/i2c.h>
0018 #include <linux/delay.h>
0019 #include <linux/videodev2.h>
0020 #include <linux/workqueue.h>
0021 #include <linux/v4l2-dv-timings.h>
0022 #include <media/v4l2-device.h>
0023 #include <media/v4l2-common.h>
0024 #include <media/v4l2-dv-timings.h>
0025 #include <media/v4l2-ctrls.h>
0026 #include <media/i2c/ad9389b.h>
0027 
0028 static int debug;
0029 module_param(debug, int, 0644);
0030 MODULE_PARM_DESC(debug, "debug level (0-2)");
0031 
0032 MODULE_DESCRIPTION("Analog Devices AD9389B/AD9889B video encoder driver");
0033 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
0034 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
0035 MODULE_LICENSE("GPL");
0036 
0037 #define MASK_AD9389B_EDID_RDY_INT   0x04
0038 #define MASK_AD9389B_MSEN_INT       0x40
0039 #define MASK_AD9389B_HPD_INT        0x80
0040 
0041 #define MASK_AD9389B_HPD_DETECT     0x40
0042 #define MASK_AD9389B_MSEN_DETECT    0x20
0043 #define MASK_AD9389B_EDID_RDY       0x10
0044 
0045 #define EDID_MAX_RETRIES (8)
0046 #define EDID_DELAY 250
0047 #define EDID_MAX_SEGM 8
0048 
0049 /*
0050 **********************************************************************
0051 *
0052 *  Arrays with configuration parameters for the AD9389B
0053 *
0054 **********************************************************************
0055 */
0056 
0057 struct ad9389b_state_edid {
0058     /* total number of blocks */
0059     u32 blocks;
0060     /* Number of segments read */
0061     u32 segments;
0062     u8 data[EDID_MAX_SEGM * 256];
0063     /* Number of EDID read retries left */
0064     unsigned read_retries;
0065 };
0066 
0067 struct ad9389b_state {
0068     struct ad9389b_platform_data pdata;
0069     struct v4l2_subdev sd;
0070     struct media_pad pad;
0071     struct v4l2_ctrl_handler hdl;
0072     int chip_revision;
0073     /* Is the ad9389b powered on? */
0074     bool power_on;
0075     /* Did we receive hotplug and rx-sense signals? */
0076     bool have_monitor;
0077     /* timings from s_dv_timings */
0078     struct v4l2_dv_timings dv_timings;
0079     /* controls */
0080     struct v4l2_ctrl *hdmi_mode_ctrl;
0081     struct v4l2_ctrl *hotplug_ctrl;
0082     struct v4l2_ctrl *rx_sense_ctrl;
0083     struct v4l2_ctrl *have_edid0_ctrl;
0084     struct v4l2_ctrl *rgb_quantization_range_ctrl;
0085     struct i2c_client *edid_i2c_client;
0086     struct ad9389b_state_edid edid;
0087     /* Running counter of the number of detected EDIDs (for debugging) */
0088     unsigned edid_detect_counter;
0089     struct delayed_work edid_handler; /* work entry */
0090 };
0091 
0092 static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd);
0093 static bool ad9389b_check_edid_status(struct v4l2_subdev *sd);
0094 static void ad9389b_setup(struct v4l2_subdev *sd);
0095 static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
0096 static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
0097 
0098 static inline struct ad9389b_state *get_ad9389b_state(struct v4l2_subdev *sd)
0099 {
0100     return container_of(sd, struct ad9389b_state, sd);
0101 }
0102 
0103 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
0104 {
0105     return &container_of(ctrl->handler, struct ad9389b_state, hdl)->sd;
0106 }
0107 
0108 /* ------------------------ I2C ----------------------------------------------- */
0109 
0110 static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg)
0111 {
0112     struct i2c_client *client = v4l2_get_subdevdata(sd);
0113 
0114     return i2c_smbus_read_byte_data(client, reg);
0115 }
0116 
0117 static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
0118 {
0119     struct i2c_client *client = v4l2_get_subdevdata(sd);
0120     int ret;
0121     int i;
0122 
0123     for (i = 0; i < 3; i++) {
0124         ret = i2c_smbus_write_byte_data(client, reg, val);
0125         if (ret == 0)
0126             return 0;
0127     }
0128     v4l2_err(sd, "%s: failed reg 0x%x, val 0x%x\n", __func__, reg, val);
0129     return ret;
0130 }
0131 
0132 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
0133    and then the value-mask (to be OR-ed). */
0134 static inline void ad9389b_wr_and_or(struct v4l2_subdev *sd, u8 reg,
0135                      u8 clr_mask, u8 val_mask)
0136 {
0137     ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask);
0138 }
0139 
0140 static void ad9389b_edid_rd(struct v4l2_subdev *sd, u16 len, u8 *buf)
0141 {
0142     struct ad9389b_state *state = get_ad9389b_state(sd);
0143     int i;
0144 
0145     v4l2_dbg(1, debug, sd, "%s:\n", __func__);
0146 
0147     for (i = 0; i < len; i++)
0148         buf[i] = i2c_smbus_read_byte_data(state->edid_i2c_client, i);
0149 }
0150 
0151 static inline bool ad9389b_have_hotplug(struct v4l2_subdev *sd)
0152 {
0153     return ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT;
0154 }
0155 
0156 static inline bool ad9389b_have_rx_sense(struct v4l2_subdev *sd)
0157 {
0158     return ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT;
0159 }
0160 
0161 static void ad9389b_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
0162 {
0163     ad9389b_wr_and_or(sd, 0x17, 0xe7, (mode & 0x3)<<3);
0164     ad9389b_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
0165 }
0166 
0167 static void ad9389b_csc_coeff(struct v4l2_subdev *sd,
0168                   u16 A1, u16 A2, u16 A3, u16 A4,
0169                   u16 B1, u16 B2, u16 B3, u16 B4,
0170                   u16 C1, u16 C2, u16 C3, u16 C4)
0171 {
0172     /* A */
0173     ad9389b_wr_and_or(sd, 0x18, 0xe0, A1>>8);
0174     ad9389b_wr(sd, 0x19, A1);
0175     ad9389b_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
0176     ad9389b_wr(sd, 0x1B, A2);
0177     ad9389b_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
0178     ad9389b_wr(sd, 0x1d, A3);
0179     ad9389b_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
0180     ad9389b_wr(sd, 0x1f, A4);
0181 
0182     /* B */
0183     ad9389b_wr_and_or(sd, 0x20, 0xe0, B1>>8);
0184     ad9389b_wr(sd, 0x21, B1);
0185     ad9389b_wr_and_or(sd, 0x22, 0xe0, B2>>8);
0186     ad9389b_wr(sd, 0x23, B2);
0187     ad9389b_wr_and_or(sd, 0x24, 0xe0, B3>>8);
0188     ad9389b_wr(sd, 0x25, B3);
0189     ad9389b_wr_and_or(sd, 0x26, 0xe0, B4>>8);
0190     ad9389b_wr(sd, 0x27, B4);
0191 
0192     /* C */
0193     ad9389b_wr_and_or(sd, 0x28, 0xe0, C1>>8);
0194     ad9389b_wr(sd, 0x29, C1);
0195     ad9389b_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
0196     ad9389b_wr(sd, 0x2B, C2);
0197     ad9389b_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
0198     ad9389b_wr(sd, 0x2D, C3);
0199     ad9389b_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
0200     ad9389b_wr(sd, 0x2F, C4);
0201 }
0202 
0203 static void ad9389b_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
0204 {
0205     if (enable) {
0206         u8 csc_mode = 0;
0207 
0208         ad9389b_csc_conversion_mode(sd, csc_mode);
0209         ad9389b_csc_coeff(sd,
0210                   4096-564, 0, 0, 256,
0211                   0, 4096-564, 0, 256,
0212                   0, 0, 4096-564, 256);
0213         /* enable CSC */
0214         ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x1);
0215         /* AVI infoframe: Limited range RGB (16-235) */
0216         ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x02);
0217     } else {
0218         /* disable CSC */
0219         ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x0);
0220         /* AVI infoframe: Full range RGB (0-255) */
0221         ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x04);
0222     }
0223 }
0224 
0225 static void ad9389b_set_IT_content_AVI_InfoFrame(struct v4l2_subdev *sd)
0226 {
0227     struct ad9389b_state *state = get_ad9389b_state(sd);
0228 
0229     if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
0230         /* CE format, not IT  */
0231         ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x00);
0232     } else {
0233         /* IT format */
0234         ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x40);
0235     }
0236 }
0237 
0238 static int ad9389b_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
0239 {
0240     struct ad9389b_state *state = get_ad9389b_state(sd);
0241 
0242     switch (ctrl->val) {
0243     case V4L2_DV_RGB_RANGE_AUTO:
0244         /* automatic */
0245         if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
0246             /* CE format, RGB limited range (16-235) */
0247             ad9389b_csc_rgb_full2limit(sd, true);
0248         } else {
0249             /* not CE format, RGB full range (0-255) */
0250             ad9389b_csc_rgb_full2limit(sd, false);
0251         }
0252         break;
0253     case V4L2_DV_RGB_RANGE_LIMITED:
0254         /* RGB limited range (16-235) */
0255         ad9389b_csc_rgb_full2limit(sd, true);
0256         break;
0257     case V4L2_DV_RGB_RANGE_FULL:
0258         /* RGB full range (0-255) */
0259         ad9389b_csc_rgb_full2limit(sd, false);
0260         break;
0261     default:
0262         return -EINVAL;
0263     }
0264     return 0;
0265 }
0266 
0267 static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)
0268 {
0269     u8 gear;
0270 
0271     /* Workaround for TMDS PLL problem
0272      * The TMDS PLL in AD9389b change gear when the chip is heated above a
0273      * certain temperature. The output is disabled when the PLL change gear
0274      * so the monitor has to lock on the signal again. A workaround for
0275      * this is to use the manual PLL gears. This is a solution from Analog
0276      * Devices that is not documented in the datasheets.
0277      * 0x98 [7] = enable manual gearing. 0x98 [6:4] = gear
0278      *
0279      * The pixel frequency ranges are based on readout of the gear the
0280      * automatic gearing selects for different pixel clocks
0281      * (read from 0x9e [3:1]).
0282      */
0283 
0284     if (pixelclock > 140000000)
0285         gear = 0xc0; /* 4th gear */
0286     else if (pixelclock > 117000000)
0287         gear = 0xb0; /* 3rd gear */
0288     else if (pixelclock > 87000000)
0289         gear = 0xa0; /* 2nd gear */
0290     else if (pixelclock > 60000000)
0291         gear = 0x90; /* 1st gear */
0292     else
0293         gear = 0x80; /* 0th gear */
0294 
0295     ad9389b_wr_and_or(sd, 0x98, 0x0f, gear);
0296 }
0297 
0298 /* ------------------------------ CTRL OPS ------------------------------ */
0299 
0300 static int ad9389b_s_ctrl(struct v4l2_ctrl *ctrl)
0301 {
0302     struct v4l2_subdev *sd = to_sd(ctrl);
0303     struct ad9389b_state *state = get_ad9389b_state(sd);
0304 
0305     v4l2_dbg(1, debug, sd,
0306          "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
0307 
0308     if (state->hdmi_mode_ctrl == ctrl) {
0309         /* Set HDMI or DVI-D */
0310         ad9389b_wr_and_or(sd, 0xaf, 0xfd,
0311                   ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
0312         return 0;
0313     }
0314     if (state->rgb_quantization_range_ctrl == ctrl)
0315         return ad9389b_set_rgb_quantization_mode(sd, ctrl);
0316     return -EINVAL;
0317 }
0318 
0319 static const struct v4l2_ctrl_ops ad9389b_ctrl_ops = {
0320     .s_ctrl = ad9389b_s_ctrl,
0321 };
0322 
0323 /* ---------------------------- CORE OPS ------------------------------------------- */
0324 
0325 #ifdef CONFIG_VIDEO_ADV_DEBUG
0326 static int ad9389b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
0327 {
0328     reg->val = ad9389b_rd(sd, reg->reg & 0xff);
0329     reg->size = 1;
0330     return 0;
0331 }
0332 
0333 static int ad9389b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
0334 {
0335     ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff);
0336     return 0;
0337 }
0338 #endif
0339 
0340 static int ad9389b_log_status(struct v4l2_subdev *sd)
0341 {
0342     struct ad9389b_state *state = get_ad9389b_state(sd);
0343     struct ad9389b_state_edid *edid = &state->edid;
0344 
0345     static const char * const states[] = {
0346         "in reset",
0347         "reading EDID",
0348         "idle",
0349         "initializing HDCP",
0350         "HDCP enabled",
0351         "initializing HDCP repeater",
0352         "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
0353     };
0354     static const char * const errors[] = {
0355         "no error",
0356         "bad receiver BKSV",
0357         "Ri mismatch",
0358         "Pj mismatch",
0359         "i2c error",
0360         "timed out",
0361         "max repeater cascade exceeded",
0362         "hash check failed",
0363         "too many devices",
0364         "9", "A", "B", "C", "D", "E", "F"
0365     };
0366 
0367     u8 manual_gear;
0368 
0369     v4l2_info(sd, "chip revision %d\n", state->chip_revision);
0370     v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
0371     v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
0372           (ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT) ?
0373           "detected" : "no",
0374           (ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT) ?
0375           "detected" : "no",
0376           edid->segments ? "found" : "no", edid->blocks);
0377     v4l2_info(sd, "%s output %s\n",
0378           (ad9389b_rd(sd, 0xaf) & 0x02) ?
0379           "HDMI" : "DVI-D",
0380           (ad9389b_rd(sd, 0xa1) & 0x3c) ?
0381           "disabled" : "enabled");
0382     v4l2_info(sd, "ad9389b: %s\n", (ad9389b_rd(sd, 0xb8) & 0x40) ?
0383           "encrypted" : "no encryption");
0384     v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
0385           states[ad9389b_rd(sd, 0xc8) & 0xf],
0386           errors[ad9389b_rd(sd, 0xc8) >> 4],
0387           state->edid_detect_counter,
0388           ad9389b_rd(sd, 0x94), ad9389b_rd(sd, 0x96));
0389     manual_gear = ad9389b_rd(sd, 0x98) & 0x80;
0390     v4l2_info(sd, "ad9389b: RGB quantization: %s range\n",
0391           ad9389b_rd(sd, 0x3b) & 0x01 ? "limited" : "full");
0392     v4l2_info(sd, "ad9389b: %s gear %d\n",
0393           manual_gear ? "manual" : "automatic",
0394           manual_gear ? ((ad9389b_rd(sd, 0x98) & 0x70) >> 4) :
0395           ((ad9389b_rd(sd, 0x9e) & 0x0e) >> 1));
0396     if (ad9389b_rd(sd, 0xaf) & 0x02) {
0397         /* HDMI only */
0398         u8 manual_cts = ad9389b_rd(sd, 0x0a) & 0x80;
0399         u32 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
0400             ad9389b_rd(sd, 0x02) << 8 |
0401             ad9389b_rd(sd, 0x03);
0402         u8 vic_detect = ad9389b_rd(sd, 0x3e) >> 2;
0403         u8 vic_sent = ad9389b_rd(sd, 0x3d) & 0x3f;
0404         u32 CTS;
0405 
0406         if (manual_cts)
0407             CTS = (ad9389b_rd(sd, 0x07) & 0xf) << 16 |
0408                   ad9389b_rd(sd, 0x08) << 8 |
0409                   ad9389b_rd(sd, 0x09);
0410         else
0411             CTS = (ad9389b_rd(sd, 0x04) & 0xf) << 16 |
0412                   ad9389b_rd(sd, 0x05) << 8 |
0413                   ad9389b_rd(sd, 0x06);
0414         N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
0415             ad9389b_rd(sd, 0x02) << 8 |
0416             ad9389b_rd(sd, 0x03);
0417 
0418         v4l2_info(sd, "ad9389b: CTS %s mode: N %d, CTS %d\n",
0419               manual_cts ? "manual" : "automatic", N, CTS);
0420 
0421         v4l2_info(sd, "ad9389b: VIC: detected %d, sent %d\n",
0422               vic_detect, vic_sent);
0423     }
0424     if (state->dv_timings.type == V4L2_DV_BT_656_1120)
0425         v4l2_print_dv_timings(sd->name, "timings: ",
0426                 &state->dv_timings, false);
0427     else
0428         v4l2_info(sd, "no timings set\n");
0429     return 0;
0430 }
0431 
0432 /* Power up/down ad9389b */
0433 static int ad9389b_s_power(struct v4l2_subdev *sd, int on)
0434 {
0435     struct ad9389b_state *state = get_ad9389b_state(sd);
0436     struct ad9389b_platform_data *pdata = &state->pdata;
0437     const int retries = 20;
0438     int i;
0439 
0440     v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
0441 
0442     state->power_on = on;
0443 
0444     if (!on) {
0445         /* Power down */
0446         ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
0447         return true;
0448     }
0449 
0450     /* Power up */
0451     /* The ad9389b does not always come up immediately.
0452        Retry multiple times. */
0453     for (i = 0; i < retries; i++) {
0454         ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x0);
0455         if ((ad9389b_rd(sd, 0x41) & 0x40) == 0)
0456             break;
0457         ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
0458         msleep(10);
0459     }
0460     if (i == retries) {
0461         v4l2_dbg(1, debug, sd, "failed to powerup the ad9389b\n");
0462         ad9389b_s_power(sd, 0);
0463         return false;
0464     }
0465     if (i > 1)
0466         v4l2_dbg(1, debug, sd,
0467              "needed %d retries to powerup the ad9389b\n", i);
0468 
0469     /* Select chip: AD9389B */
0470     ad9389b_wr_and_or(sd, 0xba, 0xef, 0x10);
0471 
0472     /* Reserved registers that must be set according to REF_01 p. 11*/
0473     ad9389b_wr_and_or(sd, 0x98, 0xf0, 0x07);
0474     ad9389b_wr(sd, 0x9c, 0x38);
0475     ad9389b_wr_and_or(sd, 0x9d, 0xfc, 0x01);
0476 
0477     /* Differential output drive strength */
0478     if (pdata->diff_data_drive_strength > 0)
0479         ad9389b_wr(sd, 0xa2, pdata->diff_data_drive_strength);
0480     else
0481         ad9389b_wr(sd, 0xa2, 0x87);
0482 
0483     if (pdata->diff_clk_drive_strength > 0)
0484         ad9389b_wr(sd, 0xa3, pdata->diff_clk_drive_strength);
0485     else
0486         ad9389b_wr(sd, 0xa3, 0x87);
0487 
0488     ad9389b_wr(sd, 0x0a, 0x01);
0489     ad9389b_wr(sd, 0xbb, 0xff);
0490 
0491     /* Set number of attempts to read the EDID */
0492     ad9389b_wr(sd, 0xc9, 0xf);
0493     return true;
0494 }
0495 
0496 /* Enable interrupts */
0497 static void ad9389b_set_isr(struct v4l2_subdev *sd, bool enable)
0498 {
0499     u8 irqs = MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT;
0500     u8 irqs_rd;
0501     int retries = 100;
0502 
0503     /* The datasheet says that the EDID ready interrupt should be
0504        disabled if there is no hotplug. */
0505     if (!enable)
0506         irqs = 0;
0507     else if (ad9389b_have_hotplug(sd))
0508         irqs |= MASK_AD9389B_EDID_RDY_INT;
0509 
0510     /*
0511      * This i2c write can fail (approx. 1 in 1000 writes). But it
0512      * is essential that this register is correct, so retry it
0513      * multiple times.
0514      *
0515      * Note that the i2c write does not report an error, but the readback
0516      * clearly shows the wrong value.
0517      */
0518     do {
0519         ad9389b_wr(sd, 0x94, irqs);
0520         irqs_rd = ad9389b_rd(sd, 0x94);
0521     } while (retries-- && irqs_rd != irqs);
0522 
0523     if (irqs_rd != irqs)
0524         v4l2_err(sd, "Could not set interrupts: hw failure?\n");
0525 }
0526 
0527 /* Interrupt handler */
0528 static int ad9389b_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
0529 {
0530     u8 irq_status;
0531 
0532     /* disable interrupts to prevent a race condition */
0533     ad9389b_set_isr(sd, false);
0534     irq_status = ad9389b_rd(sd, 0x96);
0535     /* clear detected interrupts */
0536     ad9389b_wr(sd, 0x96, irq_status);
0537     /* enable interrupts */
0538     ad9389b_set_isr(sd, true);
0539 
0540     v4l2_dbg(1, debug, sd, "%s: irq_status 0x%x\n", __func__, irq_status);
0541 
0542     if (irq_status & (MASK_AD9389B_HPD_INT))
0543         ad9389b_check_monitor_present_status(sd);
0544     if (irq_status & MASK_AD9389B_EDID_RDY_INT)
0545         ad9389b_check_edid_status(sd);
0546 
0547     *handled = true;
0548     return 0;
0549 }
0550 
0551 static const struct v4l2_subdev_core_ops ad9389b_core_ops = {
0552     .log_status = ad9389b_log_status,
0553 #ifdef CONFIG_VIDEO_ADV_DEBUG
0554     .g_register = ad9389b_g_register,
0555     .s_register = ad9389b_s_register,
0556 #endif
0557     .s_power = ad9389b_s_power,
0558     .interrupt_service_routine = ad9389b_isr,
0559 };
0560 
0561 /* ------------------------------ VIDEO OPS ------------------------------ */
0562 
0563 /* Enable/disable ad9389b output */
0564 static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
0565 {
0566     v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
0567 
0568     ad9389b_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
0569     if (enable) {
0570         ad9389b_check_monitor_present_status(sd);
0571     } else {
0572         ad9389b_s_power(sd, 0);
0573     }
0574     return 0;
0575 }
0576 
0577 static const struct v4l2_dv_timings_cap ad9389b_timings_cap = {
0578     .type = V4L2_DV_BT_656_1120,
0579     /* keep this initialization for compatibility with GCC < 4.4.6 */
0580     .reserved = { 0 },
0581     V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
0582         V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
0583             V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
0584         V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
0585         V4L2_DV_BT_CAP_CUSTOM)
0586 };
0587 
0588 static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
0589                 struct v4l2_dv_timings *timings)
0590 {
0591     struct ad9389b_state *state = get_ad9389b_state(sd);
0592 
0593     v4l2_dbg(1, debug, sd, "%s:\n", __func__);
0594 
0595     /* quick sanity check */
0596     if (!v4l2_valid_dv_timings(timings, &ad9389b_timings_cap, NULL, NULL))
0597         return -EINVAL;
0598 
0599     /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
0600        if the format is one of the CEA or DMT timings. */
0601     v4l2_find_dv_timings_cap(timings, &ad9389b_timings_cap, 0, NULL, NULL);
0602 
0603     timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
0604 
0605     /* save timings */
0606     state->dv_timings = *timings;
0607 
0608     /* update quantization range based on new dv_timings */
0609     ad9389b_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
0610 
0611     /* update PLL gear based on new dv_timings */
0612     if (state->pdata.tmds_pll_gear == AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC)
0613         ad9389b_set_manual_pll_gear(sd, (u32)timings->bt.pixelclock);
0614 
0615     /* update AVI infoframe */
0616     ad9389b_set_IT_content_AVI_InfoFrame(sd);
0617 
0618     return 0;
0619 }
0620 
0621 static int ad9389b_g_dv_timings(struct v4l2_subdev *sd,
0622                 struct v4l2_dv_timings *timings)
0623 {
0624     struct ad9389b_state *state = get_ad9389b_state(sd);
0625 
0626     v4l2_dbg(1, debug, sd, "%s:\n", __func__);
0627 
0628     if (!timings)
0629         return -EINVAL;
0630 
0631     *timings = state->dv_timings;
0632 
0633     return 0;
0634 }
0635 
0636 static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd,
0637                    struct v4l2_enum_dv_timings *timings)
0638 {
0639     if (timings->pad != 0)
0640         return -EINVAL;
0641 
0642     return v4l2_enum_dv_timings_cap(timings, &ad9389b_timings_cap,
0643             NULL, NULL);
0644 }
0645 
0646 static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd,
0647                   struct v4l2_dv_timings_cap *cap)
0648 {
0649     if (cap->pad != 0)
0650         return -EINVAL;
0651 
0652     *cap = ad9389b_timings_cap;
0653     return 0;
0654 }
0655 
0656 static const struct v4l2_subdev_video_ops ad9389b_video_ops = {
0657     .s_stream = ad9389b_s_stream,
0658     .s_dv_timings = ad9389b_s_dv_timings,
0659     .g_dv_timings = ad9389b_g_dv_timings,
0660 };
0661 
0662 /* ------------------------------ PAD OPS ------------------------------ */
0663 
0664 static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
0665 {
0666     struct ad9389b_state *state = get_ad9389b_state(sd);
0667 
0668     if (edid->pad != 0)
0669         return -EINVAL;
0670     if (edid->blocks == 0 || edid->blocks > 256)
0671         return -EINVAL;
0672     if (!state->edid.segments) {
0673         v4l2_dbg(1, debug, sd, "EDID segment 0 not found\n");
0674         return -ENODATA;
0675     }
0676     if (edid->start_block >= state->edid.segments * 2)
0677         return -E2BIG;
0678     if (edid->blocks + edid->start_block >= state->edid.segments * 2)
0679         edid->blocks = state->edid.segments * 2 - edid->start_block;
0680     memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
0681            128 * edid->blocks);
0682     return 0;
0683 }
0684 
0685 static const struct v4l2_subdev_pad_ops ad9389b_pad_ops = {
0686     .get_edid = ad9389b_get_edid,
0687     .enum_dv_timings = ad9389b_enum_dv_timings,
0688     .dv_timings_cap = ad9389b_dv_timings_cap,
0689 };
0690 
0691 /* ------------------------------ AUDIO OPS ------------------------------ */
0692 
0693 static int ad9389b_s_audio_stream(struct v4l2_subdev *sd, int enable)
0694 {
0695     v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
0696 
0697     if (enable)
0698         ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x80);
0699     else
0700         ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x40);
0701 
0702     return 0;
0703 }
0704 
0705 static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
0706 {
0707     u32 N;
0708 
0709     switch (freq) {
0710     case 32000:  N = 4096;  break;
0711     case 44100:  N = 6272;  break;
0712     case 48000:  N = 6144;  break;
0713     case 88200:  N = 12544; break;
0714     case 96000:  N = 12288; break;
0715     case 176400: N = 25088; break;
0716     case 192000: N = 24576; break;
0717     default:
0718          return -EINVAL;
0719     }
0720 
0721     /* Set N (used with CTS to regenerate the audio clock) */
0722     ad9389b_wr(sd, 0x01, (N >> 16) & 0xf);
0723     ad9389b_wr(sd, 0x02, (N >> 8) & 0xff);
0724     ad9389b_wr(sd, 0x03, N & 0xff);
0725 
0726     return 0;
0727 }
0728 
0729 static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
0730 {
0731     u32 i2s_sf;
0732 
0733     switch (freq) {
0734     case 32000:  i2s_sf = 0x30; break;
0735     case 44100:  i2s_sf = 0x00; break;
0736     case 48000:  i2s_sf = 0x20; break;
0737     case 88200:  i2s_sf = 0x80; break;
0738     case 96000:  i2s_sf = 0xa0; break;
0739     case 176400: i2s_sf = 0xc0; break;
0740     case 192000: i2s_sf = 0xe0; break;
0741     default:
0742          return -EINVAL;
0743     }
0744 
0745     /* Set sampling frequency for I2S audio to 48 kHz */
0746     ad9389b_wr_and_or(sd, 0x15, 0xf, i2s_sf);
0747 
0748     return 0;
0749 }
0750 
0751 static int ad9389b_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
0752 {
0753     /* TODO based on input/output/config */
0754     /* TODO See datasheet "Programmers guide" p. 39-40 */
0755 
0756     /* Only 2 channels in use for application */
0757     ad9389b_wr_and_or(sd, 0x50, 0x1f, 0x20);
0758     /* Speaker mapping */
0759     ad9389b_wr(sd, 0x51, 0x00);
0760 
0761     /* TODO Where should this be placed? */
0762     /* 16 bit audio word length */
0763     ad9389b_wr_and_or(sd, 0x14, 0xf0, 0x02);
0764 
0765     return 0;
0766 }
0767 
0768 static const struct v4l2_subdev_audio_ops ad9389b_audio_ops = {
0769     .s_stream = ad9389b_s_audio_stream,
0770     .s_clock_freq = ad9389b_s_clock_freq,
0771     .s_i2s_clock_freq = ad9389b_s_i2s_clock_freq,
0772     .s_routing = ad9389b_s_routing,
0773 };
0774 
0775 /* --------------------- SUBDEV OPS --------------------------------------- */
0776 
0777 static const struct v4l2_subdev_ops ad9389b_ops = {
0778     .core  = &ad9389b_core_ops,
0779     .video = &ad9389b_video_ops,
0780     .audio = &ad9389b_audio_ops,
0781     .pad = &ad9389b_pad_ops,
0782 };
0783 
0784 /* ----------------------------------------------------------------------- */
0785 static void ad9389b_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd,
0786                   int segment, u8 *buf)
0787 {
0788     int i, j;
0789 
0790     if (debug < lvl)
0791         return;
0792 
0793     v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
0794     for (i = 0; i < 256; i += 16) {
0795         u8 b[128];
0796         u8 *bp = b;
0797 
0798         if (i == 128)
0799             v4l2_dbg(lvl, debug, sd, "\n");
0800         for (j = i; j < i + 16; j++) {
0801             sprintf(bp, "0x%02x, ", buf[j]);
0802             bp += 6;
0803         }
0804         bp[0] = '\0';
0805         v4l2_dbg(lvl, debug, sd, "%s\n", b);
0806     }
0807 }
0808 
0809 static void ad9389b_edid_handler(struct work_struct *work)
0810 {
0811     struct delayed_work *dwork = to_delayed_work(work);
0812     struct ad9389b_state *state =
0813         container_of(dwork, struct ad9389b_state, edid_handler);
0814     struct v4l2_subdev *sd = &state->sd;
0815     struct ad9389b_edid_detect ed;
0816 
0817     v4l2_dbg(1, debug, sd, "%s:\n", __func__);
0818 
0819     if (ad9389b_check_edid_status(sd)) {
0820         /* Return if we received the EDID. */
0821         return;
0822     }
0823 
0824     if (ad9389b_have_hotplug(sd)) {
0825         /* We must retry reading the EDID several times, it is possible
0826          * that initially the EDID couldn't be read due to i2c errors
0827          * (DVI connectors are particularly prone to this problem). */
0828         if (state->edid.read_retries) {
0829             state->edid.read_retries--;
0830             v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__);
0831             ad9389b_s_power(sd, false);
0832             ad9389b_s_power(sd, true);
0833             schedule_delayed_work(&state->edid_handler, EDID_DELAY);
0834             return;
0835         }
0836     }
0837 
0838     /* We failed to read the EDID, so send an event for this. */
0839     ed.present = false;
0840     ed.segment = ad9389b_rd(sd, 0xc4);
0841     v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
0842     v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
0843 }
0844 
0845 static void ad9389b_audio_setup(struct v4l2_subdev *sd)
0846 {
0847     v4l2_dbg(1, debug, sd, "%s\n", __func__);
0848 
0849     ad9389b_s_i2s_clock_freq(sd, 48000);
0850     ad9389b_s_clock_freq(sd, 48000);
0851     ad9389b_s_routing(sd, 0, 0, 0);
0852 }
0853 
0854 /* Initial setup of AD9389b */
0855 
0856 /* Configure hdmi transmitter. */
0857 static void ad9389b_setup(struct v4l2_subdev *sd)
0858 {
0859     struct ad9389b_state *state = get_ad9389b_state(sd);
0860 
0861     v4l2_dbg(1, debug, sd, "%s\n", __func__);
0862 
0863     /* Input format: RGB 4:4:4 */
0864     ad9389b_wr_and_or(sd, 0x15, 0xf1, 0x0);
0865     /* Output format: RGB 4:4:4 */
0866     ad9389b_wr_and_or(sd, 0x16, 0x3f, 0x0);
0867     /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion,
0868        Aspect ratio: 16:9 */
0869     ad9389b_wr_and_or(sd, 0x17, 0xf9, 0x06);
0870     /* Output format: RGB 4:4:4, Active Format Information is valid. */
0871     ad9389b_wr_and_or(sd, 0x45, 0xc7, 0x08);
0872     /* Underscanned */
0873     ad9389b_wr_and_or(sd, 0x46, 0x3f, 0x80);
0874     /* Setup video format */
0875     ad9389b_wr(sd, 0x3c, 0x0);
0876     /* Active format aspect ratio: same as picure. */
0877     ad9389b_wr(sd, 0x47, 0x80);
0878     /* No encryption */
0879     ad9389b_wr_and_or(sd, 0xaf, 0xef, 0x0);
0880     /* Positive clk edge capture for input video clock */
0881     ad9389b_wr_and_or(sd, 0xba, 0x1f, 0x60);
0882 
0883     ad9389b_audio_setup(sd);
0884 
0885     v4l2_ctrl_handler_setup(&state->hdl);
0886 
0887     ad9389b_set_IT_content_AVI_InfoFrame(sd);
0888 }
0889 
0890 static void ad9389b_notify_monitor_detect(struct v4l2_subdev *sd)
0891 {
0892     struct ad9389b_monitor_detect mdt;
0893     struct ad9389b_state *state = get_ad9389b_state(sd);
0894 
0895     mdt.present = state->have_monitor;
0896     v4l2_subdev_notify(sd, AD9389B_MONITOR_DETECT, (void *)&mdt);
0897 }
0898 
0899 static void ad9389b_update_monitor_present_status(struct v4l2_subdev *sd)
0900 {
0901     struct ad9389b_state *state = get_ad9389b_state(sd);
0902     /* read hotplug and rx-sense state */
0903     u8 status = ad9389b_rd(sd, 0x42);
0904 
0905     v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
0906          __func__,
0907          status,
0908          status & MASK_AD9389B_HPD_DETECT ? ", hotplug" : "",
0909          status & MASK_AD9389B_MSEN_DETECT ? ", rx-sense" : "");
0910 
0911     if (status & MASK_AD9389B_HPD_DETECT) {
0912         v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
0913         state->have_monitor = true;
0914         if (!ad9389b_s_power(sd, true)) {
0915             v4l2_dbg(1, debug, sd,
0916                  "%s: monitor detected, powerup failed\n", __func__);
0917             return;
0918         }
0919         ad9389b_setup(sd);
0920         ad9389b_notify_monitor_detect(sd);
0921         state->edid.read_retries = EDID_MAX_RETRIES;
0922         schedule_delayed_work(&state->edid_handler, EDID_DELAY);
0923     } else if (!(status & MASK_AD9389B_HPD_DETECT)) {
0924         v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
0925         state->have_monitor = false;
0926         ad9389b_notify_monitor_detect(sd);
0927         ad9389b_s_power(sd, false);
0928         memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
0929     }
0930 
0931     /* update read only ctrls */
0932     v4l2_ctrl_s_ctrl(state->hotplug_ctrl, ad9389b_have_hotplug(sd) ? 0x1 : 0x0);
0933     v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, ad9389b_have_rx_sense(sd) ? 0x1 : 0x0);
0934     v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
0935 
0936     /* update with setting from ctrls */
0937     ad9389b_s_ctrl(state->rgb_quantization_range_ctrl);
0938     ad9389b_s_ctrl(state->hdmi_mode_ctrl);
0939 }
0940 
0941 static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd)
0942 {
0943     struct ad9389b_state *state = get_ad9389b_state(sd);
0944     int retry = 0;
0945 
0946     ad9389b_update_monitor_present_status(sd);
0947 
0948     /*
0949      * Rapid toggling of the hotplug may leave the chip powered off,
0950      * even if we think it is on. In that case reset and power up again.
0951      */
0952     while (state->power_on && (ad9389b_rd(sd, 0x41) & 0x40)) {
0953         if (++retry > 5) {
0954             v4l2_err(sd, "retried %d times, give up\n", retry);
0955             return;
0956         }
0957         v4l2_dbg(1, debug, sd, "%s: reset and re-check status (%d)\n", __func__, retry);
0958         ad9389b_notify_monitor_detect(sd);
0959         cancel_delayed_work_sync(&state->edid_handler);
0960         memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
0961         ad9389b_s_power(sd, false);
0962         ad9389b_update_monitor_present_status(sd);
0963     }
0964 }
0965 
0966 static bool edid_block_verify_crc(u8 *edid_block)
0967 {
0968     u8 sum = 0;
0969     int i;
0970 
0971     for (i = 0; i < 128; i++)
0972         sum += edid_block[i];
0973     return sum == 0;
0974 }
0975 
0976 static bool edid_verify_crc(struct v4l2_subdev *sd, u32 segment)
0977 {
0978     struct ad9389b_state *state = get_ad9389b_state(sd);
0979     u32 blocks = state->edid.blocks;
0980     u8 *data = state->edid.data;
0981 
0982     if (edid_block_verify_crc(&data[segment * 256])) {
0983         if ((segment + 1) * 2 <= blocks)
0984             return edid_block_verify_crc(&data[segment * 256 + 128]);
0985         return true;
0986     }
0987     return false;
0988 }
0989 
0990 static bool edid_verify_header(struct v4l2_subdev *sd, u32 segment)
0991 {
0992     static const u8 hdmi_header[] = {
0993         0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
0994     };
0995     struct ad9389b_state *state = get_ad9389b_state(sd);
0996     u8 *data = state->edid.data;
0997     int i;
0998 
0999     if (segment)
1000         return true;
1001 
1002     for (i = 0; i < ARRAY_SIZE(hdmi_header); i++)
1003         if (data[i] != hdmi_header[i])
1004             return false;
1005 
1006     return true;
1007 }
1008 
1009 static bool ad9389b_check_edid_status(struct v4l2_subdev *sd)
1010 {
1011     struct ad9389b_state *state = get_ad9389b_state(sd);
1012     struct ad9389b_edid_detect ed;
1013     int segment;
1014     u8 edidRdy = ad9389b_rd(sd, 0xc5);
1015 
1016     v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
1017          __func__, EDID_MAX_RETRIES - state->edid.read_retries);
1018 
1019     if (!(edidRdy & MASK_AD9389B_EDID_RDY))
1020         return false;
1021 
1022     segment = ad9389b_rd(sd, 0xc4);
1023     if (segment >= EDID_MAX_SEGM) {
1024         v4l2_err(sd, "edid segment number too big\n");
1025         return false;
1026     }
1027     v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1028     ad9389b_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1029     ad9389b_dbg_dump_edid(2, debug, sd, segment,
1030                   &state->edid.data[segment * 256]);
1031     if (segment == 0) {
1032         state->edid.blocks = state->edid.data[0x7e] + 1;
1033         v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
1034              __func__, state->edid.blocks);
1035     }
1036     if (!edid_verify_crc(sd, segment) ||
1037         !edid_verify_header(sd, segment)) {
1038         /* edid crc error, force reread of edid segment */
1039         v4l2_err(sd, "%s: edid crc or header error\n", __func__);
1040         ad9389b_s_power(sd, false);
1041         ad9389b_s_power(sd, true);
1042         return false;
1043     }
1044     /* one more segment read ok */
1045     state->edid.segments = segment + 1;
1046     if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1047         /* Request next EDID segment */
1048         v4l2_dbg(1, debug, sd, "%s: request segment %d\n",
1049              __func__, state->edid.segments);
1050         ad9389b_wr(sd, 0xc9, 0xf);
1051         ad9389b_wr(sd, 0xc4, state->edid.segments);
1052         state->edid.read_retries = EDID_MAX_RETRIES;
1053         schedule_delayed_work(&state->edid_handler, EDID_DELAY);
1054         return false;
1055     }
1056 
1057     /* report when we have all segments but report only for segment 0 */
1058     ed.present = true;
1059     ed.segment = 0;
1060     v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
1061     state->edid_detect_counter++;
1062     v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1063     return ed.present;
1064 }
1065 
1066 /* ----------------------------------------------------------------------- */
1067 
1068 static void ad9389b_init_setup(struct v4l2_subdev *sd)
1069 {
1070     struct ad9389b_state *state = get_ad9389b_state(sd);
1071     struct ad9389b_state_edid *edid = &state->edid;
1072 
1073     v4l2_dbg(1, debug, sd, "%s\n", __func__);
1074 
1075     /* clear all interrupts */
1076     ad9389b_wr(sd, 0x96, 0xff);
1077 
1078     memset(edid, 0, sizeof(struct ad9389b_state_edid));
1079     state->have_monitor = false;
1080     ad9389b_set_isr(sd, false);
1081 }
1082 
1083 static int ad9389b_probe(struct i2c_client *client, const struct i2c_device_id *id)
1084 {
1085     const struct v4l2_dv_timings dv1080p60 = V4L2_DV_BT_CEA_1920X1080P60;
1086     struct ad9389b_state *state;
1087     struct ad9389b_platform_data *pdata = client->dev.platform_data;
1088     struct v4l2_ctrl_handler *hdl;
1089     struct v4l2_subdev *sd;
1090     int err = -EIO;
1091 
1092     /* Check if the adapter supports the needed features */
1093     if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1094         return -EIO;
1095 
1096     v4l_dbg(1, debug, client, "detecting ad9389b client on address 0x%x\n",
1097         client->addr << 1);
1098 
1099     state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1100     if (!state)
1101         return -ENOMEM;
1102 
1103     /* Platform data */
1104     if (pdata == NULL) {
1105         v4l_err(client, "No platform data!\n");
1106         return -ENODEV;
1107     }
1108     memcpy(&state->pdata, pdata, sizeof(state->pdata));
1109 
1110     sd = &state->sd;
1111     v4l2_i2c_subdev_init(sd, client, &ad9389b_ops);
1112     sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1113 
1114     hdl = &state->hdl;
1115     v4l2_ctrl_handler_init(hdl, 5);
1116 
1117     state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1118             V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1119             0, V4L2_DV_TX_MODE_DVI_D);
1120     state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1121             V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
1122     state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1123             V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
1124     state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1125             V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
1126     state->rgb_quantization_range_ctrl =
1127         v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1128             V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1129             0, V4L2_DV_RGB_RANGE_AUTO);
1130     sd->ctrl_handler = hdl;
1131     if (hdl->error) {
1132         err = hdl->error;
1133 
1134         goto err_hdl;
1135     }
1136     state->pad.flags = MEDIA_PAD_FL_SINK;
1137     sd->entity.function = MEDIA_ENT_F_DV_ENCODER;
1138     err = media_entity_pads_init(&sd->entity, 1, &state->pad);
1139     if (err)
1140         goto err_hdl;
1141 
1142     state->chip_revision = ad9389b_rd(sd, 0x0);
1143     if (state->chip_revision != 2) {
1144         v4l2_err(sd, "chip_revision %d != 2\n", state->chip_revision);
1145         err = -EIO;
1146         goto err_entity;
1147     }
1148     v4l2_dbg(1, debug, sd, "reg 0x41 0x%x, chip version (reg 0x00) 0x%x\n",
1149          ad9389b_rd(sd, 0x41), state->chip_revision);
1150 
1151     state->edid_i2c_client = i2c_new_dummy_device(client->adapter, (0x7e >> 1));
1152     if (IS_ERR(state->edid_i2c_client)) {
1153         v4l2_err(sd, "failed to register edid i2c client\n");
1154         err = PTR_ERR(state->edid_i2c_client);
1155         goto err_entity;
1156     }
1157 
1158     INIT_DELAYED_WORK(&state->edid_handler, ad9389b_edid_handler);
1159     state->dv_timings = dv1080p60;
1160 
1161     ad9389b_init_setup(sd);
1162     ad9389b_set_isr(sd, true);
1163 
1164     v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1165           client->addr << 1, client->adapter->name);
1166     return 0;
1167 
1168 err_entity:
1169     media_entity_cleanup(&sd->entity);
1170 err_hdl:
1171     v4l2_ctrl_handler_free(&state->hdl);
1172     return err;
1173 }
1174 
1175 /* ----------------------------------------------------------------------- */
1176 
1177 static int ad9389b_remove(struct i2c_client *client)
1178 {
1179     struct v4l2_subdev *sd = i2c_get_clientdata(client);
1180     struct ad9389b_state *state = get_ad9389b_state(sd);
1181 
1182     state->chip_revision = -1;
1183 
1184     v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1185          client->addr << 1, client->adapter->name);
1186 
1187     ad9389b_s_stream(sd, false);
1188     ad9389b_s_audio_stream(sd, false);
1189     ad9389b_init_setup(sd);
1190     cancel_delayed_work_sync(&state->edid_handler);
1191     i2c_unregister_device(state->edid_i2c_client);
1192     v4l2_device_unregister_subdev(sd);
1193     media_entity_cleanup(&sd->entity);
1194     v4l2_ctrl_handler_free(sd->ctrl_handler);
1195     return 0;
1196 }
1197 
1198 /* ----------------------------------------------------------------------- */
1199 
1200 static const struct i2c_device_id ad9389b_id[] = {
1201     { "ad9389b", 0 },
1202     { "ad9889b", 0 },
1203     { }
1204 };
1205 MODULE_DEVICE_TABLE(i2c, ad9389b_id);
1206 
1207 static struct i2c_driver ad9389b_driver = {
1208     .driver = {
1209         .name = "ad9389b",
1210     },
1211     .probe = ad9389b_probe,
1212     .remove = ad9389b_remove,
1213     .id_table = ad9389b_id,
1214 };
1215 
1216 module_i2c_driver(ad9389b_driver);
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