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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for Zarlink DVB-T ZL10353 demodulator
0004  *
0005  * Copyright (C) 2006, 2007 Christopher Pascoe <c.pascoe@itee.uq.edu.au>
0006  */
0007 
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/init.h>
0011 #include <linux/delay.h>
0012 #include <linux/string.h>
0013 #include <linux/slab.h>
0014 #include <asm/div64.h>
0015 
0016 #include <media/dvb_frontend.h>
0017 #include "zl10353_priv.h"
0018 #include "zl10353.h"
0019 
0020 struct zl10353_state {
0021     struct i2c_adapter *i2c;
0022     struct dvb_frontend frontend;
0023 
0024     struct zl10353_config config;
0025 
0026     u32 bandwidth;
0027     u32 ucblocks;
0028     u32 frequency;
0029 };
0030 
0031 static int debug;
0032 #define dprintk(args...) \
0033     do { \
0034         if (debug) printk(KERN_DEBUG "zl10353: " args); \
0035     } while (0)
0036 
0037 static int debug_regs;
0038 
0039 static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
0040 {
0041     struct zl10353_state *state = fe->demodulator_priv;
0042     u8 buf[2] = { reg, val };
0043     struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
0044                    .buf = buf, .len = 2 };
0045     int err = i2c_transfer(state->i2c, &msg, 1);
0046     if (err != 1) {
0047         printk("zl10353: write to reg %x failed (err = %d)!\n", reg, err);
0048         return err;
0049     }
0050     return 0;
0051 }
0052 
0053 static int zl10353_write(struct dvb_frontend *fe, const u8 ibuf[], int ilen)
0054 {
0055     int err, i;
0056     for (i = 0; i < ilen - 1; i++)
0057         if ((err = zl10353_single_write(fe, ibuf[0] + i, ibuf[i + 1])))
0058             return err;
0059 
0060     return 0;
0061 }
0062 
0063 static int zl10353_read_register(struct zl10353_state *state, u8 reg)
0064 {
0065     int ret;
0066     u8 b0[1] = { reg };
0067     u8 b1[1] = { 0 };
0068     struct i2c_msg msg[2] = { { .addr = state->config.demod_address,
0069                     .flags = 0,
0070                     .buf = b0, .len = 1 },
0071                   { .addr = state->config.demod_address,
0072                     .flags = I2C_M_RD,
0073                     .buf = b1, .len = 1 } };
0074 
0075     ret = i2c_transfer(state->i2c, msg, 2);
0076 
0077     if (ret != 2) {
0078         printk("%s: readreg error (reg=%d, ret==%i)\n",
0079                __func__, reg, ret);
0080         return ret;
0081     }
0082 
0083     return b1[0];
0084 }
0085 
0086 static void zl10353_dump_regs(struct dvb_frontend *fe)
0087 {
0088     struct zl10353_state *state = fe->demodulator_priv;
0089     int ret;
0090     u8 reg;
0091 
0092     /* Dump all registers. */
0093     for (reg = 0; ; reg++) {
0094         if (reg % 16 == 0) {
0095             if (reg)
0096                 printk(KERN_CONT "\n");
0097             printk(KERN_DEBUG "%02x:", reg);
0098         }
0099         ret = zl10353_read_register(state, reg);
0100         if (ret >= 0)
0101             printk(KERN_CONT " %02x", (u8)ret);
0102         else
0103             printk(KERN_CONT " --");
0104         if (reg == 0xff)
0105             break;
0106     }
0107     printk(KERN_CONT "\n");
0108 }
0109 
0110 static void zl10353_calc_nominal_rate(struct dvb_frontend *fe,
0111                       u32 bandwidth,
0112                       u16 *nominal_rate)
0113 {
0114     struct zl10353_state *state = fe->demodulator_priv;
0115     u32 adc_clock = 450560; /* 45.056 MHz */
0116     u64 value;
0117     u8 bw = bandwidth / 1000000;
0118 
0119     if (state->config.adc_clock)
0120         adc_clock = state->config.adc_clock;
0121 
0122     value = (u64)10 * (1 << 23) / 7 * 125;
0123     value = (bw * value) + adc_clock / 2;
0124     *nominal_rate = div_u64(value, adc_clock);
0125 
0126     dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
0127         __func__, bw, adc_clock, *nominal_rate);
0128 }
0129 
0130 static void zl10353_calc_input_freq(struct dvb_frontend *fe,
0131                     u16 *input_freq)
0132 {
0133     struct zl10353_state *state = fe->demodulator_priv;
0134     u32 adc_clock = 450560; /* 45.056  MHz */
0135     int if2 = 361667;   /* 36.1667 MHz */
0136     int ife;
0137     u64 value;
0138 
0139     if (state->config.adc_clock)
0140         adc_clock = state->config.adc_clock;
0141     if (state->config.if2)
0142         if2 = state->config.if2;
0143 
0144     if (adc_clock >= if2 * 2)
0145         ife = if2;
0146     else {
0147         ife = adc_clock - (if2 % adc_clock);
0148         if (ife > adc_clock / 2)
0149             ife = adc_clock - ife;
0150     }
0151     value = div_u64((u64)65536 * ife + adc_clock / 2, adc_clock);
0152     *input_freq = -value;
0153 
0154     dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
0155         __func__, if2, ife, adc_clock, -(int)value, *input_freq);
0156 }
0157 
0158 static int zl10353_sleep(struct dvb_frontend *fe)
0159 {
0160     static u8 zl10353_softdown[] = { 0x50, 0x0C, 0x44 };
0161 
0162     zl10353_write(fe, zl10353_softdown, sizeof(zl10353_softdown));
0163     return 0;
0164 }
0165 
0166 static int zl10353_set_parameters(struct dvb_frontend *fe)
0167 {
0168     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0169     struct zl10353_state *state = fe->demodulator_priv;
0170     u16 nominal_rate, input_freq;
0171     u8 pllbuf[6] = { 0x67 }, acq_ctl = 0;
0172     u16 tps = 0;
0173 
0174     state->frequency = c->frequency;
0175 
0176     zl10353_single_write(fe, RESET, 0x80);
0177     udelay(200);
0178     zl10353_single_write(fe, 0xEA, 0x01);
0179     udelay(200);
0180     zl10353_single_write(fe, 0xEA, 0x00);
0181 
0182     zl10353_single_write(fe, AGC_TARGET, 0x28);
0183 
0184     if (c->transmission_mode != TRANSMISSION_MODE_AUTO)
0185         acq_ctl |= (1 << 0);
0186     if (c->guard_interval != GUARD_INTERVAL_AUTO)
0187         acq_ctl |= (1 << 1);
0188     zl10353_single_write(fe, ACQ_CTL, acq_ctl);
0189 
0190     switch (c->bandwidth_hz) {
0191     case 6000000:
0192         /* These are extrapolated from the 7 and 8MHz values */
0193         zl10353_single_write(fe, MCLK_RATIO, 0x97);
0194         zl10353_single_write(fe, 0x64, 0x34);
0195         zl10353_single_write(fe, 0xcc, 0xdd);
0196         break;
0197     case 7000000:
0198         zl10353_single_write(fe, MCLK_RATIO, 0x86);
0199         zl10353_single_write(fe, 0x64, 0x35);
0200         zl10353_single_write(fe, 0xcc, 0x73);
0201         break;
0202     default:
0203         c->bandwidth_hz = 8000000;
0204         fallthrough;
0205     case 8000000:
0206         zl10353_single_write(fe, MCLK_RATIO, 0x75);
0207         zl10353_single_write(fe, 0x64, 0x36);
0208         zl10353_single_write(fe, 0xcc, 0x73);
0209     }
0210 
0211     zl10353_calc_nominal_rate(fe, c->bandwidth_hz, &nominal_rate);
0212     zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate));
0213     zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate));
0214     state->bandwidth = c->bandwidth_hz;
0215 
0216     zl10353_calc_input_freq(fe, &input_freq);
0217     zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq));
0218     zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq));
0219 
0220     /* Hint at TPS settings */
0221     switch (c->code_rate_HP) {
0222     case FEC_2_3:
0223         tps |= (1 << 7);
0224         break;
0225     case FEC_3_4:
0226         tps |= (2 << 7);
0227         break;
0228     case FEC_5_6:
0229         tps |= (3 << 7);
0230         break;
0231     case FEC_7_8:
0232         tps |= (4 << 7);
0233         break;
0234     case FEC_1_2:
0235     case FEC_AUTO:
0236         break;
0237     default:
0238         return -EINVAL;
0239     }
0240 
0241     switch (c->code_rate_LP) {
0242     case FEC_2_3:
0243         tps |= (1 << 4);
0244         break;
0245     case FEC_3_4:
0246         tps |= (2 << 4);
0247         break;
0248     case FEC_5_6:
0249         tps |= (3 << 4);
0250         break;
0251     case FEC_7_8:
0252         tps |= (4 << 4);
0253         break;
0254     case FEC_1_2:
0255     case FEC_AUTO:
0256         break;
0257     case FEC_NONE:
0258         if (c->hierarchy == HIERARCHY_AUTO ||
0259             c->hierarchy == HIERARCHY_NONE)
0260             break;
0261         fallthrough;
0262     default:
0263         return -EINVAL;
0264     }
0265 
0266     switch (c->modulation) {
0267     case QPSK:
0268         break;
0269     case QAM_AUTO:
0270     case QAM_16:
0271         tps |= (1 << 13);
0272         break;
0273     case QAM_64:
0274         tps |= (2 << 13);
0275         break;
0276     default:
0277         return -EINVAL;
0278     }
0279 
0280     switch (c->transmission_mode) {
0281     case TRANSMISSION_MODE_2K:
0282     case TRANSMISSION_MODE_AUTO:
0283         break;
0284     case TRANSMISSION_MODE_8K:
0285         tps |= (1 << 0);
0286         break;
0287     default:
0288         return -EINVAL;
0289     }
0290 
0291     switch (c->guard_interval) {
0292     case GUARD_INTERVAL_1_32:
0293     case GUARD_INTERVAL_AUTO:
0294         break;
0295     case GUARD_INTERVAL_1_16:
0296         tps |= (1 << 2);
0297         break;
0298     case GUARD_INTERVAL_1_8:
0299         tps |= (2 << 2);
0300         break;
0301     case GUARD_INTERVAL_1_4:
0302         tps |= (3 << 2);
0303         break;
0304     default:
0305         return -EINVAL;
0306     }
0307 
0308     switch (c->hierarchy) {
0309     case HIERARCHY_AUTO:
0310     case HIERARCHY_NONE:
0311         break;
0312     case HIERARCHY_1:
0313         tps |= (1 << 10);
0314         break;
0315     case HIERARCHY_2:
0316         tps |= (2 << 10);
0317         break;
0318     case HIERARCHY_4:
0319         tps |= (3 << 10);
0320         break;
0321     default:
0322         return -EINVAL;
0323     }
0324 
0325     zl10353_single_write(fe, TPS_GIVEN_1, msb(tps));
0326     zl10353_single_write(fe, TPS_GIVEN_0, lsb(tps));
0327 
0328     if (fe->ops.i2c_gate_ctrl)
0329         fe->ops.i2c_gate_ctrl(fe, 0);
0330 
0331     /*
0332      * If there is no tuner attached to the secondary I2C bus, we call
0333      * set_params to program a potential tuner attached somewhere else.
0334      * Otherwise, we update the PLL registers via calc_regs.
0335      */
0336     if (state->config.no_tuner) {
0337         if (fe->ops.tuner_ops.set_params) {
0338             fe->ops.tuner_ops.set_params(fe);
0339             if (fe->ops.i2c_gate_ctrl)
0340                 fe->ops.i2c_gate_ctrl(fe, 0);
0341         }
0342     } else if (fe->ops.tuner_ops.calc_regs) {
0343         fe->ops.tuner_ops.calc_regs(fe, pllbuf + 1, 5);
0344         pllbuf[1] <<= 1;
0345         zl10353_write(fe, pllbuf, sizeof(pllbuf));
0346     }
0347 
0348     zl10353_single_write(fe, 0x5F, 0x13);
0349 
0350     /* If no attached tuner or invalid PLL registers, just start the FSM. */
0351     if (state->config.no_tuner || fe->ops.tuner_ops.calc_regs == NULL)
0352         zl10353_single_write(fe, FSM_GO, 0x01);
0353     else
0354         zl10353_single_write(fe, TUNER_GO, 0x01);
0355 
0356     return 0;
0357 }
0358 
0359 static int zl10353_get_parameters(struct dvb_frontend *fe,
0360                   struct dtv_frontend_properties *c)
0361 {
0362     struct zl10353_state *state = fe->demodulator_priv;
0363     int s6, s9;
0364     u16 tps;
0365     static const u8 tps_fec_to_api[8] = {
0366         FEC_1_2,
0367         FEC_2_3,
0368         FEC_3_4,
0369         FEC_5_6,
0370         FEC_7_8,
0371         FEC_AUTO,
0372         FEC_AUTO,
0373         FEC_AUTO
0374     };
0375 
0376     s6 = zl10353_read_register(state, STATUS_6);
0377     s9 = zl10353_read_register(state, STATUS_9);
0378     if (s6 < 0 || s9 < 0)
0379         return -EREMOTEIO;
0380     if ((s6 & (1 << 5)) == 0 || (s9 & (1 << 4)) == 0)
0381         return -EINVAL; /* no FE or TPS lock */
0382 
0383     tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 |
0384           zl10353_read_register(state, TPS_RECEIVED_0);
0385 
0386     c->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
0387     c->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
0388 
0389     switch ((tps >> 13) & 3) {
0390     case 0:
0391         c->modulation = QPSK;
0392         break;
0393     case 1:
0394         c->modulation = QAM_16;
0395         break;
0396     case 2:
0397         c->modulation = QAM_64;
0398         break;
0399     default:
0400         c->modulation = QAM_AUTO;
0401         break;
0402     }
0403 
0404     c->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K :
0405                            TRANSMISSION_MODE_2K;
0406 
0407     switch ((tps >> 2) & 3) {
0408     case 0:
0409         c->guard_interval = GUARD_INTERVAL_1_32;
0410         break;
0411     case 1:
0412         c->guard_interval = GUARD_INTERVAL_1_16;
0413         break;
0414     case 2:
0415         c->guard_interval = GUARD_INTERVAL_1_8;
0416         break;
0417     case 3:
0418         c->guard_interval = GUARD_INTERVAL_1_4;
0419         break;
0420     default:
0421         c->guard_interval = GUARD_INTERVAL_AUTO;
0422         break;
0423     }
0424 
0425     switch ((tps >> 10) & 7) {
0426     case 0:
0427         c->hierarchy = HIERARCHY_NONE;
0428         break;
0429     case 1:
0430         c->hierarchy = HIERARCHY_1;
0431         break;
0432     case 2:
0433         c->hierarchy = HIERARCHY_2;
0434         break;
0435     case 3:
0436         c->hierarchy = HIERARCHY_4;
0437         break;
0438     default:
0439         c->hierarchy = HIERARCHY_AUTO;
0440         break;
0441     }
0442 
0443     c->frequency = state->frequency;
0444     c->bandwidth_hz = state->bandwidth;
0445     c->inversion = INVERSION_AUTO;
0446 
0447     return 0;
0448 }
0449 
0450 static int zl10353_read_status(struct dvb_frontend *fe, enum fe_status *status)
0451 {
0452     struct zl10353_state *state = fe->demodulator_priv;
0453     int s6, s7, s8;
0454 
0455     if ((s6 = zl10353_read_register(state, STATUS_6)) < 0)
0456         return -EREMOTEIO;
0457     if ((s7 = zl10353_read_register(state, STATUS_7)) < 0)
0458         return -EREMOTEIO;
0459     if ((s8 = zl10353_read_register(state, STATUS_8)) < 0)
0460         return -EREMOTEIO;
0461 
0462     *status = 0;
0463     if (s6 & (1 << 2))
0464         *status |= FE_HAS_CARRIER;
0465     if (s6 & (1 << 1))
0466         *status |= FE_HAS_VITERBI;
0467     if (s6 & (1 << 5))
0468         *status |= FE_HAS_LOCK;
0469     if (s7 & (1 << 4))
0470         *status |= FE_HAS_SYNC;
0471     if (s8 & (1 << 6))
0472         *status |= FE_HAS_SIGNAL;
0473 
0474     if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
0475         (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
0476         *status &= ~FE_HAS_LOCK;
0477 
0478     return 0;
0479 }
0480 
0481 static int zl10353_read_ber(struct dvb_frontend *fe, u32 *ber)
0482 {
0483     struct zl10353_state *state = fe->demodulator_priv;
0484 
0485     *ber = zl10353_read_register(state, RS_ERR_CNT_2) << 16 |
0486            zl10353_read_register(state, RS_ERR_CNT_1) << 8 |
0487            zl10353_read_register(state, RS_ERR_CNT_0);
0488 
0489     return 0;
0490 }
0491 
0492 static int zl10353_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
0493 {
0494     struct zl10353_state *state = fe->demodulator_priv;
0495 
0496     u16 signal = zl10353_read_register(state, AGC_GAIN_1) << 10 |
0497              zl10353_read_register(state, AGC_GAIN_0) << 2 | 3;
0498 
0499     *strength = ~signal;
0500 
0501     return 0;
0502 }
0503 
0504 static int zl10353_read_snr(struct dvb_frontend *fe, u16 *snr)
0505 {
0506     struct zl10353_state *state = fe->demodulator_priv;
0507     u8 _snr;
0508 
0509     if (debug_regs)
0510         zl10353_dump_regs(fe);
0511 
0512     _snr = zl10353_read_register(state, SNR);
0513     *snr = 10 * _snr / 8;
0514 
0515     return 0;
0516 }
0517 
0518 static int zl10353_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
0519 {
0520     struct zl10353_state *state = fe->demodulator_priv;
0521     u32 ubl = 0;
0522 
0523     ubl = zl10353_read_register(state, RS_UBC_1) << 8 |
0524           zl10353_read_register(state, RS_UBC_0);
0525 
0526     state->ucblocks += ubl;
0527     *ucblocks = state->ucblocks;
0528 
0529     return 0;
0530 }
0531 
0532 static int zl10353_get_tune_settings(struct dvb_frontend *fe,
0533                      struct dvb_frontend_tune_settings
0534                      *fe_tune_settings)
0535 {
0536     fe_tune_settings->min_delay_ms = 1000;
0537     fe_tune_settings->step_size = 0;
0538     fe_tune_settings->max_drift = 0;
0539 
0540     return 0;
0541 }
0542 
0543 static int zl10353_init(struct dvb_frontend *fe)
0544 {
0545     struct zl10353_state *state = fe->demodulator_priv;
0546     u8 zl10353_reset_attach[6] = { 0x50, 0x03, 0x64, 0x46, 0x15, 0x0F };
0547 
0548     if (debug_regs)
0549         zl10353_dump_regs(fe);
0550     if (state->config.parallel_ts)
0551         zl10353_reset_attach[2] &= ~0x20;
0552     if (state->config.clock_ctl_1)
0553         zl10353_reset_attach[3] = state->config.clock_ctl_1;
0554     if (state->config.pll_0)
0555         zl10353_reset_attach[4] = state->config.pll_0;
0556 
0557     /* Do a "hard" reset if not already done */
0558     if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] ||
0559         zl10353_read_register(state, 0x51) != zl10353_reset_attach[2]) {
0560         zl10353_write(fe, zl10353_reset_attach,
0561                    sizeof(zl10353_reset_attach));
0562         if (debug_regs)
0563             zl10353_dump_regs(fe);
0564     }
0565 
0566     return 0;
0567 }
0568 
0569 static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
0570 {
0571     struct zl10353_state *state = fe->demodulator_priv;
0572     u8 val = 0x0a;
0573 
0574     if (state->config.disable_i2c_gate_ctrl) {
0575         /* No tuner attached to the internal I2C bus */
0576         /* If set enable I2C bridge, the main I2C bus stopped hardly */
0577         return 0;
0578     }
0579 
0580     if (enable)
0581         val |= 0x10;
0582 
0583     return zl10353_single_write(fe, 0x62, val);
0584 }
0585 
0586 static void zl10353_release(struct dvb_frontend *fe)
0587 {
0588     struct zl10353_state *state = fe->demodulator_priv;
0589     kfree(state);
0590 }
0591 
0592 static const struct dvb_frontend_ops zl10353_ops;
0593 
0594 struct dvb_frontend *zl10353_attach(const struct zl10353_config *config,
0595                     struct i2c_adapter *i2c)
0596 {
0597     struct zl10353_state *state = NULL;
0598     int id;
0599 
0600     /* allocate memory for the internal state */
0601     state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL);
0602     if (state == NULL)
0603         goto error;
0604 
0605     /* setup the state */
0606     state->i2c = i2c;
0607     memcpy(&state->config, config, sizeof(struct zl10353_config));
0608 
0609     /* check if the demod is there */
0610     id = zl10353_read_register(state, CHIP_ID);
0611     if ((id != ID_ZL10353) && (id != ID_CE6230) && (id != ID_CE6231))
0612         goto error;
0613 
0614     /* create dvb_frontend */
0615     memcpy(&state->frontend.ops, &zl10353_ops, sizeof(struct dvb_frontend_ops));
0616     state->frontend.demodulator_priv = state;
0617 
0618     return &state->frontend;
0619 error:
0620     kfree(state);
0621     return NULL;
0622 }
0623 
0624 static const struct dvb_frontend_ops zl10353_ops = {
0625     .delsys = { SYS_DVBT },
0626     .info = {
0627         .name           = "Zarlink ZL10353 DVB-T",
0628         .frequency_min_hz   = 174 * MHz,
0629         .frequency_max_hz   = 862 * MHz,
0630         .frequency_stepsize_hz  = 166667,
0631         .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
0632             FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
0633             FE_CAN_FEC_AUTO |
0634             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
0635             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
0636             FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
0637             FE_CAN_MUTE_TS
0638     },
0639 
0640     .release = zl10353_release,
0641 
0642     .init = zl10353_init,
0643     .sleep = zl10353_sleep,
0644     .i2c_gate_ctrl = zl10353_i2c_gate_ctrl,
0645     .write = zl10353_write,
0646 
0647     .set_frontend = zl10353_set_parameters,
0648     .get_frontend = zl10353_get_parameters,
0649     .get_tune_settings = zl10353_get_tune_settings,
0650 
0651     .read_status = zl10353_read_status,
0652     .read_ber = zl10353_read_ber,
0653     .read_signal_strength = zl10353_read_signal_strength,
0654     .read_snr = zl10353_read_snr,
0655     .read_ucblocks = zl10353_read_ucblocks,
0656 };
0657 
0658 module_param(debug, int, 0644);
0659 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
0660 
0661 module_param(debug_regs, int, 0644);
0662 MODULE_PARM_DESC(debug_regs, "Turn on/off frontend register dumps (default:off).");
0663 
0664 MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver");
0665 MODULE_AUTHOR("Chris Pascoe");
0666 MODULE_LICENSE("GPL");
0667 
0668 EXPORT_SYMBOL(zl10353_attach);
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