Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002   /*
0003      Driver for Philips tda1004xh OFDM Demodulator
0004 
0005      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
0006 
0007 
0008    */
0009 /*
0010  * This driver needs external firmware. Please use the commands
0011  * "<kerneldir>/scripts/get_dvb_firmware tda10045",
0012  * "<kerneldir>/scripts/get_dvb_firmware tda10046" to
0013  * download/extract them, and then copy them to /usr/lib/hotplug/firmware
0014  * or /lib/firmware (depending on configuration of firmware hotplug).
0015  */
0016 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
0017 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
0018 
0019 #include <linux/init.h>
0020 #include <linux/module.h>
0021 #include <linux/device.h>
0022 #include <linux/jiffies.h>
0023 #include <linux/string.h>
0024 #include <linux/slab.h>
0025 
0026 #include <media/dvb_frontend.h>
0027 #include "tda1004x.h"
0028 
0029 static int debug;
0030 #define dprintk(args...) \
0031     do { \
0032         if (debug) printk(KERN_DEBUG "tda1004x: " args); \
0033     } while (0)
0034 
0035 #define TDA1004X_CHIPID      0x00
0036 #define TDA1004X_AUTO        0x01
0037 #define TDA1004X_IN_CONF1    0x02
0038 #define TDA1004X_IN_CONF2    0x03
0039 #define TDA1004X_OUT_CONF1   0x04
0040 #define TDA1004X_OUT_CONF2   0x05
0041 #define TDA1004X_STATUS_CD   0x06
0042 #define TDA1004X_CONFC4      0x07
0043 #define TDA1004X_DSSPARE2    0x0C
0044 #define TDA10045H_CODE_IN    0x0D
0045 #define TDA10045H_FWPAGE     0x0E
0046 #define TDA1004X_SCAN_CPT    0x10
0047 #define TDA1004X_DSP_CMD     0x11
0048 #define TDA1004X_DSP_ARG     0x12
0049 #define TDA1004X_DSP_DATA1   0x13
0050 #define TDA1004X_DSP_DATA2   0x14
0051 #define TDA1004X_CONFADC1    0x15
0052 #define TDA1004X_CONFC1      0x16
0053 #define TDA10045H_S_AGC      0x1a
0054 #define TDA10046H_AGC_TUN_LEVEL  0x1a
0055 #define TDA1004X_SNR         0x1c
0056 #define TDA1004X_CONF_TS1    0x1e
0057 #define TDA1004X_CONF_TS2    0x1f
0058 #define TDA1004X_CBER_RESET  0x20
0059 #define TDA1004X_CBER_MSB    0x21
0060 #define TDA1004X_CBER_LSB    0x22
0061 #define TDA1004X_CVBER_LUT   0x23
0062 #define TDA1004X_VBER_MSB    0x24
0063 #define TDA1004X_VBER_MID    0x25
0064 #define TDA1004X_VBER_LSB    0x26
0065 #define TDA1004X_UNCOR       0x27
0066 
0067 #define TDA10045H_CONFPLL_P  0x2D
0068 #define TDA10045H_CONFPLL_M_MSB  0x2E
0069 #define TDA10045H_CONFPLL_M_LSB  0x2F
0070 #define TDA10045H_CONFPLL_N  0x30
0071 
0072 #define TDA10046H_CONFPLL1   0x2D
0073 #define TDA10046H_CONFPLL2   0x2F
0074 #define TDA10046H_CONFPLL3   0x30
0075 #define TDA10046H_TIME_WREF1     0x31
0076 #define TDA10046H_TIME_WREF2     0x32
0077 #define TDA10046H_TIME_WREF3     0x33
0078 #define TDA10046H_TIME_WREF4     0x34
0079 #define TDA10046H_TIME_WREF5     0x35
0080 
0081 #define TDA10045H_UNSURW_MSB     0x31
0082 #define TDA10045H_UNSURW_LSB     0x32
0083 #define TDA10045H_WREF_MSB   0x33
0084 #define TDA10045H_WREF_MID   0x34
0085 #define TDA10045H_WREF_LSB   0x35
0086 #define TDA10045H_MUXOUT     0x36
0087 #define TDA1004X_CONFADC2    0x37
0088 
0089 #define TDA10045H_IOFFSET    0x38
0090 
0091 #define TDA10046H_CONF_TRISTATE1 0x3B
0092 #define TDA10046H_CONF_TRISTATE2 0x3C
0093 #define TDA10046H_CONF_POLARITY  0x3D
0094 #define TDA10046H_FREQ_OFFSET    0x3E
0095 #define TDA10046H_GPIO_OUT_SEL   0x41
0096 #define TDA10046H_GPIO_SELECT    0x42
0097 #define TDA10046H_AGC_CONF   0x43
0098 #define TDA10046H_AGC_THR    0x44
0099 #define TDA10046H_AGC_RENORM     0x45
0100 #define TDA10046H_AGC_GAINS  0x46
0101 #define TDA10046H_AGC_TUN_MIN    0x47
0102 #define TDA10046H_AGC_TUN_MAX    0x48
0103 #define TDA10046H_AGC_IF_MIN     0x49
0104 #define TDA10046H_AGC_IF_MAX     0x4A
0105 
0106 #define TDA10046H_FREQ_PHY2_MSB  0x4D
0107 #define TDA10046H_FREQ_PHY2_LSB  0x4E
0108 
0109 #define TDA10046H_CVBER_CTRL     0x4F
0110 #define TDA10046H_AGC_IF_LEVEL   0x52
0111 #define TDA10046H_CODE_CPT   0x57
0112 #define TDA10046H_CODE_IN    0x58
0113 
0114 
0115 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
0116 {
0117     int ret;
0118     u8 buf[] = { reg, data };
0119     struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
0120 
0121     dprintk("%s: reg=0x%x, data=0x%x\n", __func__, reg, data);
0122 
0123     msg.addr = state->config->demod_address;
0124     ret = i2c_transfer(state->i2c, &msg, 1);
0125 
0126     if (ret != 1)
0127         dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
0128             __func__, reg, data, ret);
0129 
0130     dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
0131         reg, data, ret);
0132     return (ret != 1) ? -1 : 0;
0133 }
0134 
0135 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
0136 {
0137     int ret;
0138     u8 b0[] = { reg };
0139     u8 b1[] = { 0 };
0140     struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
0141                 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
0142 
0143     dprintk("%s: reg=0x%x\n", __func__, reg);
0144 
0145     msg[0].addr = state->config->demod_address;
0146     msg[1].addr = state->config->demod_address;
0147     ret = i2c_transfer(state->i2c, msg, 2);
0148 
0149     if (ret != 2) {
0150         dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg,
0151             ret);
0152         return -EINVAL;
0153     }
0154 
0155     dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
0156         reg, b1[0], ret);
0157     return b1[0];
0158 }
0159 
0160 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
0161 {
0162     int val;
0163     dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __func__, reg,
0164         mask, data);
0165 
0166     // read a byte and check
0167     val = tda1004x_read_byte(state, reg);
0168     if (val < 0)
0169         return val;
0170 
0171     // mask if off
0172     val = val & ~mask;
0173     val |= data & 0xff;
0174 
0175     // write it out again
0176     return tda1004x_write_byteI(state, reg, val);
0177 }
0178 
0179 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
0180 {
0181     int i;
0182     int result;
0183 
0184     dprintk("%s: reg=0x%x, len=0x%x\n", __func__, reg, len);
0185 
0186     result = 0;
0187     for (i = 0; i < len; i++) {
0188         result = tda1004x_write_byteI(state, reg + i, buf[i]);
0189         if (result != 0)
0190             break;
0191     }
0192 
0193     return result;
0194 }
0195 
0196 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
0197 {
0198     int result;
0199     dprintk("%s\n", __func__);
0200 
0201     result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
0202     msleep(20);
0203     return result;
0204 }
0205 
0206 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
0207 {
0208     dprintk("%s\n", __func__);
0209 
0210     return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
0211 }
0212 
0213 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
0214                    u32 bandwidth)
0215 {
0216     static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
0217     static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
0218     static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
0219 
0220     switch (bandwidth) {
0221     case 6000000:
0222         tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
0223         break;
0224 
0225     case 7000000:
0226         tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
0227         break;
0228 
0229     case 8000000:
0230         tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
0231         break;
0232 
0233     default:
0234         return -EINVAL;
0235     }
0236 
0237     tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
0238 
0239     return 0;
0240 }
0241 
0242 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
0243                    u32 bandwidth)
0244 {
0245     static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
0246     static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
0247     static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
0248 
0249     static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
0250     static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
0251     static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
0252     int tda10046_clk53m;
0253 
0254     if ((state->config->if_freq == TDA10046_FREQ_045) ||
0255         (state->config->if_freq == TDA10046_FREQ_052))
0256         tda10046_clk53m = 0;
0257     else
0258         tda10046_clk53m = 1;
0259     switch (bandwidth) {
0260     case 6000000:
0261         if (tda10046_clk53m)
0262             tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
0263                           sizeof(bandwidth_6mhz_53M));
0264         else
0265             tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
0266                           sizeof(bandwidth_6mhz_48M));
0267         if (state->config->if_freq == TDA10046_FREQ_045) {
0268             tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
0269             tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
0270         }
0271         break;
0272 
0273     case 7000000:
0274         if (tda10046_clk53m)
0275             tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
0276                           sizeof(bandwidth_7mhz_53M));
0277         else
0278             tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
0279                           sizeof(bandwidth_7mhz_48M));
0280         if (state->config->if_freq == TDA10046_FREQ_045) {
0281             tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
0282             tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
0283         }
0284         break;
0285 
0286     case 8000000:
0287         if (tda10046_clk53m)
0288             tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
0289                           sizeof(bandwidth_8mhz_53M));
0290         else
0291             tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
0292                           sizeof(bandwidth_8mhz_48M));
0293         if (state->config->if_freq == TDA10046_FREQ_045) {
0294             tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
0295             tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
0296         }
0297         break;
0298 
0299     default:
0300         return -EINVAL;
0301     }
0302 
0303     return 0;
0304 }
0305 
0306 static int tda1004x_do_upload(struct tda1004x_state *state,
0307                   const unsigned char *mem, unsigned int len,
0308                   u8 dspCodeCounterReg, u8 dspCodeInReg)
0309 {
0310     u8 buf[65];
0311     struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
0312     int tx_size;
0313     int pos = 0;
0314 
0315     /* clear code counter */
0316     tda1004x_write_byteI(state, dspCodeCounterReg, 0);
0317     fw_msg.addr = state->config->demod_address;
0318 
0319     i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT);
0320     buf[0] = dspCodeInReg;
0321     while (pos != len) {
0322         // work out how much to send this time
0323         tx_size = len - pos;
0324         if (tx_size > 0x10)
0325             tx_size = 0x10;
0326 
0327         // send the chunk
0328         memcpy(buf + 1, mem + pos, tx_size);
0329         fw_msg.len = tx_size + 1;
0330         if (__i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
0331             printk(KERN_ERR "tda1004x: Error during firmware upload\n");
0332             i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
0333             return -EIO;
0334         }
0335         pos += tx_size;
0336 
0337         dprintk("%s: fw_pos=0x%x\n", __func__, pos);
0338     }
0339     i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
0340 
0341     /* give the DSP a chance to settle 03/10/05 Hac */
0342     msleep(100);
0343 
0344     return 0;
0345 }
0346 
0347 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
0348 {
0349     u8 data1, data2;
0350     unsigned long timeout;
0351 
0352     if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
0353         timeout = jiffies + 2 * HZ;
0354         while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
0355             if (time_after(jiffies, timeout)) {
0356                 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
0357                 break;
0358             }
0359             msleep(1);
0360         }
0361     } else
0362         msleep(100);
0363 
0364     // check upload was OK
0365     tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
0366     tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
0367 
0368     data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
0369     data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
0370     if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
0371         printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
0372         return -EIO;
0373     }
0374     printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
0375     return 0;
0376 }
0377 
0378 static int tda10045_fwupload(struct dvb_frontend* fe)
0379 {
0380     struct tda1004x_state* state = fe->demodulator_priv;
0381     int ret;
0382     const struct firmware *fw;
0383 
0384     /* don't re-upload unless necessary */
0385     if (tda1004x_check_upload_ok(state) == 0)
0386         return 0;
0387 
0388     /* request the firmware, this will block until someone uploads it */
0389     printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
0390     ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
0391     if (ret) {
0392         printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
0393         return ret;
0394     }
0395 
0396     /* reset chip */
0397     tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
0398     tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
0399     tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
0400     msleep(10);
0401 
0402     /* set parameters */
0403     tda10045h_set_bandwidth(state, 8000000);
0404 
0405     ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
0406     release_firmware(fw);
0407     if (ret)
0408         return ret;
0409     printk(KERN_INFO "tda1004x: firmware upload complete\n");
0410 
0411     /* wait for DSP to initialise */
0412     /* DSPREADY doesn't seem to work on the TDA10045H */
0413     msleep(100);
0414 
0415     return tda1004x_check_upload_ok(state);
0416 }
0417 
0418 static void tda10046_init_plls(struct dvb_frontend* fe)
0419 {
0420     struct tda1004x_state* state = fe->demodulator_priv;
0421     int tda10046_clk53m;
0422 
0423     if ((state->config->if_freq == TDA10046_FREQ_045) ||
0424         (state->config->if_freq == TDA10046_FREQ_052))
0425         tda10046_clk53m = 0;
0426     else
0427         tda10046_clk53m = 1;
0428 
0429     tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
0430     if(tda10046_clk53m) {
0431         printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
0432         tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
0433     } else {
0434         printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
0435         tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
0436     }
0437     if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
0438         dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __func__);
0439         tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
0440     } else {
0441         dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __func__);
0442         tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
0443     }
0444     if(tda10046_clk53m)
0445         tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
0446     else
0447         tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
0448     /* Note clock frequency is handled implicitly */
0449     switch (state->config->if_freq) {
0450     case TDA10046_FREQ_045:
0451         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
0452         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
0453         break;
0454     case TDA10046_FREQ_052:
0455         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
0456         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
0457         break;
0458     case TDA10046_FREQ_3617:
0459         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
0460         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
0461         break;
0462     case TDA10046_FREQ_3613:
0463         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
0464         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
0465         break;
0466     }
0467     tda10046h_set_bandwidth(state, 8000000); /* default bandwidth 8 MHz */
0468     /* let the PLLs settle */
0469     msleep(120);
0470 }
0471 
0472 static int tda10046_fwupload(struct dvb_frontend* fe)
0473 {
0474     struct tda1004x_state* state = fe->demodulator_priv;
0475     int ret, confc4;
0476     const struct firmware *fw;
0477 
0478     /* reset + wake up chip */
0479     if (state->config->xtal_freq == TDA10046_XTAL_4M) {
0480         confc4 = 0;
0481     } else {
0482         dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __func__);
0483         confc4 = 0x80;
0484     }
0485     tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
0486 
0487     tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
0488     /* set GPIO 1 and 3 */
0489     if (state->config->gpio_config != TDA10046_GPTRI) {
0490         tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33);
0491         tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f);
0492     }
0493     /* let the clocks recover from sleep */
0494     msleep(10);
0495 
0496     /* The PLLs need to be reprogrammed after sleep */
0497     tda10046_init_plls(fe);
0498     tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0);
0499 
0500     /* don't re-upload unless necessary */
0501     if (tda1004x_check_upload_ok(state) == 0)
0502         return 0;
0503 
0504     /*
0505        For i2c normal work, we need to slow down the bus speed.
0506        However, the slow down breaks the eeprom firmware load.
0507        So, use normal speed for eeprom booting and then restore the
0508        i2c speed after that. Tested with MSI TV @nyware A/D board,
0509        that comes with firmware version 29 inside their eeprom.
0510 
0511        It should also be noticed that no other I2C transfer should
0512        be in course while booting from eeprom, otherwise, tda10046
0513        goes into an instable state. So, proper locking are needed
0514        at the i2c bus master.
0515      */
0516     printk(KERN_INFO "tda1004x: trying to boot from eeprom\n");
0517     tda1004x_write_byteI(state, TDA1004X_CONFC4, 4);
0518     msleep(300);
0519     tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
0520 
0521     /* Checks if eeprom firmware went without troubles */
0522     if (tda1004x_check_upload_ok(state) == 0)
0523         return 0;
0524 
0525     /* eeprom firmware didn't work. Load one manually. */
0526 
0527     if (state->config->request_firmware != NULL) {
0528         /* request the firmware, this will block until someone uploads it */
0529         printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
0530         ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
0531         if (ret) {
0532             /* remain compatible to old bug: try to load with tda10045 image name */
0533             ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
0534             if (ret) {
0535                 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
0536                 return ret;
0537             } else {
0538                 printk(KERN_INFO "tda1004x: please rename the firmware file to %s\n",
0539                           TDA10046_DEFAULT_FIRMWARE);
0540             }
0541         }
0542     } else {
0543         printk(KERN_ERR "tda1004x: no request function defined, can't upload from file\n");
0544         return -EIO;
0545     }
0546     tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
0547     ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
0548     release_firmware(fw);
0549     return tda1004x_check_upload_ok(state);
0550 }
0551 
0552 static int tda1004x_encode_fec(int fec)
0553 {
0554     // convert known FEC values
0555     switch (fec) {
0556     case FEC_1_2:
0557         return 0;
0558     case FEC_2_3:
0559         return 1;
0560     case FEC_3_4:
0561         return 2;
0562     case FEC_5_6:
0563         return 3;
0564     case FEC_7_8:
0565         return 4;
0566     }
0567 
0568     // unsupported
0569     return -EINVAL;
0570 }
0571 
0572 static int tda1004x_decode_fec(int tdafec)
0573 {
0574     // convert known FEC values
0575     switch (tdafec) {
0576     case 0:
0577         return FEC_1_2;
0578     case 1:
0579         return FEC_2_3;
0580     case 2:
0581         return FEC_3_4;
0582     case 3:
0583         return FEC_5_6;
0584     case 4:
0585         return FEC_7_8;
0586     }
0587 
0588     // unsupported
0589     return -1;
0590 }
0591 
0592 static int tda1004x_write(struct dvb_frontend* fe, const u8 buf[], int len)
0593 {
0594     struct tda1004x_state* state = fe->demodulator_priv;
0595 
0596     if (len != 2)
0597         return -EINVAL;
0598 
0599     return tda1004x_write_byteI(state, buf[0], buf[1]);
0600 }
0601 
0602 static int tda10045_init(struct dvb_frontend* fe)
0603 {
0604     struct tda1004x_state* state = fe->demodulator_priv;
0605 
0606     dprintk("%s\n", __func__);
0607 
0608     if (tda10045_fwupload(fe)) {
0609         printk("tda1004x: firmware upload failed\n");
0610         return -EIO;
0611     }
0612 
0613     tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
0614 
0615     // tda setup
0616     tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
0617     tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
0618     tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
0619     tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
0620     tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
0621     tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
0622     tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
0623     tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
0624     tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
0625     tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
0626     tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
0627 
0628     tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
0629 
0630     return 0;
0631 }
0632 
0633 static int tda10046_init(struct dvb_frontend* fe)
0634 {
0635     struct tda1004x_state* state = fe->demodulator_priv;
0636     dprintk("%s\n", __func__);
0637 
0638     if (tda10046_fwupload(fe)) {
0639         printk("tda1004x: firmware upload failed\n");
0640         return -EIO;
0641     }
0642 
0643     // tda setup
0644     tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
0645     tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87);    // 100 ppm crystal, select HP stream
0646     tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88);      // enable pulse killer
0647 
0648     switch (state->config->agc_config) {
0649     case TDA10046_AGC_DEFAULT:
0650         tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
0651         tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
0652         break;
0653     case TDA10046_AGC_IFO_AUTO_NEG:
0654         tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
0655         tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
0656         break;
0657     case TDA10046_AGC_IFO_AUTO_POS:
0658         tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
0659         tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00);  // set AGC polarities
0660         break;
0661     case TDA10046_AGC_TDA827X:
0662         tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02);   // AGC setup
0663         tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70);    // AGC Threshold
0664         tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
0665         tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
0666         break;
0667     }
0668     if (state->config->ts_mode == 0) {
0669         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40);
0670         tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
0671     } else {
0672         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80);
0673         tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10,
0674                             state->config->invert_oclk << 4);
0675     }
0676     tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
0677     tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on
0678     tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);    // }
0679     tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
0680     tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0);     // }
0681     tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff);  // }
0682     tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
0683     tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
0684     tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
0685     tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
0686     // tda1004x_write_mask(state, 0x50, 0x80, 0x80);         // handle out of guard echoes
0687 
0688     return 0;
0689 }
0690 
0691 static int tda1004x_set_fe(struct dvb_frontend *fe)
0692 {
0693     struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
0694     struct tda1004x_state* state = fe->demodulator_priv;
0695     int tmp;
0696     int inversion;
0697 
0698     dprintk("%s\n", __func__);
0699 
0700     if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
0701         // setup auto offset
0702         tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
0703         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
0704         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
0705 
0706         // disable agc_conf[2]
0707         tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
0708     }
0709 
0710     // set frequency
0711     if (fe->ops.tuner_ops.set_params) {
0712         fe->ops.tuner_ops.set_params(fe);
0713         if (fe->ops.i2c_gate_ctrl)
0714             fe->ops.i2c_gate_ctrl(fe, 0);
0715     }
0716 
0717     // Hardcoded to use auto as much as possible on the TDA10045 as it
0718     // is very unreliable if AUTO mode is _not_ used.
0719     if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
0720         fe_params->code_rate_HP = FEC_AUTO;
0721         fe_params->guard_interval = GUARD_INTERVAL_AUTO;
0722         fe_params->transmission_mode = TRANSMISSION_MODE_AUTO;
0723     }
0724 
0725     // Set standard params.. or put them to auto
0726     if ((fe_params->code_rate_HP == FEC_AUTO) ||
0727         (fe_params->code_rate_LP == FEC_AUTO) ||
0728         (fe_params->modulation == QAM_AUTO) ||
0729         (fe_params->hierarchy == HIERARCHY_AUTO)) {
0730         tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1);    // enable auto
0731         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */
0732         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
0733         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
0734     } else {
0735         tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0);    // disable auto
0736 
0737         // set HP FEC
0738         tmp = tda1004x_encode_fec(fe_params->code_rate_HP);
0739         if (tmp < 0)
0740             return tmp;
0741         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
0742 
0743         // set LP FEC
0744         tmp = tda1004x_encode_fec(fe_params->code_rate_LP);
0745         if (tmp < 0)
0746             return tmp;
0747         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
0748 
0749         /* set modulation */
0750         switch (fe_params->modulation) {
0751         case QPSK:
0752             tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
0753             break;
0754 
0755         case QAM_16:
0756             tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
0757             break;
0758 
0759         case QAM_64:
0760             tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
0761             break;
0762 
0763         default:
0764             return -EINVAL;
0765         }
0766 
0767         // set hierarchy
0768         switch (fe_params->hierarchy) {
0769         case HIERARCHY_NONE:
0770             tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
0771             break;
0772 
0773         case HIERARCHY_1:
0774             tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
0775             break;
0776 
0777         case HIERARCHY_2:
0778             tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
0779             break;
0780 
0781         case HIERARCHY_4:
0782             tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
0783             break;
0784 
0785         default:
0786             return -EINVAL;
0787         }
0788     }
0789 
0790     // set bandwidth
0791     switch (state->demod_type) {
0792     case TDA1004X_DEMOD_TDA10045:
0793         tda10045h_set_bandwidth(state, fe_params->bandwidth_hz);
0794         break;
0795 
0796     case TDA1004X_DEMOD_TDA10046:
0797         tda10046h_set_bandwidth(state, fe_params->bandwidth_hz);
0798         break;
0799     }
0800 
0801     // set inversion
0802     inversion = fe_params->inversion;
0803     if (state->config->invert)
0804         inversion = inversion ? INVERSION_OFF : INVERSION_ON;
0805     switch (inversion) {
0806     case INVERSION_OFF:
0807         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
0808         break;
0809 
0810     case INVERSION_ON:
0811         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
0812         break;
0813 
0814     default:
0815         return -EINVAL;
0816     }
0817 
0818     // set guard interval
0819     switch (fe_params->guard_interval) {
0820     case GUARD_INTERVAL_1_32:
0821         tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
0822         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
0823         break;
0824 
0825     case GUARD_INTERVAL_1_16:
0826         tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
0827         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
0828         break;
0829 
0830     case GUARD_INTERVAL_1_8:
0831         tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
0832         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
0833         break;
0834 
0835     case GUARD_INTERVAL_1_4:
0836         tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
0837         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
0838         break;
0839 
0840     case GUARD_INTERVAL_AUTO:
0841         tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
0842         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
0843         break;
0844 
0845     default:
0846         return -EINVAL;
0847     }
0848 
0849     // set transmission mode
0850     switch (fe_params->transmission_mode) {
0851     case TRANSMISSION_MODE_2K:
0852         tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
0853         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
0854         break;
0855 
0856     case TRANSMISSION_MODE_8K:
0857         tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
0858         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
0859         break;
0860 
0861     case TRANSMISSION_MODE_AUTO:
0862         tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
0863         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
0864         break;
0865 
0866     default:
0867         return -EINVAL;
0868     }
0869 
0870     // start the lock
0871     switch (state->demod_type) {
0872     case TDA1004X_DEMOD_TDA10045:
0873         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
0874         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
0875         break;
0876 
0877     case TDA1004X_DEMOD_TDA10046:
0878         tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
0879         msleep(1);
0880         tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
0881         break;
0882     }
0883 
0884     msleep(10);
0885 
0886     return 0;
0887 }
0888 
0889 static int tda1004x_get_fe(struct dvb_frontend *fe,
0890                struct dtv_frontend_properties *fe_params)
0891 {
0892     struct tda1004x_state* state = fe->demodulator_priv;
0893     int status;
0894 
0895     dprintk("%s\n", __func__);
0896 
0897     status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
0898     if (status == -1)
0899         return -EIO;
0900 
0901     /* Only update the properties cache if device is locked */
0902     if (!(status & 8))
0903         return 0;
0904 
0905     // inversion status
0906     fe_params->inversion = INVERSION_OFF;
0907     if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
0908         fe_params->inversion = INVERSION_ON;
0909     if (state->config->invert)
0910         fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
0911 
0912     // bandwidth
0913     switch (state->demod_type) {
0914     case TDA1004X_DEMOD_TDA10045:
0915         switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
0916         case 0x14:
0917             fe_params->bandwidth_hz = 8000000;
0918             break;
0919         case 0xdb:
0920             fe_params->bandwidth_hz = 7000000;
0921             break;
0922         case 0x4f:
0923             fe_params->bandwidth_hz = 6000000;
0924             break;
0925         }
0926         break;
0927     case TDA1004X_DEMOD_TDA10046:
0928         switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
0929         case 0x5c:
0930         case 0x54:
0931             fe_params->bandwidth_hz = 8000000;
0932             break;
0933         case 0x6a:
0934         case 0x60:
0935             fe_params->bandwidth_hz = 7000000;
0936             break;
0937         case 0x7b:
0938         case 0x70:
0939             fe_params->bandwidth_hz = 6000000;
0940             break;
0941         }
0942         break;
0943     }
0944 
0945     // FEC
0946     fe_params->code_rate_HP =
0947         tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
0948     fe_params->code_rate_LP =
0949         tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
0950 
0951     /* modulation */
0952     switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
0953     case 0:
0954         fe_params->modulation = QPSK;
0955         break;
0956     case 1:
0957         fe_params->modulation = QAM_16;
0958         break;
0959     case 2:
0960         fe_params->modulation = QAM_64;
0961         break;
0962     }
0963 
0964     // transmission mode
0965     fe_params->transmission_mode = TRANSMISSION_MODE_2K;
0966     if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
0967         fe_params->transmission_mode = TRANSMISSION_MODE_8K;
0968 
0969     // guard interval
0970     switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
0971     case 0:
0972         fe_params->guard_interval = GUARD_INTERVAL_1_32;
0973         break;
0974     case 1:
0975         fe_params->guard_interval = GUARD_INTERVAL_1_16;
0976         break;
0977     case 2:
0978         fe_params->guard_interval = GUARD_INTERVAL_1_8;
0979         break;
0980     case 3:
0981         fe_params->guard_interval = GUARD_INTERVAL_1_4;
0982         break;
0983     }
0984 
0985     // hierarchy
0986     switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
0987     case 0:
0988         fe_params->hierarchy = HIERARCHY_NONE;
0989         break;
0990     case 1:
0991         fe_params->hierarchy = HIERARCHY_1;
0992         break;
0993     case 2:
0994         fe_params->hierarchy = HIERARCHY_2;
0995         break;
0996     case 3:
0997         fe_params->hierarchy = HIERARCHY_4;
0998         break;
0999     }
1000 
1001     return 0;
1002 }
1003 
1004 static int tda1004x_read_status(struct dvb_frontend *fe,
1005                 enum fe_status *fe_status)
1006 {
1007     struct tda1004x_state* state = fe->demodulator_priv;
1008     int status;
1009     int cber;
1010     int vber;
1011 
1012     dprintk("%s\n", __func__);
1013 
1014     // read status
1015     status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
1016     if (status == -1)
1017         return -EIO;
1018 
1019     // decode
1020     *fe_status = 0;
1021     if (status & 4)
1022         *fe_status |= FE_HAS_SIGNAL;
1023     if (status & 2)
1024         *fe_status |= FE_HAS_CARRIER;
1025     if (status & 8)
1026         *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1027 
1028     // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1029     // is getting anything valid
1030     if (!(*fe_status & FE_HAS_VITERBI)) {
1031         // read the CBER
1032         cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1033         if (cber == -1)
1034             return -EIO;
1035         status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1036         if (status == -1)
1037             return -EIO;
1038         cber |= (status << 8);
1039         // The address 0x20 should be read to cope with a TDA10046 bug
1040         tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1041 
1042         if (cber != 65535)
1043             *fe_status |= FE_HAS_VITERBI;
1044     }
1045 
1046     // if we DO have some valid VITERBI output, but don't already have SYNC
1047     // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1048     if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1049         // read the VBER
1050         vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1051         if (vber == -1)
1052             return -EIO;
1053         status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1054         if (status == -1)
1055             return -EIO;
1056         vber |= (status << 8);
1057         status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1058         if (status == -1)
1059             return -EIO;
1060         vber |= (status & 0x0f) << 16;
1061         // The CVBER_LUT should be read to cope with TDA10046 hardware bug
1062         tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1063 
1064         // if RS has passed some valid TS packets, then we must be
1065         // getting some SYNC bytes
1066         if (vber < 16632)
1067             *fe_status |= FE_HAS_SYNC;
1068     }
1069 
1070     // success
1071     dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
1072     return 0;
1073 }
1074 
1075 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1076 {
1077     struct tda1004x_state* state = fe->demodulator_priv;
1078     int tmp;
1079     int reg = 0;
1080 
1081     dprintk("%s\n", __func__);
1082 
1083     // determine the register to use
1084     switch (state->demod_type) {
1085     case TDA1004X_DEMOD_TDA10045:
1086         reg = TDA10045H_S_AGC;
1087         break;
1088 
1089     case TDA1004X_DEMOD_TDA10046:
1090         reg = TDA10046H_AGC_IF_LEVEL;
1091         break;
1092     }
1093 
1094     // read it
1095     tmp = tda1004x_read_byte(state, reg);
1096     if (tmp < 0)
1097         return -EIO;
1098 
1099     *signal = (tmp << 8) | tmp;
1100     dprintk("%s: signal=0x%x\n", __func__, *signal);
1101     return 0;
1102 }
1103 
1104 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1105 {
1106     struct tda1004x_state* state = fe->demodulator_priv;
1107     int tmp;
1108 
1109     dprintk("%s\n", __func__);
1110 
1111     // read it
1112     tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1113     if (tmp < 0)
1114         return -EIO;
1115     tmp = 255 - tmp;
1116 
1117     *snr = ((tmp << 8) | tmp);
1118     dprintk("%s: snr=0x%x\n", __func__, *snr);
1119     return 0;
1120 }
1121 
1122 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1123 {
1124     struct tda1004x_state* state = fe->demodulator_priv;
1125     int tmp;
1126     int tmp2;
1127     int counter;
1128 
1129     dprintk("%s\n", __func__);
1130 
1131     // read the UCBLOCKS and reset
1132     counter = 0;
1133     tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1134     if (tmp < 0)
1135         return -EIO;
1136     tmp &= 0x7f;
1137     while (counter++ < 5) {
1138         tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1139         tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1140         tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1141 
1142         tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1143         if (tmp2 < 0)
1144             return -EIO;
1145         tmp2 &= 0x7f;
1146         if ((tmp2 < tmp) || (tmp2 == 0))
1147             break;
1148     }
1149 
1150     if (tmp != 0x7f)
1151         *ucblocks = tmp;
1152     else
1153         *ucblocks = 0xffffffff;
1154 
1155     dprintk("%s: ucblocks=0x%x\n", __func__, *ucblocks);
1156     return 0;
1157 }
1158 
1159 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1160 {
1161     struct tda1004x_state* state = fe->demodulator_priv;
1162     int tmp;
1163 
1164     dprintk("%s\n", __func__);
1165 
1166     // read it in
1167     tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1168     if (tmp < 0)
1169         return -EIO;
1170     *ber = tmp << 1;
1171     tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1172     if (tmp < 0)
1173         return -EIO;
1174     *ber |= (tmp << 9);
1175     // The address 0x20 should be read to cope with a TDA10046 bug
1176     tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1177 
1178     dprintk("%s: ber=0x%x\n", __func__, *ber);
1179     return 0;
1180 }
1181 
1182 static int tda1004x_sleep(struct dvb_frontend* fe)
1183 {
1184     struct tda1004x_state* state = fe->demodulator_priv;
1185     int gpio_conf;
1186 
1187     switch (state->demod_type) {
1188     case TDA1004X_DEMOD_TDA10045:
1189         tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1190         break;
1191 
1192     case TDA1004X_DEMOD_TDA10046:
1193         /* set outputs to tristate */
1194         tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
1195         /* invert GPIO 1 and 3 if desired*/
1196         gpio_conf = state->config->gpio_config;
1197         if (gpio_conf >= TDA10046_GP00_I)
1198             tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f,
1199                             (gpio_conf & 0x0f) ^ 0x0a);
1200 
1201         tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0);
1202         tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1203         break;
1204     }
1205 
1206     return 0;
1207 }
1208 
1209 static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
1210 {
1211     struct tda1004x_state* state = fe->demodulator_priv;
1212 
1213     if (enable) {
1214         return tda1004x_enable_tuner_i2c(state);
1215     } else {
1216         return tda1004x_disable_tuner_i2c(state);
1217     }
1218 }
1219 
1220 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1221 {
1222     fesettings->min_delay_ms = 800;
1223     /* Drift compensation makes no sense for DVB-T */
1224     fesettings->step_size = 0;
1225     fesettings->max_drift = 0;
1226     return 0;
1227 }
1228 
1229 static void tda1004x_release(struct dvb_frontend* fe)
1230 {
1231     struct tda1004x_state *state = fe->demodulator_priv;
1232     kfree(state);
1233 }
1234 
1235 static const struct dvb_frontend_ops tda10045_ops = {
1236     .delsys = { SYS_DVBT },
1237     .info = {
1238         .name = "Philips TDA10045H DVB-T",
1239         .frequency_min_hz =  51 * MHz,
1240         .frequency_max_hz = 858 * MHz,
1241         .frequency_stepsize_hz = 166667,
1242         .caps =
1243             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1244             FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1245             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1246             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1247     },
1248 
1249     .release = tda1004x_release,
1250 
1251     .init = tda10045_init,
1252     .sleep = tda1004x_sleep,
1253     .write = tda1004x_write,
1254     .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1255 
1256     .set_frontend = tda1004x_set_fe,
1257     .get_frontend = tda1004x_get_fe,
1258     .get_tune_settings = tda1004x_get_tune_settings,
1259 
1260     .read_status = tda1004x_read_status,
1261     .read_ber = tda1004x_read_ber,
1262     .read_signal_strength = tda1004x_read_signal_strength,
1263     .read_snr = tda1004x_read_snr,
1264     .read_ucblocks = tda1004x_read_ucblocks,
1265 };
1266 
1267 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1268                      struct i2c_adapter* i2c)
1269 {
1270     struct tda1004x_state *state;
1271     int id;
1272 
1273     /* allocate memory for the internal state */
1274     state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1275     if (!state) {
1276         printk(KERN_ERR "Can't allocate memory for tda10045 state\n");
1277         return NULL;
1278     }
1279 
1280     /* setup the state */
1281     state->config = config;
1282     state->i2c = i2c;
1283     state->demod_type = TDA1004X_DEMOD_TDA10045;
1284 
1285     /* check if the demod is there */
1286     id = tda1004x_read_byte(state, TDA1004X_CHIPID);
1287     if (id < 0) {
1288         printk(KERN_ERR "tda10045: chip is not answering. Giving up.\n");
1289         kfree(state);
1290         return NULL;
1291     }
1292 
1293     if (id != 0x25) {
1294         printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
1295         kfree(state);
1296         return NULL;
1297     }
1298 
1299     /* create dvb_frontend */
1300     memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1301     state->frontend.demodulator_priv = state;
1302     return &state->frontend;
1303 }
1304 
1305 static const struct dvb_frontend_ops tda10046_ops = {
1306     .delsys = { SYS_DVBT },
1307     .info = {
1308         .name = "Philips TDA10046H DVB-T",
1309         .frequency_min_hz =  51 * MHz,
1310         .frequency_max_hz = 858 * MHz,
1311         .frequency_stepsize_hz = 166667,
1312         .caps =
1313             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1314             FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1315             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1316             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1317     },
1318 
1319     .release = tda1004x_release,
1320 
1321     .init = tda10046_init,
1322     .sleep = tda1004x_sleep,
1323     .write = tda1004x_write,
1324     .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1325 
1326     .set_frontend = tda1004x_set_fe,
1327     .get_frontend = tda1004x_get_fe,
1328     .get_tune_settings = tda1004x_get_tune_settings,
1329 
1330     .read_status = tda1004x_read_status,
1331     .read_ber = tda1004x_read_ber,
1332     .read_signal_strength = tda1004x_read_signal_strength,
1333     .read_snr = tda1004x_read_snr,
1334     .read_ucblocks = tda1004x_read_ucblocks,
1335 };
1336 
1337 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1338                      struct i2c_adapter* i2c)
1339 {
1340     struct tda1004x_state *state;
1341     int id;
1342 
1343     /* allocate memory for the internal state */
1344     state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1345     if (!state) {
1346         printk(KERN_ERR "Can't allocate memory for tda10046 state\n");
1347         return NULL;
1348     }
1349 
1350     /* setup the state */
1351     state->config = config;
1352     state->i2c = i2c;
1353     state->demod_type = TDA1004X_DEMOD_TDA10046;
1354 
1355     /* check if the demod is there */
1356     id = tda1004x_read_byte(state, TDA1004X_CHIPID);
1357     if (id < 0) {
1358         printk(KERN_ERR "tda10046: chip is not answering. Giving up.\n");
1359         kfree(state);
1360         return NULL;
1361     }
1362     if (id != 0x46) {
1363         printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
1364         kfree(state);
1365         return NULL;
1366     }
1367 
1368     /* create dvb_frontend */
1369     memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1370     state->frontend.demodulator_priv = state;
1371     return &state->frontend;
1372 }
1373 
1374 module_param(debug, int, 0644);
1375 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1376 
1377 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1378 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1379 MODULE_LICENSE("GPL");
1380 
1381 EXPORT_SYMBOL(tda10045_attach);
1382 EXPORT_SYMBOL(tda10046_attach);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!