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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003     NXP TDA10048HN DVB OFDM demodulator driver
0004 
0005     Copyright (C) 2009 Steven Toth <stoth@kernellabs.com>
0006 
0007 
0008 */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/init.h>
0012 #include <linux/module.h>
0013 #include <linux/string.h>
0014 #include <linux/slab.h>
0015 #include <linux/delay.h>
0016 #include <linux/math64.h>
0017 #include <asm/div64.h>
0018 #include <media/dvb_frontend.h>
0019 #include <media/dvb_math.h>
0020 #include "tda10048.h"
0021 
0022 #define TDA10048_DEFAULT_FIRMWARE "dvb-fe-tda10048-1.0.fw"
0023 #define TDA10048_DEFAULT_FIRMWARE_SIZE 24878
0024 
0025 /* Register name definitions */
0026 #define TDA10048_IDENTITY          0x00
0027 #define TDA10048_VERSION           0x01
0028 #define TDA10048_DSP_CODE_CPT      0x0C
0029 #define TDA10048_DSP_CODE_IN       0x0E
0030 #define TDA10048_IN_CONF1          0x10
0031 #define TDA10048_IN_CONF2          0x11
0032 #define TDA10048_IN_CONF3          0x12
0033 #define TDA10048_OUT_CONF1         0x14
0034 #define TDA10048_OUT_CONF2         0x15
0035 #define TDA10048_OUT_CONF3         0x16
0036 #define TDA10048_AUTO              0x18
0037 #define TDA10048_SYNC_STATUS       0x1A
0038 #define TDA10048_CONF_C4_1         0x1E
0039 #define TDA10048_CONF_C4_2         0x1F
0040 #define TDA10048_CODE_IN_RAM       0x20
0041 #define TDA10048_CHANNEL_INFO1_R   0x22
0042 #define TDA10048_CHANNEL_INFO2_R   0x23
0043 #define TDA10048_CHANNEL_INFO1     0x24
0044 #define TDA10048_CHANNEL_INFO2     0x25
0045 #define TDA10048_TIME_ERROR_R      0x26
0046 #define TDA10048_TIME_ERROR        0x27
0047 #define TDA10048_FREQ_ERROR_LSB_R  0x28
0048 #define TDA10048_FREQ_ERROR_MSB_R  0x29
0049 #define TDA10048_FREQ_ERROR_LSB    0x2A
0050 #define TDA10048_FREQ_ERROR_MSB    0x2B
0051 #define TDA10048_IT_SEL            0x30
0052 #define TDA10048_IT_STAT           0x32
0053 #define TDA10048_DSP_AD_LSB        0x3C
0054 #define TDA10048_DSP_AD_MSB        0x3D
0055 #define TDA10048_DSP_REG_LSB       0x3E
0056 #define TDA10048_DSP_REG_MSB       0x3F
0057 #define TDA10048_CONF_TRISTATE1    0x44
0058 #define TDA10048_CONF_TRISTATE2    0x45
0059 #define TDA10048_CONF_POLARITY     0x46
0060 #define TDA10048_GPIO_SP_DS0       0x48
0061 #define TDA10048_GPIO_SP_DS1       0x49
0062 #define TDA10048_GPIO_SP_DS2       0x4A
0063 #define TDA10048_GPIO_SP_DS3       0x4B
0064 #define TDA10048_GPIO_OUT_SEL      0x4C
0065 #define TDA10048_GPIO_SELECT       0x4D
0066 #define TDA10048_IC_MODE           0x4E
0067 #define TDA10048_CONF_XO           0x50
0068 #define TDA10048_CONF_PLL1         0x51
0069 #define TDA10048_CONF_PLL2         0x52
0070 #define TDA10048_CONF_PLL3         0x53
0071 #define TDA10048_CONF_ADC          0x54
0072 #define TDA10048_CONF_ADC_2        0x55
0073 #define TDA10048_CONF_C1_1         0x60
0074 #define TDA10048_CONF_C1_3         0x62
0075 #define TDA10048_AGC_CONF          0x70
0076 #define TDA10048_AGC_THRESHOLD_LSB 0x72
0077 #define TDA10048_AGC_THRESHOLD_MSB 0x73
0078 #define TDA10048_AGC_RENORM        0x74
0079 #define TDA10048_AGC_GAINS         0x76
0080 #define TDA10048_AGC_TUN_MIN       0x78
0081 #define TDA10048_AGC_TUN_MAX       0x79
0082 #define TDA10048_AGC_IF_MIN        0x7A
0083 #define TDA10048_AGC_IF_MAX        0x7B
0084 #define TDA10048_AGC_TUN_LEVEL     0x7E
0085 #define TDA10048_AGC_IF_LEVEL      0x7F
0086 #define TDA10048_DIG_AGC_LEVEL     0x81
0087 #define TDA10048_FREQ_PHY2_LSB     0x86
0088 #define TDA10048_FREQ_PHY2_MSB     0x87
0089 #define TDA10048_TIME_INVWREF_LSB  0x88
0090 #define TDA10048_TIME_INVWREF_MSB  0x89
0091 #define TDA10048_TIME_WREF_LSB     0x8A
0092 #define TDA10048_TIME_WREF_MID1    0x8B
0093 #define TDA10048_TIME_WREF_MID2    0x8C
0094 #define TDA10048_TIME_WREF_MSB     0x8D
0095 #define TDA10048_NP_OUT            0xA2
0096 #define TDA10048_CELL_ID_LSB       0xA4
0097 #define TDA10048_CELL_ID_MSB       0xA5
0098 #define TDA10048_EXTTPS_ODD        0xAA
0099 #define TDA10048_EXTTPS_EVEN       0xAB
0100 #define TDA10048_TPS_LENGTH        0xAC
0101 #define TDA10048_FREE_REG_1        0xB2
0102 #define TDA10048_FREE_REG_2        0xB3
0103 #define TDA10048_CONF_C3_1         0xC0
0104 #define TDA10048_CVBER_CTRL        0xC2
0105 #define TDA10048_CBER_NMAX_LSB     0xC4
0106 #define TDA10048_CBER_NMAX_MSB     0xC5
0107 #define TDA10048_CBER_LSB          0xC6
0108 #define TDA10048_CBER_MSB          0xC7
0109 #define TDA10048_VBER_LSB          0xC8
0110 #define TDA10048_VBER_MID          0xC9
0111 #define TDA10048_VBER_MSB          0xCA
0112 #define TDA10048_CVBER_LUT         0xCC
0113 #define TDA10048_UNCOR_CTRL        0xCD
0114 #define TDA10048_UNCOR_CPT_LSB     0xCE
0115 #define TDA10048_UNCOR_CPT_MSB     0xCF
0116 #define TDA10048_SOFT_IT_C3        0xD6
0117 #define TDA10048_CONF_TS2          0xE0
0118 #define TDA10048_CONF_TS1          0xE1
0119 
0120 static unsigned int debug;
0121 
0122 #define dprintk(level, fmt, arg...)\
0123     do { if (debug >= level)\
0124         printk(KERN_DEBUG "tda10048: " fmt, ## arg);\
0125     } while (0)
0126 
0127 struct tda10048_state {
0128 
0129     struct i2c_adapter *i2c;
0130 
0131     /* We'll cache and update the attach config settings */
0132     struct tda10048_config config;
0133     struct dvb_frontend frontend;
0134 
0135     int fwloaded;
0136 
0137     u32 freq_if_hz;
0138     u32 xtal_hz;
0139     u32 pll_mfactor;
0140     u32 pll_nfactor;
0141     u32 pll_pfactor;
0142     u32 sample_freq;
0143 
0144     u32 bandwidth;
0145 };
0146 
0147 static struct init_tab {
0148     u8  reg;
0149     u16 data;
0150 } init_tab[] = {
0151     { TDA10048_CONF_PLL1, 0x08 },
0152     { TDA10048_CONF_ADC_2, 0x00 },
0153     { TDA10048_CONF_C4_1, 0x00 },
0154     { TDA10048_CONF_PLL1, 0x0f },
0155     { TDA10048_CONF_PLL2, 0x0a },
0156     { TDA10048_CONF_PLL3, 0x43 },
0157     { TDA10048_FREQ_PHY2_LSB, 0x02 },
0158     { TDA10048_FREQ_PHY2_MSB, 0x0a },
0159     { TDA10048_TIME_WREF_LSB, 0xbd },
0160     { TDA10048_TIME_WREF_MID1, 0xe4 },
0161     { TDA10048_TIME_WREF_MID2, 0xa8 },
0162     { TDA10048_TIME_WREF_MSB, 0x02 },
0163     { TDA10048_TIME_INVWREF_LSB, 0x04 },
0164     { TDA10048_TIME_INVWREF_MSB, 0x06 },
0165     { TDA10048_CONF_C4_1, 0x00 },
0166     { TDA10048_CONF_C1_1, 0xa8 },
0167     { TDA10048_AGC_CONF, 0x16 },
0168     { TDA10048_CONF_C1_3, 0x0b },
0169     { TDA10048_AGC_TUN_MIN, 0x00 },
0170     { TDA10048_AGC_TUN_MAX, 0xff },
0171     { TDA10048_AGC_IF_MIN, 0x00 },
0172     { TDA10048_AGC_IF_MAX, 0xff },
0173     { TDA10048_AGC_THRESHOLD_MSB, 0x00 },
0174     { TDA10048_AGC_THRESHOLD_LSB, 0x70 },
0175     { TDA10048_CVBER_CTRL, 0x38 },
0176     { TDA10048_AGC_GAINS, 0x12 },
0177     { TDA10048_CONF_XO, 0x00 },
0178     { TDA10048_CONF_TS1, 0x07 },
0179     { TDA10048_IC_MODE, 0x00 },
0180     { TDA10048_CONF_TS2, 0xc0 },
0181     { TDA10048_CONF_TRISTATE1, 0x21 },
0182     { TDA10048_CONF_TRISTATE2, 0x00 },
0183     { TDA10048_CONF_POLARITY, 0x00 },
0184     { TDA10048_CONF_C4_2, 0x04 },
0185     { TDA10048_CONF_ADC, 0x60 },
0186     { TDA10048_CONF_ADC_2, 0x10 },
0187     { TDA10048_CONF_ADC, 0x60 },
0188     { TDA10048_CONF_ADC_2, 0x00 },
0189     { TDA10048_CONF_C1_1, 0xa8 },
0190     { TDA10048_UNCOR_CTRL, 0x00 },
0191     { TDA10048_CONF_C4_2, 0x04 },
0192 };
0193 
0194 static struct pll_tab {
0195     u32 clk_freq_khz;
0196     u32 if_freq_khz;
0197 } pll_tab[] = {
0198     { TDA10048_CLK_4000,  TDA10048_IF_36130 },
0199     { TDA10048_CLK_16000, TDA10048_IF_3300 },
0200     { TDA10048_CLK_16000, TDA10048_IF_3500 },
0201     { TDA10048_CLK_16000, TDA10048_IF_3800 },
0202     { TDA10048_CLK_16000, TDA10048_IF_4000 },
0203     { TDA10048_CLK_16000, TDA10048_IF_4300 },
0204     { TDA10048_CLK_16000, TDA10048_IF_4500 },
0205     { TDA10048_CLK_16000, TDA10048_IF_5000 },
0206     { TDA10048_CLK_16000, TDA10048_IF_36130 },
0207 };
0208 
0209 static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data)
0210 {
0211     struct tda10048_config *config = &state->config;
0212     int ret;
0213     u8 buf[] = { reg, data };
0214     struct i2c_msg msg = {
0215         .addr = config->demod_address,
0216         .flags = 0, .buf = buf, .len = 2 };
0217 
0218     dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data);
0219 
0220     ret = i2c_transfer(state->i2c, &msg, 1);
0221 
0222     if (ret != 1)
0223         printk("%s: writereg error (ret == %i)\n", __func__, ret);
0224 
0225     return (ret != 1) ? -1 : 0;
0226 }
0227 
0228 static u8 tda10048_readreg(struct tda10048_state *state, u8 reg)
0229 {
0230     struct tda10048_config *config = &state->config;
0231     int ret;
0232     u8 b0[] = { reg };
0233     u8 b1[] = { 0 };
0234     struct i2c_msg msg[] = {
0235         { .addr = config->demod_address,
0236             .flags = 0, .buf = b0, .len = 1 },
0237         { .addr = config->demod_address,
0238             .flags = I2C_M_RD, .buf = b1, .len = 1 } };
0239 
0240     dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg);
0241 
0242     ret = i2c_transfer(state->i2c, msg, 2);
0243 
0244     if (ret != 2)
0245         printk(KERN_ERR "%s: readreg error (ret == %i)\n",
0246             __func__, ret);
0247 
0248     return b1[0];
0249 }
0250 
0251 static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg,
0252                  const u8 *data, u16 len)
0253 {
0254     struct tda10048_config *config = &state->config;
0255     int ret = -EREMOTEIO;
0256     struct i2c_msg msg;
0257     u8 *buf;
0258 
0259     dprintk(2, "%s(%d, ?, len = %d)\n", __func__, reg, len);
0260 
0261     buf = kmalloc(len + 1, GFP_KERNEL);
0262     if (buf == NULL) {
0263         ret = -ENOMEM;
0264         goto error;
0265     }
0266 
0267     *buf = reg;
0268     memcpy(buf + 1, data, len);
0269 
0270     msg.addr = config->demod_address;
0271     msg.flags = 0;
0272     msg.buf = buf;
0273     msg.len = len + 1;
0274 
0275     dprintk(2, "%s():  write len = %d\n",
0276         __func__, msg.len);
0277 
0278     ret = i2c_transfer(state->i2c, &msg, 1);
0279     if (ret != 1) {
0280         printk(KERN_ERR "%s(): writereg error err %i\n",
0281              __func__, ret);
0282         ret = -EREMOTEIO;
0283     }
0284 
0285 error:
0286     kfree(buf);
0287 
0288     return ret;
0289 }
0290 
0291 static int tda10048_set_phy2(struct dvb_frontend *fe, u32 sample_freq_hz,
0292                  u32 if_hz)
0293 {
0294     struct tda10048_state *state = fe->demodulator_priv;
0295     u64 t;
0296 
0297     dprintk(1, "%s()\n", __func__);
0298 
0299     if (sample_freq_hz == 0)
0300         return -EINVAL;
0301 
0302     if (if_hz < (sample_freq_hz / 2)) {
0303         /* PHY2 = (if2/fs) * 2^15 */
0304         t = if_hz;
0305         t *= 10;
0306         t *= 32768;
0307         do_div(t, sample_freq_hz);
0308         t += 5;
0309         do_div(t, 10);
0310     } else {
0311         /* PHY2 = ((IF1-fs)/fs) * 2^15 */
0312         t = sample_freq_hz - if_hz;
0313         t *= 10;
0314         t *= 32768;
0315         do_div(t, sample_freq_hz);
0316         t += 5;
0317         do_div(t, 10);
0318         t = ~t + 1;
0319     }
0320 
0321     tda10048_writereg(state, TDA10048_FREQ_PHY2_LSB, (u8)t);
0322     tda10048_writereg(state, TDA10048_FREQ_PHY2_MSB, (u8)(t >> 8));
0323 
0324     return 0;
0325 }
0326 
0327 static int tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz,
0328                  u32 bw)
0329 {
0330     struct tda10048_state *state = fe->demodulator_priv;
0331     u64 t, z;
0332 
0333     dprintk(1, "%s()\n", __func__);
0334 
0335     if (sample_freq_hz == 0)
0336         return -EINVAL;
0337 
0338     /* WREF = (B / (7 * fs)) * 2^31 */
0339     t = bw * 10;
0340     /* avoid warning: this decimal constant is unsigned only in ISO C90 */
0341     /* t *= 2147483648 on 32bit platforms */
0342     t *= (2048 * 1024);
0343     t *= 1024;
0344     z = 7 * sample_freq_hz;
0345     do_div(t, z);
0346     t += 5;
0347     do_div(t, 10);
0348 
0349     tda10048_writereg(state, TDA10048_TIME_WREF_LSB, (u8)t);
0350     tda10048_writereg(state, TDA10048_TIME_WREF_MID1, (u8)(t >> 8));
0351     tda10048_writereg(state, TDA10048_TIME_WREF_MID2, (u8)(t >> 16));
0352     tda10048_writereg(state, TDA10048_TIME_WREF_MSB, (u8)(t >> 24));
0353 
0354     return 0;
0355 }
0356 
0357 static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz,
0358                 u32 bw)
0359 {
0360     struct tda10048_state *state = fe->demodulator_priv;
0361     u64 t;
0362 
0363     dprintk(1, "%s()\n", __func__);
0364 
0365     if (sample_freq_hz == 0)
0366         return -EINVAL;
0367 
0368     /* INVWREF = ((7 * fs) / B) * 2^5 */
0369     t = sample_freq_hz;
0370     t *= 7;
0371     t *= 32;
0372     t *= 10;
0373     do_div(t, bw);
0374     t += 5;
0375     do_div(t, 10);
0376 
0377     tda10048_writereg(state, TDA10048_TIME_INVWREF_LSB, (u8)t);
0378     tda10048_writereg(state, TDA10048_TIME_INVWREF_MSB, (u8)(t >> 8));
0379 
0380     return 0;
0381 }
0382 
0383 static int tda10048_set_bandwidth(struct dvb_frontend *fe,
0384     u32 bw)
0385 {
0386     struct tda10048_state *state = fe->demodulator_priv;
0387     dprintk(1, "%s(bw=%d)\n", __func__, bw);
0388 
0389     /* Bandwidth setting may need to be adjusted */
0390     switch (bw) {
0391     case 6000000:
0392     case 7000000:
0393     case 8000000:
0394         tda10048_set_wref(fe, state->sample_freq, bw);
0395         tda10048_set_invwref(fe, state->sample_freq, bw);
0396         break;
0397     default:
0398         printk(KERN_ERR "%s() invalid bandwidth\n", __func__);
0399         return -EINVAL;
0400     }
0401 
0402     state->bandwidth = bw;
0403 
0404     return 0;
0405 }
0406 
0407 static int tda10048_set_if(struct dvb_frontend *fe, u32 bw)
0408 {
0409     struct tda10048_state *state = fe->demodulator_priv;
0410     struct tda10048_config *config = &state->config;
0411     int i;
0412     u32 if_freq_khz;
0413 
0414     dprintk(1, "%s(bw = %d)\n", __func__, bw);
0415 
0416     /* based on target bandwidth and clk we calculate pll factors */
0417     switch (bw) {
0418     case 6000000:
0419         if_freq_khz = config->dtv6_if_freq_khz;
0420         break;
0421     case 7000000:
0422         if_freq_khz = config->dtv7_if_freq_khz;
0423         break;
0424     case 8000000:
0425         if_freq_khz = config->dtv8_if_freq_khz;
0426         break;
0427     default:
0428         printk(KERN_ERR "%s() no default\n", __func__);
0429         return -EINVAL;
0430     }
0431 
0432     for (i = 0; i < ARRAY_SIZE(pll_tab); i++) {
0433         if ((pll_tab[i].clk_freq_khz == config->clk_freq_khz) &&
0434             (pll_tab[i].if_freq_khz == if_freq_khz)) {
0435 
0436             state->freq_if_hz = pll_tab[i].if_freq_khz * 1000;
0437             state->xtal_hz = pll_tab[i].clk_freq_khz * 1000;
0438             break;
0439         }
0440     }
0441     if (i == ARRAY_SIZE(pll_tab)) {
0442         printk(KERN_ERR "%s() Incorrect attach settings\n",
0443             __func__);
0444         return -EINVAL;
0445     }
0446 
0447     dprintk(1, "- freq_if_hz = %d\n", state->freq_if_hz);
0448     dprintk(1, "- xtal_hz = %d\n", state->xtal_hz);
0449     dprintk(1, "- pll_mfactor = %d\n", state->pll_mfactor);
0450     dprintk(1, "- pll_nfactor = %d\n", state->pll_nfactor);
0451     dprintk(1, "- pll_pfactor = %d\n", state->pll_pfactor);
0452 
0453     /* Calculate the sample frequency */
0454     state->sample_freq = state->xtal_hz * (state->pll_mfactor + 45);
0455     state->sample_freq /= (state->pll_nfactor + 1);
0456     state->sample_freq /= (state->pll_pfactor + 4);
0457     dprintk(1, "- sample_freq = %d\n", state->sample_freq);
0458 
0459     /* Update the I/F */
0460     tda10048_set_phy2(fe, state->sample_freq, state->freq_if_hz);
0461 
0462     return 0;
0463 }
0464 
0465 static int tda10048_firmware_upload(struct dvb_frontend *fe)
0466 {
0467     struct tda10048_state *state = fe->demodulator_priv;
0468     struct tda10048_config *config = &state->config;
0469     const struct firmware *fw;
0470     int ret;
0471     int pos = 0;
0472     int cnt;
0473     u8 wlen = config->fwbulkwritelen;
0474 
0475     if ((wlen != TDA10048_BULKWRITE_200) && (wlen != TDA10048_BULKWRITE_50))
0476         wlen = TDA10048_BULKWRITE_200;
0477 
0478     /* request the firmware, this will block and timeout */
0479     printk(KERN_INFO "%s: waiting for firmware upload (%s)...\n",
0480         __func__,
0481         TDA10048_DEFAULT_FIRMWARE);
0482 
0483     ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE,
0484         state->i2c->dev.parent);
0485     if (ret) {
0486         printk(KERN_ERR "%s: Upload failed. (file not found?)\n",
0487             __func__);
0488         return -EIO;
0489     } else {
0490         printk(KERN_INFO "%s: firmware read %zu bytes.\n",
0491             __func__,
0492             fw->size);
0493         ret = 0;
0494     }
0495 
0496     if (fw->size != TDA10048_DEFAULT_FIRMWARE_SIZE) {
0497         printk(KERN_ERR "%s: firmware incorrect size\n", __func__);
0498         ret = -EIO;
0499     } else {
0500         printk(KERN_INFO "%s: firmware uploading\n", __func__);
0501 
0502         /* Soft reset */
0503         tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
0504             tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
0505                 & 0xfe);
0506         tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
0507             tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
0508                 | 0x01);
0509 
0510         /* Put the demod into host download mode */
0511         tda10048_writereg(state, TDA10048_CONF_C4_1,
0512             tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xf9);
0513 
0514         /* Boot the DSP */
0515         tda10048_writereg(state, TDA10048_CONF_C4_1,
0516             tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x08);
0517 
0518         /* Prepare for download */
0519         tda10048_writereg(state, TDA10048_DSP_CODE_CPT, 0);
0520 
0521         /* Download the firmware payload */
0522         while (pos < fw->size) {
0523 
0524             if ((fw->size - pos) > wlen)
0525                 cnt = wlen;
0526             else
0527                 cnt = fw->size - pos;
0528 
0529             tda10048_writeregbulk(state, TDA10048_DSP_CODE_IN,
0530                 &fw->data[pos], cnt);
0531 
0532             pos += cnt;
0533         }
0534 
0535         ret = -EIO;
0536         /* Wait up to 250ms for the DSP to boot */
0537         for (cnt = 0; cnt < 250 ; cnt += 10) {
0538 
0539             msleep(10);
0540 
0541             if (tda10048_readreg(state, TDA10048_SYNC_STATUS)
0542                 & 0x40) {
0543                 ret = 0;
0544                 break;
0545             }
0546         }
0547     }
0548 
0549     release_firmware(fw);
0550 
0551     if (ret == 0) {
0552         printk(KERN_INFO "%s: firmware uploaded\n", __func__);
0553         state->fwloaded = 1;
0554     } else
0555         printk(KERN_ERR "%s: firmware upload failed\n", __func__);
0556 
0557     return ret;
0558 }
0559 
0560 static int tda10048_set_inversion(struct dvb_frontend *fe, int inversion)
0561 {
0562     struct tda10048_state *state = fe->demodulator_priv;
0563 
0564     dprintk(1, "%s(%d)\n", __func__, inversion);
0565 
0566     if (inversion == TDA10048_INVERSION_ON)
0567         tda10048_writereg(state, TDA10048_CONF_C1_1,
0568             tda10048_readreg(state, TDA10048_CONF_C1_1) | 0x20);
0569     else
0570         tda10048_writereg(state, TDA10048_CONF_C1_1,
0571             tda10048_readreg(state, TDA10048_CONF_C1_1) & 0xdf);
0572 
0573     return 0;
0574 }
0575 
0576 /* Retrieve the demod settings */
0577 static int tda10048_get_tps(struct tda10048_state *state,
0578     struct dtv_frontend_properties *p)
0579 {
0580     u8 val;
0581 
0582     /* Make sure the TPS regs are valid */
0583     if (!(tda10048_readreg(state, TDA10048_AUTO) & 0x01))
0584         return -EAGAIN;
0585 
0586     val = tda10048_readreg(state, TDA10048_OUT_CONF2);
0587     switch ((val & 0x60) >> 5) {
0588     case 0:
0589         p->modulation = QPSK;
0590         break;
0591     case 1:
0592         p->modulation = QAM_16;
0593         break;
0594     case 2:
0595         p->modulation = QAM_64;
0596         break;
0597     }
0598     switch ((val & 0x18) >> 3) {
0599     case 0:
0600         p->hierarchy = HIERARCHY_NONE;
0601         break;
0602     case 1:
0603         p->hierarchy = HIERARCHY_1;
0604         break;
0605     case 2:
0606         p->hierarchy = HIERARCHY_2;
0607         break;
0608     case 3:
0609         p->hierarchy = HIERARCHY_4;
0610         break;
0611     }
0612     switch (val & 0x07) {
0613     case 0:
0614         p->code_rate_HP = FEC_1_2;
0615         break;
0616     case 1:
0617         p->code_rate_HP = FEC_2_3;
0618         break;
0619     case 2:
0620         p->code_rate_HP = FEC_3_4;
0621         break;
0622     case 3:
0623         p->code_rate_HP = FEC_5_6;
0624         break;
0625     case 4:
0626         p->code_rate_HP = FEC_7_8;
0627         break;
0628     }
0629 
0630     val = tda10048_readreg(state, TDA10048_OUT_CONF3);
0631     switch (val & 0x07) {
0632     case 0:
0633         p->code_rate_LP = FEC_1_2;
0634         break;
0635     case 1:
0636         p->code_rate_LP = FEC_2_3;
0637         break;
0638     case 2:
0639         p->code_rate_LP = FEC_3_4;
0640         break;
0641     case 3:
0642         p->code_rate_LP = FEC_5_6;
0643         break;
0644     case 4:
0645         p->code_rate_LP = FEC_7_8;
0646         break;
0647     }
0648 
0649     val = tda10048_readreg(state, TDA10048_OUT_CONF1);
0650     switch ((val & 0x0c) >> 2) {
0651     case 0:
0652         p->guard_interval = GUARD_INTERVAL_1_32;
0653         break;
0654     case 1:
0655         p->guard_interval = GUARD_INTERVAL_1_16;
0656         break;
0657     case 2:
0658         p->guard_interval =  GUARD_INTERVAL_1_8;
0659         break;
0660     case 3:
0661         p->guard_interval =  GUARD_INTERVAL_1_4;
0662         break;
0663     }
0664     switch (val & 0x03) {
0665     case 0:
0666         p->transmission_mode = TRANSMISSION_MODE_2K;
0667         break;
0668     case 1:
0669         p->transmission_mode = TRANSMISSION_MODE_8K;
0670         break;
0671     }
0672 
0673     return 0;
0674 }
0675 
0676 static int tda10048_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
0677 {
0678     struct tda10048_state *state = fe->demodulator_priv;
0679     struct tda10048_config *config = &state->config;
0680     dprintk(1, "%s(%d)\n", __func__, enable);
0681 
0682     if (config->disable_gate_access)
0683         return 0;
0684 
0685     if (enable)
0686         return tda10048_writereg(state, TDA10048_CONF_C4_1,
0687             tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02);
0688     else
0689         return tda10048_writereg(state, TDA10048_CONF_C4_1,
0690             tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xfd);
0691 }
0692 
0693 static int tda10048_output_mode(struct dvb_frontend *fe, int serial)
0694 {
0695     struct tda10048_state *state = fe->demodulator_priv;
0696     dprintk(1, "%s(%d)\n", __func__, serial);
0697 
0698     /* Ensure pins are out of tri-state */
0699     tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 0x21);
0700     tda10048_writereg(state, TDA10048_CONF_TRISTATE2, 0x00);
0701 
0702     if (serial) {
0703         tda10048_writereg(state, TDA10048_IC_MODE, 0x80 | 0x20);
0704         tda10048_writereg(state, TDA10048_CONF_TS2, 0xc0);
0705     } else {
0706         tda10048_writereg(state, TDA10048_IC_MODE, 0x00);
0707         tda10048_writereg(state, TDA10048_CONF_TS2, 0x01);
0708     }
0709 
0710     return 0;
0711 }
0712 
0713 /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
0714 /* TODO: Support manual tuning with specific params */
0715 static int tda10048_set_frontend(struct dvb_frontend *fe)
0716 {
0717     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0718     struct tda10048_state *state = fe->demodulator_priv;
0719 
0720     dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency);
0721 
0722     /* Update the I/F pll's if the bandwidth changes */
0723     if (p->bandwidth_hz != state->bandwidth) {
0724         tda10048_set_if(fe, p->bandwidth_hz);
0725         tda10048_set_bandwidth(fe, p->bandwidth_hz);
0726     }
0727 
0728     if (fe->ops.tuner_ops.set_params) {
0729 
0730         if (fe->ops.i2c_gate_ctrl)
0731             fe->ops.i2c_gate_ctrl(fe, 1);
0732 
0733         fe->ops.tuner_ops.set_params(fe);
0734 
0735         if (fe->ops.i2c_gate_ctrl)
0736             fe->ops.i2c_gate_ctrl(fe, 0);
0737     }
0738 
0739     /* Enable demod TPS auto detection and begin acquisition */
0740     tda10048_writereg(state, TDA10048_AUTO, 0x57);
0741     /* trigger cber and vber acquisition */
0742     tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x3B);
0743 
0744     return 0;
0745 }
0746 
0747 /* Establish sane defaults and load firmware. */
0748 static int tda10048_init(struct dvb_frontend *fe)
0749 {
0750     struct tda10048_state *state = fe->demodulator_priv;
0751     struct tda10048_config *config = &state->config;
0752     int ret = 0, i;
0753 
0754     dprintk(1, "%s()\n", __func__);
0755 
0756     /* PLL */
0757     init_tab[4].data = (u8)(state->pll_mfactor);
0758     init_tab[5].data = (u8)(state->pll_nfactor) | 0x40;
0759 
0760     /* Apply register defaults */
0761     for (i = 0; i < ARRAY_SIZE(init_tab); i++)
0762         tda10048_writereg(state, init_tab[i].reg, init_tab[i].data);
0763 
0764     if (state->fwloaded == 0)
0765         ret = tda10048_firmware_upload(fe);
0766 
0767     /* Set either serial or parallel */
0768     tda10048_output_mode(fe, config->output_mode);
0769 
0770     /* Set inversion */
0771     tda10048_set_inversion(fe, config->inversion);
0772 
0773     /* Establish default RF values */
0774     tda10048_set_if(fe, 8000000);
0775     tda10048_set_bandwidth(fe, 8000000);
0776 
0777     /* Ensure we leave the gate closed */
0778     tda10048_i2c_gate_ctrl(fe, 0);
0779 
0780     return ret;
0781 }
0782 
0783 static int tda10048_read_status(struct dvb_frontend *fe, enum fe_status *status)
0784 {
0785     struct tda10048_state *state = fe->demodulator_priv;
0786     u8 reg;
0787 
0788     *status = 0;
0789 
0790     reg = tda10048_readreg(state, TDA10048_SYNC_STATUS);
0791 
0792     dprintk(1, "%s() status =0x%02x\n", __func__, reg);
0793 
0794     if (reg & 0x02)
0795         *status |= FE_HAS_CARRIER;
0796 
0797     if (reg & 0x04)
0798         *status |= FE_HAS_SIGNAL;
0799 
0800     if (reg & 0x08) {
0801         *status |= FE_HAS_LOCK;
0802         *status |= FE_HAS_VITERBI;
0803         *status |= FE_HAS_SYNC;
0804     }
0805 
0806     return 0;
0807 }
0808 
0809 static int tda10048_read_ber(struct dvb_frontend *fe, u32 *ber)
0810 {
0811     struct tda10048_state *state = fe->demodulator_priv;
0812     static u32 cber_current;
0813     u32 cber_nmax;
0814     u64 cber_tmp;
0815 
0816     dprintk(1, "%s()\n", __func__);
0817 
0818     /* update cber on interrupt */
0819     if (tda10048_readreg(state, TDA10048_SOFT_IT_C3) & 0x01) {
0820         cber_tmp = tda10048_readreg(state, TDA10048_CBER_MSB) << 8 |
0821             tda10048_readreg(state, TDA10048_CBER_LSB);
0822         cber_nmax = tda10048_readreg(state, TDA10048_CBER_NMAX_MSB) << 8 |
0823             tda10048_readreg(state, TDA10048_CBER_NMAX_LSB);
0824         cber_tmp *= 100000000;
0825         cber_tmp *= 2;
0826         cber_tmp = div_u64(cber_tmp, (cber_nmax * 32) + 1);
0827         cber_current = (u32)cber_tmp;
0828         /* retrigger cber acquisition */
0829         tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x39);
0830     }
0831     /* actual cber is (*ber)/1e8 */
0832     *ber = cber_current;
0833 
0834     return 0;
0835 }
0836 
0837 static int tda10048_read_signal_strength(struct dvb_frontend *fe,
0838     u16 *signal_strength)
0839 {
0840     struct tda10048_state *state = fe->demodulator_priv;
0841     u8 v;
0842 
0843     dprintk(1, "%s()\n", __func__);
0844 
0845     *signal_strength = 65535;
0846 
0847     v = tda10048_readreg(state, TDA10048_NP_OUT);
0848     if (v > 0)
0849         *signal_strength -= (v << 8) | v;
0850 
0851     return 0;
0852 }
0853 
0854 /* SNR lookup table */
0855 static struct snr_tab {
0856     u8 val;
0857     u8 data;
0858 } snr_tab[] = {
0859     {   0,   0 },
0860     {   1, 246 },
0861     {   2, 215 },
0862     {   3, 198 },
0863     {   4, 185 },
0864     {   5, 176 },
0865     {   6, 168 },
0866     {   7, 161 },
0867     {   8, 155 },
0868     {   9, 150 },
0869     {  10, 146 },
0870     {  11, 141 },
0871     {  12, 138 },
0872     {  13, 134 },
0873     {  14, 131 },
0874     {  15, 128 },
0875     {  16, 125 },
0876     {  17, 122 },
0877     {  18, 120 },
0878     {  19, 118 },
0879     {  20, 115 },
0880     {  21, 113 },
0881     {  22, 111 },
0882     {  23, 109 },
0883     {  24, 107 },
0884     {  25, 106 },
0885     {  26, 104 },
0886     {  27, 102 },
0887     {  28, 101 },
0888     {  29,  99 },
0889     {  30,  98 },
0890     {  31,  96 },
0891     {  32,  95 },
0892     {  33,  94 },
0893     {  34,  92 },
0894     {  35,  91 },
0895     {  36,  90 },
0896     {  37,  89 },
0897     {  38,  88 },
0898     {  39,  86 },
0899     {  40,  85 },
0900     {  41,  84 },
0901     {  42,  83 },
0902     {  43,  82 },
0903     {  44,  81 },
0904     {  45,  80 },
0905     {  46,  79 },
0906     {  47,  78 },
0907     {  48,  77 },
0908     {  49,  76 },
0909     {  50,  76 },
0910     {  51,  75 },
0911     {  52,  74 },
0912     {  53,  73 },
0913     {  54,  72 },
0914     {  56,  71 },
0915     {  57,  70 },
0916     {  58,  69 },
0917     {  60,  68 },
0918     {  61,  67 },
0919     {  63,  66 },
0920     {  64,  65 },
0921     {  66,  64 },
0922     {  67,  63 },
0923     {  68,  62 },
0924     {  69,  62 },
0925     {  70,  61 },
0926     {  72,  60 },
0927     {  74,  59 },
0928     {  75,  58 },
0929     {  77,  57 },
0930     {  79,  56 },
0931     {  81,  55 },
0932     {  83,  54 },
0933     {  85,  53 },
0934     {  87,  52 },
0935     {  89,  51 },
0936     {  91,  50 },
0937     {  93,  49 },
0938     {  95,  48 },
0939     {  97,  47 },
0940     { 100,  46 },
0941     { 102,  45 },
0942     { 104,  44 },
0943     { 107,  43 },
0944     { 109,  42 },
0945     { 112,  41 },
0946     { 114,  40 },
0947     { 117,  39 },
0948     { 120,  38 },
0949     { 123,  37 },
0950     { 125,  36 },
0951     { 128,  35 },
0952     { 131,  34 },
0953     { 134,  33 },
0954     { 138,  32 },
0955     { 141,  31 },
0956     { 144,  30 },
0957     { 147,  29 },
0958     { 151,  28 },
0959     { 154,  27 },
0960     { 158,  26 },
0961     { 162,  25 },
0962     { 165,  24 },
0963     { 169,  23 },
0964     { 173,  22 },
0965     { 177,  21 },
0966     { 181,  20 },
0967     { 186,  19 },
0968     { 190,  18 },
0969     { 194,  17 },
0970     { 199,  16 },
0971     { 204,  15 },
0972     { 208,  14 },
0973     { 213,  13 },
0974     { 218,  12 },
0975     { 223,  11 },
0976     { 229,  10 },
0977     { 234,   9 },
0978     { 239,   8 },
0979     { 245,   7 },
0980     { 251,   6 },
0981     { 255,   5 },
0982 };
0983 
0984 static int tda10048_read_snr(struct dvb_frontend *fe, u16 *snr)
0985 {
0986     struct tda10048_state *state = fe->demodulator_priv;
0987     u8 v;
0988     int i, ret = -EINVAL;
0989 
0990     dprintk(1, "%s()\n", __func__);
0991 
0992     v = tda10048_readreg(state, TDA10048_NP_OUT);
0993     for (i = 0; i < ARRAY_SIZE(snr_tab); i++) {
0994         if (v <= snr_tab[i].val) {
0995             *snr = snr_tab[i].data;
0996             ret = 0;
0997             break;
0998         }
0999     }
1000 
1001     return ret;
1002 }
1003 
1004 static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1005 {
1006     struct tda10048_state *state = fe->demodulator_priv;
1007 
1008     dprintk(1, "%s()\n", __func__);
1009 
1010     *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 |
1011         tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB);
1012     /* clear the uncorrected TS packets counter when saturated */
1013     if (*ucblocks == 0xFFFF)
1014         tda10048_writereg(state, TDA10048_UNCOR_CTRL, 0x80);
1015 
1016     return 0;
1017 }
1018 
1019 static int tda10048_get_frontend(struct dvb_frontend *fe,
1020                  struct dtv_frontend_properties *p)
1021 {
1022     struct tda10048_state *state = fe->demodulator_priv;
1023 
1024     dprintk(1, "%s()\n", __func__);
1025 
1026     p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1)
1027         & 0x20 ? INVERSION_ON : INVERSION_OFF;
1028 
1029     return tda10048_get_tps(state, p);
1030 }
1031 
1032 static int tda10048_get_tune_settings(struct dvb_frontend *fe,
1033     struct dvb_frontend_tune_settings *tune)
1034 {
1035     tune->min_delay_ms = 1000;
1036     return 0;
1037 }
1038 
1039 static void tda10048_release(struct dvb_frontend *fe)
1040 {
1041     struct tda10048_state *state = fe->demodulator_priv;
1042     dprintk(1, "%s()\n", __func__);
1043     kfree(state);
1044 }
1045 
1046 static void tda10048_establish_defaults(struct dvb_frontend *fe)
1047 {
1048     struct tda10048_state *state = fe->demodulator_priv;
1049     struct tda10048_config *config = &state->config;
1050 
1051     /* Validate/default the config */
1052     if (config->dtv6_if_freq_khz == 0) {
1053         config->dtv6_if_freq_khz = TDA10048_IF_4300;
1054         printk(KERN_WARNING "%s() tda10048_config.dtv6_if_freq_khz is not set (defaulting to %d)\n",
1055             __func__,
1056             config->dtv6_if_freq_khz);
1057     }
1058 
1059     if (config->dtv7_if_freq_khz == 0) {
1060         config->dtv7_if_freq_khz = TDA10048_IF_4300;
1061         printk(KERN_WARNING "%s() tda10048_config.dtv7_if_freq_khz is not set (defaulting to %d)\n",
1062             __func__,
1063             config->dtv7_if_freq_khz);
1064     }
1065 
1066     if (config->dtv8_if_freq_khz == 0) {
1067         config->dtv8_if_freq_khz = TDA10048_IF_4300;
1068         printk(KERN_WARNING "%s() tda10048_config.dtv8_if_freq_khz is not set (defaulting to %d)\n",
1069             __func__,
1070             config->dtv8_if_freq_khz);
1071     }
1072 
1073     if (config->clk_freq_khz == 0) {
1074         config->clk_freq_khz = TDA10048_CLK_16000;
1075         printk(KERN_WARNING "%s() tda10048_config.clk_freq_khz is not set (defaulting to %d)\n",
1076             __func__,
1077             config->clk_freq_khz);
1078     }
1079 }
1080 
1081 static const struct dvb_frontend_ops tda10048_ops;
1082 
1083 struct dvb_frontend *tda10048_attach(const struct tda10048_config *config,
1084     struct i2c_adapter *i2c)
1085 {
1086     struct tda10048_state *state = NULL;
1087 
1088     dprintk(1, "%s()\n", __func__);
1089 
1090     /* allocate memory for the internal state */
1091     state = kzalloc(sizeof(struct tda10048_state), GFP_KERNEL);
1092     if (state == NULL)
1093         goto error;
1094 
1095     /* setup the state and clone the config */
1096     memcpy(&state->config, config, sizeof(*config));
1097     state->i2c = i2c;
1098     state->fwloaded = config->no_firmware;
1099     state->bandwidth = 8000000;
1100 
1101     /* check if the demod is present */
1102     if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048)
1103         goto error;
1104 
1105     /* create dvb_frontend */
1106     memcpy(&state->frontend.ops, &tda10048_ops,
1107         sizeof(struct dvb_frontend_ops));
1108     state->frontend.demodulator_priv = state;
1109 
1110     /* set pll */
1111     if (config->set_pll) {
1112         state->pll_mfactor = config->pll_m;
1113         state->pll_nfactor = config->pll_n;
1114         state->pll_pfactor = config->pll_p;
1115     } else {
1116         state->pll_mfactor = 10;
1117         state->pll_nfactor = 3;
1118         state->pll_pfactor = 0;
1119     }
1120 
1121     /* Establish any defaults the the user didn't pass */
1122     tda10048_establish_defaults(&state->frontend);
1123 
1124     /* Set the xtal and freq defaults */
1125     if (tda10048_set_if(&state->frontend, 8000000) != 0)
1126         goto error;
1127 
1128     /* Default bandwidth */
1129     if (tda10048_set_bandwidth(&state->frontend, 8000000) != 0)
1130         goto error;
1131 
1132     /* Leave the gate closed */
1133     tda10048_i2c_gate_ctrl(&state->frontend, 0);
1134 
1135     return &state->frontend;
1136 
1137 error:
1138     kfree(state);
1139     return NULL;
1140 }
1141 EXPORT_SYMBOL(tda10048_attach);
1142 
1143 static const struct dvb_frontend_ops tda10048_ops = {
1144     .delsys = { SYS_DVBT },
1145     .info = {
1146         .name           = "NXP TDA10048HN DVB-T",
1147         .frequency_min_hz   = 177 * MHz,
1148         .frequency_max_hz   = 858 * MHz,
1149         .frequency_stepsize_hz  = 166666,
1150         .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1151         FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1152         FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1153         FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
1154         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
1155     },
1156 
1157     .release = tda10048_release,
1158     .init = tda10048_init,
1159     .i2c_gate_ctrl = tda10048_i2c_gate_ctrl,
1160     .set_frontend = tda10048_set_frontend,
1161     .get_frontend = tda10048_get_frontend,
1162     .get_tune_settings = tda10048_get_tune_settings,
1163     .read_status = tda10048_read_status,
1164     .read_ber = tda10048_read_ber,
1165     .read_signal_strength = tda10048_read_signal_strength,
1166     .read_snr = tda10048_read_snr,
1167     .read_ucblocks = tda10048_read_ucblocks,
1168 };
1169 
1170 module_param(debug, int, 0644);
1171 MODULE_PARM_DESC(debug, "Enable verbose debug messages");
1172 
1173 MODULE_DESCRIPTION("NXP TDA10048HN DVB-T Demodulator driver");
1174 MODULE_AUTHOR("Steven Toth");
1175 MODULE_LICENSE("GPL");
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