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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Toshiba TC90522 Demodulator
0004  *
0005  * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
0006  */
0007 
0008 /*
0009  * NOTICE:
0010  * This driver is incomplete and lacks init/config of the chips,
0011  * as the necessary info is not disclosed.
0012  * It assumes that users of this driver (such as a PCI bridge of
0013  * DTV receiver cards) properly init and configure the chip
0014  * via I2C *before* calling this driver's init() function.
0015  *
0016  * Currently, PT3 driver is the only one that uses this driver,
0017  * and contains init/config code in its firmware.
0018  * Thus some part of the code might be dependent on PT3 specific config.
0019  */
0020 
0021 #include <linux/kernel.h>
0022 #include <linux/math64.h>
0023 #include <linux/dvb/frontend.h>
0024 #include <media/dvb_math.h>
0025 #include "tc90522.h"
0026 
0027 #define TC90522_I2C_THRU_REG 0xfe
0028 
0029 #define TC90522_MODULE_IDX(addr) (((u8)(addr) & 0x02U) >> 1)
0030 
0031 struct tc90522_state {
0032     struct tc90522_config cfg;
0033     struct dvb_frontend fe;
0034     struct i2c_client *i2c_client;
0035     struct i2c_adapter tuner_i2c;
0036 
0037     bool lna;
0038 };
0039 
0040 struct reg_val {
0041     u8 reg;
0042     u8 val;
0043 };
0044 
0045 static int
0046 reg_write(struct tc90522_state *state, const struct reg_val *regs, int num)
0047 {
0048     int i, ret;
0049     struct i2c_msg msg;
0050 
0051     ret = 0;
0052     msg.addr = state->i2c_client->addr;
0053     msg.flags = 0;
0054     msg.len = 2;
0055     for (i = 0; i < num; i++) {
0056         msg.buf = (u8 *)&regs[i];
0057         ret = i2c_transfer(state->i2c_client->adapter, &msg, 1);
0058         if (ret == 0)
0059             ret = -EIO;
0060         if (ret < 0)
0061             return ret;
0062     }
0063     return 0;
0064 }
0065 
0066 static int reg_read(struct tc90522_state *state, u8 reg, u8 *val, u8 len)
0067 {
0068     struct i2c_msg msgs[2] = {
0069         {
0070             .addr = state->i2c_client->addr,
0071             .flags = 0,
0072             .buf = &reg,
0073             .len = 1,
0074         },
0075         {
0076             .addr = state->i2c_client->addr,
0077             .flags = I2C_M_RD,
0078             .buf = val,
0079             .len = len,
0080         },
0081     };
0082     int ret;
0083 
0084     ret = i2c_transfer(state->i2c_client->adapter, msgs, ARRAY_SIZE(msgs));
0085     if (ret == ARRAY_SIZE(msgs))
0086         ret = 0;
0087     else if (ret >= 0)
0088         ret = -EIO;
0089     return ret;
0090 }
0091 
0092 static struct tc90522_state *cfg_to_state(struct tc90522_config *c)
0093 {
0094     return container_of(c, struct tc90522_state, cfg);
0095 }
0096 
0097 
0098 static int tc90522s_set_tsid(struct dvb_frontend *fe)
0099 {
0100     struct reg_val set_tsid[] = {
0101         { 0x8f, 00 },
0102         { 0x90, 00 }
0103     };
0104 
0105     set_tsid[0].val = (fe->dtv_property_cache.stream_id & 0xff00) >> 8;
0106     set_tsid[1].val = fe->dtv_property_cache.stream_id & 0xff;
0107     return reg_write(fe->demodulator_priv, set_tsid, ARRAY_SIZE(set_tsid));
0108 }
0109 
0110 static int tc90522t_set_layers(struct dvb_frontend *fe)
0111 {
0112     struct reg_val rv;
0113     u8 laysel;
0114 
0115     laysel = ~fe->dtv_property_cache.isdbt_layer_enabled & 0x07;
0116     laysel = (laysel & 0x01) << 2 | (laysel & 0x02) | (laysel & 0x04) >> 2;
0117     rv.reg = 0x71;
0118     rv.val = laysel;
0119     return reg_write(fe->demodulator_priv, &rv, 1);
0120 }
0121 
0122 /* frontend ops */
0123 
0124 static int tc90522s_read_status(struct dvb_frontend *fe, enum fe_status *status)
0125 {
0126     struct tc90522_state *state;
0127     int ret;
0128     u8 reg;
0129 
0130     state = fe->demodulator_priv;
0131     ret = reg_read(state, 0xc3, &reg, 1);
0132     if (ret < 0)
0133         return ret;
0134 
0135     *status = 0;
0136     if (reg & 0x80) /* input level under min ? */
0137         return 0;
0138     *status |= FE_HAS_SIGNAL;
0139 
0140     if (reg & 0x60) /* carrier? */
0141         return 0;
0142     *status |= FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
0143 
0144     if (reg & 0x10)
0145         return 0;
0146     if (reg_read(state, 0xc5, &reg, 1) < 0 || !(reg & 0x03))
0147         return 0;
0148     *status |= FE_HAS_LOCK;
0149     return 0;
0150 }
0151 
0152 static int tc90522t_read_status(struct dvb_frontend *fe, enum fe_status *status)
0153 {
0154     struct tc90522_state *state;
0155     int ret;
0156     u8 reg;
0157 
0158     state = fe->demodulator_priv;
0159     ret = reg_read(state, 0x96, &reg, 1);
0160     if (ret < 0)
0161         return ret;
0162 
0163     *status = 0;
0164     if (reg & 0xe0) {
0165         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
0166                 | FE_HAS_SYNC | FE_HAS_LOCK;
0167         return 0;
0168     }
0169 
0170     ret = reg_read(state, 0x80, &reg, 1);
0171     if (ret < 0)
0172         return ret;
0173 
0174     if (reg & 0xf0)
0175         return 0;
0176     *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
0177 
0178     if (reg & 0x0c)
0179         return 0;
0180     *status |= FE_HAS_SYNC | FE_HAS_VITERBI;
0181 
0182     if (reg & 0x02)
0183         return 0;
0184     *status |= FE_HAS_LOCK;
0185     return 0;
0186 }
0187 
0188 static const enum fe_code_rate fec_conv_sat[] = {
0189     FEC_NONE, /* unused */
0190     FEC_1_2, /* for BPSK */
0191     FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, /* for QPSK */
0192     FEC_2_3, /* for 8PSK. (trellis code) */
0193 };
0194 
0195 static int tc90522s_get_frontend(struct dvb_frontend *fe,
0196                  struct dtv_frontend_properties *c)
0197 {
0198     struct tc90522_state *state;
0199     struct dtv_fe_stats *stats;
0200     int ret, i;
0201     int layers;
0202     u8 val[10];
0203     u32 cndat;
0204 
0205     state = fe->demodulator_priv;
0206     c->delivery_system = SYS_ISDBS;
0207     c->symbol_rate = 28860000;
0208 
0209     layers = 0;
0210     ret = reg_read(state, 0xe6, val, 5);
0211     if (ret == 0) {
0212         u8 v;
0213 
0214         c->stream_id = val[0] << 8 | val[1];
0215 
0216         /* high/single layer */
0217         v = (val[2] & 0x70) >> 4;
0218         c->modulation = (v == 7) ? PSK_8 : QPSK;
0219         c->fec_inner = fec_conv_sat[v];
0220         c->layer[0].fec = c->fec_inner;
0221         c->layer[0].modulation = c->modulation;
0222         c->layer[0].segment_count = val[3] & 0x3f; /* slots */
0223 
0224         /* low layer */
0225         v = (val[2] & 0x07);
0226         c->layer[1].fec = fec_conv_sat[v];
0227         if (v == 0)  /* no low layer */
0228             c->layer[1].segment_count = 0;
0229         else
0230             c->layer[1].segment_count = val[4] & 0x3f; /* slots */
0231         /*
0232          * actually, BPSK if v==1, but not defined in
0233          * enum fe_modulation
0234          */
0235         c->layer[1].modulation = QPSK;
0236         layers = (v > 0) ? 2 : 1;
0237     }
0238 
0239     /* statistics */
0240 
0241     stats = &c->strength;
0242     stats->len = 0;
0243     /* let the connected tuner set RSSI property cache */
0244     if (fe->ops.tuner_ops.get_rf_strength) {
0245         u16 dummy;
0246 
0247         fe->ops.tuner_ops.get_rf_strength(fe, &dummy);
0248     }
0249 
0250     stats = &c->cnr;
0251     stats->len = 1;
0252     stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0253     cndat = 0;
0254     ret = reg_read(state, 0xbc, val, 2);
0255     if (ret == 0)
0256         cndat = val[0] << 8 | val[1];
0257     if (cndat >= 3000) {
0258         u32 p, p4;
0259         s64 cn;
0260 
0261         cndat -= 3000;  /* cndat: 4.12 fixed point float */
0262         /*
0263          * cnr[mdB] = -1634.6 * P^5 + 14341 * P^4 - 50259 * P^3
0264          *                 + 88977 * P^2 - 89565 * P + 58857
0265          *  (P = sqrt(cndat) / 64)
0266          */
0267         /* p := sqrt(cndat) << 8 = P << 14, 2.14 fixed  point float */
0268         /* cn = cnr << 3 */
0269         p = int_sqrt(cndat << 16);
0270         p4 = cndat * cndat;
0271         cn = div64_s64(-16346LL * p4 * p, 10) >> 35;
0272         cn += (14341LL * p4) >> 21;
0273         cn -= (50259LL * cndat * p) >> 23;
0274         cn += (88977LL * cndat) >> 9;
0275         cn -= (89565LL * p) >> 11;
0276         cn += 58857  << 3;
0277         stats->stat[0].svalue = cn >> 3;
0278         stats->stat[0].scale = FE_SCALE_DECIBEL;
0279     }
0280 
0281     /* per-layer post viterbi BER (or PER? config dependent?) */
0282     stats = &c->post_bit_error;
0283     memset(stats, 0, sizeof(*stats));
0284     stats->len = layers;
0285     ret = reg_read(state, 0xeb, val, 10);
0286     if (ret < 0)
0287         for (i = 0; i < layers; i++)
0288             stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
0289     else {
0290         for (i = 0; i < layers; i++) {
0291             stats->stat[i].scale = FE_SCALE_COUNTER;
0292             stats->stat[i].uvalue = val[i * 5] << 16
0293                 | val[i * 5 + 1] << 8 | val[i * 5 + 2];
0294         }
0295     }
0296     stats = &c->post_bit_count;
0297     memset(stats, 0, sizeof(*stats));
0298     stats->len = layers;
0299     if (ret < 0)
0300         for (i = 0; i < layers; i++)
0301             stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
0302     else {
0303         for (i = 0; i < layers; i++) {
0304             stats->stat[i].scale = FE_SCALE_COUNTER;
0305             stats->stat[i].uvalue =
0306                 val[i * 5 + 3] << 8 | val[i * 5 + 4];
0307             stats->stat[i].uvalue *= 204 * 8;
0308         }
0309     }
0310 
0311     return 0;
0312 }
0313 
0314 
0315 static const enum fe_transmit_mode tm_conv[] = {
0316     TRANSMISSION_MODE_2K,
0317     TRANSMISSION_MODE_4K,
0318     TRANSMISSION_MODE_8K,
0319     0
0320 };
0321 
0322 static const enum fe_code_rate fec_conv_ter[] = {
0323     FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, 0, 0, 0
0324 };
0325 
0326 static const enum fe_modulation mod_conv[] = {
0327     DQPSK, QPSK, QAM_16, QAM_64, 0, 0, 0, 0
0328 };
0329 
0330 static int tc90522t_get_frontend(struct dvb_frontend *fe,
0331                  struct dtv_frontend_properties *c)
0332 {
0333     struct tc90522_state *state;
0334     struct dtv_fe_stats *stats;
0335     int ret, i;
0336     int layers;
0337     u8 val[15], mode;
0338     u32 cndat;
0339 
0340     state = fe->demodulator_priv;
0341     c->delivery_system = SYS_ISDBT;
0342     c->bandwidth_hz = 6000000;
0343     mode = 1;
0344     ret = reg_read(state, 0xb0, val, 1);
0345     if (ret == 0) {
0346         mode = (val[0] & 0xc0) >> 6;
0347         c->transmission_mode = tm_conv[mode];
0348         c->guard_interval = (val[0] & 0x30) >> 4;
0349     }
0350 
0351     ret = reg_read(state, 0xb2, val, 6);
0352     layers = 0;
0353     if (ret == 0) {
0354         u8 v;
0355 
0356         c->isdbt_partial_reception = val[0] & 0x01;
0357         c->isdbt_sb_mode = (val[0] & 0xc0) == 0x40;
0358 
0359         /* layer A */
0360         v = (val[2] & 0x78) >> 3;
0361         if (v == 0x0f)
0362             c->layer[0].segment_count = 0;
0363         else {
0364             layers++;
0365             c->layer[0].segment_count = v;
0366             c->layer[0].fec = fec_conv_ter[(val[1] & 0x1c) >> 2];
0367             c->layer[0].modulation = mod_conv[(val[1] & 0xe0) >> 5];
0368             v = (val[1] & 0x03) << 1 | (val[2] & 0x80) >> 7;
0369             c->layer[0].interleaving = v;
0370         }
0371 
0372         /* layer B */
0373         v = (val[3] & 0x03) << 2 | (val[4] & 0xc0) >> 6;
0374         if (v == 0x0f)
0375             c->layer[1].segment_count = 0;
0376         else {
0377             layers++;
0378             c->layer[1].segment_count = v;
0379             c->layer[1].fec = fec_conv_ter[(val[3] & 0xe0) >> 5];
0380             c->layer[1].modulation = mod_conv[(val[2] & 0x07)];
0381             c->layer[1].interleaving = (val[3] & 0x1c) >> 2;
0382         }
0383 
0384         /* layer C */
0385         v = (val[5] & 0x1e) >> 1;
0386         if (v == 0x0f)
0387             c->layer[2].segment_count = 0;
0388         else {
0389             layers++;
0390             c->layer[2].segment_count = v;
0391             c->layer[2].fec = fec_conv_ter[(val[4] & 0x07)];
0392             c->layer[2].modulation = mod_conv[(val[4] & 0x38) >> 3];
0393             c->layer[2].interleaving = (val[5] & 0xe0) >> 5;
0394         }
0395     }
0396 
0397     /* statistics */
0398 
0399     stats = &c->strength;
0400     stats->len = 0;
0401     /* let the connected tuner set RSSI property cache */
0402     if (fe->ops.tuner_ops.get_rf_strength) {
0403         u16 dummy;
0404 
0405         fe->ops.tuner_ops.get_rf_strength(fe, &dummy);
0406     }
0407 
0408     stats = &c->cnr;
0409     stats->len = 1;
0410     stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0411     cndat = 0;
0412     ret = reg_read(state, 0x8b, val, 3);
0413     if (ret == 0)
0414         cndat = val[0] << 16 | val[1] << 8 | val[2];
0415     if (cndat != 0) {
0416         u32 p, tmp;
0417         s64 cn;
0418 
0419         /*
0420          * cnr[mdB] = 0.024 P^4 - 1.6 P^3 + 39.8 P^2 + 549.1 P + 3096.5
0421          * (P = 10log10(5505024/cndat))
0422          */
0423         /* cn = cnr << 3 (61.3 fixed point float */
0424         /* p = 10log10(5505024/cndat) << 24  (8.24 fixed point float)*/
0425         p = intlog10(5505024) - intlog10(cndat);
0426         p *= 10;
0427 
0428         cn = 24772;
0429         cn += div64_s64(43827LL * p, 10) >> 24;
0430         tmp = p >> 8;
0431         cn += div64_s64(3184LL * tmp * tmp, 10) >> 32;
0432         tmp = p >> 13;
0433         cn -= div64_s64(128LL * tmp * tmp * tmp, 10) >> 33;
0434         tmp = p >> 18;
0435         cn += div64_s64(192LL * tmp * tmp * tmp * tmp, 1000) >> 24;
0436 
0437         stats->stat[0].svalue = cn >> 3;
0438         stats->stat[0].scale = FE_SCALE_DECIBEL;
0439     }
0440 
0441     /* per-layer post viterbi BER (or PER? config dependent?) */
0442     stats = &c->post_bit_error;
0443     memset(stats, 0, sizeof(*stats));
0444     stats->len = layers;
0445     ret = reg_read(state, 0x9d, val, 15);
0446     if (ret < 0)
0447         for (i = 0; i < layers; i++)
0448             stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
0449     else {
0450         for (i = 0; i < layers; i++) {
0451             stats->stat[i].scale = FE_SCALE_COUNTER;
0452             stats->stat[i].uvalue = val[i * 3] << 16
0453                 | val[i * 3 + 1] << 8 | val[i * 3 + 2];
0454         }
0455     }
0456     stats = &c->post_bit_count;
0457     memset(stats, 0, sizeof(*stats));
0458     stats->len = layers;
0459     if (ret < 0)
0460         for (i = 0; i < layers; i++)
0461             stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
0462     else {
0463         for (i = 0; i < layers; i++) {
0464             stats->stat[i].scale = FE_SCALE_COUNTER;
0465             stats->stat[i].uvalue =
0466                 val[9 + i * 2] << 8 | val[9 + i * 2 + 1];
0467             stats->stat[i].uvalue *= 204 * 8;
0468         }
0469     }
0470 
0471     return 0;
0472 }
0473 
0474 static const struct reg_val reset_sat = { 0x03, 0x01 };
0475 static const struct reg_val reset_ter = { 0x01, 0x40 };
0476 
0477 static int tc90522_set_frontend(struct dvb_frontend *fe)
0478 {
0479     struct tc90522_state *state;
0480     int ret;
0481 
0482     state = fe->demodulator_priv;
0483 
0484     if (fe->ops.tuner_ops.set_params)
0485         ret = fe->ops.tuner_ops.set_params(fe);
0486     else
0487         ret = -ENODEV;
0488     if (ret < 0)
0489         goto failed;
0490 
0491     if (fe->ops.delsys[0] == SYS_ISDBS) {
0492         ret = tc90522s_set_tsid(fe);
0493         if (ret < 0)
0494             goto failed;
0495         ret = reg_write(state, &reset_sat, 1);
0496     } else {
0497         ret = tc90522t_set_layers(fe);
0498         if (ret < 0)
0499             goto failed;
0500         ret = reg_write(state, &reset_ter, 1);
0501     }
0502     if (ret < 0)
0503         goto failed;
0504 
0505     return 0;
0506 
0507 failed:
0508     dev_warn(&state->tuner_i2c.dev, "(%s) failed. [adap%d-fe%d]\n",
0509             __func__, fe->dvb->num, fe->id);
0510     return ret;
0511 }
0512 
0513 static int tc90522_get_tune_settings(struct dvb_frontend *fe,
0514     struct dvb_frontend_tune_settings *settings)
0515 {
0516     if (fe->ops.delsys[0] == SYS_ISDBS) {
0517         settings->min_delay_ms = 250;
0518         settings->step_size = 1000;
0519         settings->max_drift = settings->step_size * 2;
0520     } else {
0521         settings->min_delay_ms = 400;
0522         settings->step_size = 142857;
0523         settings->max_drift = settings->step_size;
0524     }
0525     return 0;
0526 }
0527 
0528 static int tc90522_set_if_agc(struct dvb_frontend *fe, bool on)
0529 {
0530     struct reg_val agc_sat[] = {
0531         { 0x0a, 0x00 },
0532         { 0x10, 0x30 },
0533         { 0x11, 0x00 },
0534         { 0x03, 0x01 },
0535     };
0536     struct reg_val agc_ter[] = {
0537         { 0x25, 0x00 },
0538         { 0x23, 0x4c },
0539         { 0x01, 0x40 },
0540     };
0541     struct tc90522_state *state;
0542     struct reg_val *rv;
0543     int num;
0544 
0545     state = fe->demodulator_priv;
0546     if (fe->ops.delsys[0] == SYS_ISDBS) {
0547         agc_sat[0].val = on ? 0xff : 0x00;
0548         agc_sat[1].val |= 0x80;
0549         agc_sat[1].val |= on ? 0x01 : 0x00;
0550         agc_sat[2].val |= on ? 0x40 : 0x00;
0551         rv = agc_sat;
0552         num = ARRAY_SIZE(agc_sat);
0553     } else {
0554         agc_ter[0].val = on ? 0x40 : 0x00;
0555         agc_ter[1].val |= on ? 0x00 : 0x01;
0556         rv = agc_ter;
0557         num = ARRAY_SIZE(agc_ter);
0558     }
0559     return reg_write(state, rv, num);
0560 }
0561 
0562 static const struct reg_val sleep_sat = { 0x17, 0x01 };
0563 static const struct reg_val sleep_ter = { 0x03, 0x90 };
0564 
0565 static int tc90522_sleep(struct dvb_frontend *fe)
0566 {
0567     struct tc90522_state *state;
0568     int ret;
0569 
0570     state = fe->demodulator_priv;
0571     if (fe->ops.delsys[0] == SYS_ISDBS)
0572         ret = reg_write(state, &sleep_sat, 1);
0573     else {
0574         ret = reg_write(state, &sleep_ter, 1);
0575         if (ret == 0 && fe->ops.set_lna &&
0576             fe->dtv_property_cache.lna == LNA_AUTO) {
0577             fe->dtv_property_cache.lna = 0;
0578             ret = fe->ops.set_lna(fe);
0579             fe->dtv_property_cache.lna = LNA_AUTO;
0580         }
0581     }
0582     if (ret < 0)
0583         dev_warn(&state->tuner_i2c.dev,
0584             "(%s) failed. [adap%d-fe%d]\n",
0585             __func__, fe->dvb->num, fe->id);
0586     return ret;
0587 }
0588 
0589 static const struct reg_val wakeup_sat = { 0x17, 0x00 };
0590 static const struct reg_val wakeup_ter = { 0x03, 0x80 };
0591 
0592 static int tc90522_init(struct dvb_frontend *fe)
0593 {
0594     struct tc90522_state *state;
0595     int ret;
0596 
0597     /*
0598      * Because the init sequence is not public,
0599      * the parent device/driver should have init'ed the device before.
0600      * just wake up the device here.
0601      */
0602 
0603     state = fe->demodulator_priv;
0604     if (fe->ops.delsys[0] == SYS_ISDBS)
0605         ret = reg_write(state, &wakeup_sat, 1);
0606     else {
0607         ret = reg_write(state, &wakeup_ter, 1);
0608         if (ret == 0 && fe->ops.set_lna &&
0609             fe->dtv_property_cache.lna == LNA_AUTO) {
0610             fe->dtv_property_cache.lna = 1;
0611             ret = fe->ops.set_lna(fe);
0612             fe->dtv_property_cache.lna = LNA_AUTO;
0613         }
0614     }
0615     if (ret < 0) {
0616         dev_warn(&state->tuner_i2c.dev,
0617             "(%s) failed. [adap%d-fe%d]\n",
0618             __func__, fe->dvb->num, fe->id);
0619         return ret;
0620     }
0621 
0622     /* prefer 'all-layers' to 'none' as a default */
0623     if (fe->dtv_property_cache.isdbt_layer_enabled == 0)
0624         fe->dtv_property_cache.isdbt_layer_enabled = 7;
0625     return tc90522_set_if_agc(fe, true);
0626 }
0627 
0628 
0629 /*
0630  * tuner I2C adapter functions
0631  */
0632 
0633 static int
0634 tc90522_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
0635 {
0636     struct tc90522_state *state;
0637     struct i2c_msg *new_msgs;
0638     int i, j;
0639     int ret, rd_num;
0640     u8 wbuf[256];
0641     u8 *p, *bufend;
0642 
0643     if (num <= 0)
0644         return -EINVAL;
0645 
0646     rd_num = 0;
0647     for (i = 0; i < num; i++)
0648         if (msgs[i].flags & I2C_M_RD)
0649             rd_num++;
0650     new_msgs = kmalloc_array(num + rd_num, sizeof(*new_msgs), GFP_KERNEL);
0651     if (!new_msgs)
0652         return -ENOMEM;
0653 
0654     state = i2c_get_adapdata(adap);
0655     p = wbuf;
0656     bufend = wbuf + sizeof(wbuf);
0657     for (i = 0, j = 0; i < num; i++, j++) {
0658         new_msgs[j].addr = state->i2c_client->addr;
0659         new_msgs[j].flags = msgs[i].flags;
0660 
0661         if (msgs[i].flags & I2C_M_RD) {
0662             new_msgs[j].flags &= ~I2C_M_RD;
0663             if (p + 2 > bufend)
0664                 break;
0665             p[0] = TC90522_I2C_THRU_REG;
0666             p[1] = msgs[i].addr << 1 | 0x01;
0667             new_msgs[j].buf = p;
0668             new_msgs[j].len = 2;
0669             p += 2;
0670             j++;
0671             new_msgs[j].addr = state->i2c_client->addr;
0672             new_msgs[j].flags = msgs[i].flags;
0673             new_msgs[j].buf = msgs[i].buf;
0674             new_msgs[j].len = msgs[i].len;
0675             continue;
0676         }
0677 
0678         if (p + msgs[i].len + 2 > bufend)
0679             break;
0680         p[0] = TC90522_I2C_THRU_REG;
0681         p[1] = msgs[i].addr << 1;
0682         memcpy(p + 2, msgs[i].buf, msgs[i].len);
0683         new_msgs[j].buf = p;
0684         new_msgs[j].len = msgs[i].len + 2;
0685         p += new_msgs[j].len;
0686     }
0687 
0688     if (i < num) {
0689         ret = -ENOMEM;
0690     } else if (!state->cfg.split_tuner_read_i2c || rd_num == 0) {
0691         ret = i2c_transfer(state->i2c_client->adapter, new_msgs, j);
0692     } else {
0693         /*
0694          * Split transactions at each I2C_M_RD message.
0695          * Some of the parent device require this,
0696          * such as Friio (see. dvb-usb-gl861).
0697          */
0698         int from, to;
0699 
0700         ret = 0;
0701         from = 0;
0702         do {
0703             int r;
0704 
0705             to = from + 1;
0706             while (to < j && !(new_msgs[to].flags & I2C_M_RD))
0707                 to++;
0708             r = i2c_transfer(state->i2c_client->adapter,
0709                      &new_msgs[from], to - from);
0710             ret = (r <= 0) ? r : ret + r;
0711             from = to;
0712         } while (from < j && ret > 0);
0713     }
0714 
0715     if (ret >= 0 && ret < j)
0716         ret = -EIO;
0717     kfree(new_msgs);
0718     return (ret == j) ? num : ret;
0719 }
0720 
0721 static u32 tc90522_functionality(struct i2c_adapter *adap)
0722 {
0723     return I2C_FUNC_I2C;
0724 }
0725 
0726 static const struct i2c_algorithm tc90522_tuner_i2c_algo = {
0727     .master_xfer   = &tc90522_master_xfer,
0728     .functionality = &tc90522_functionality,
0729 };
0730 
0731 
0732 /*
0733  * I2C driver functions
0734  */
0735 
0736 static const struct dvb_frontend_ops tc90522_ops_sat = {
0737     .delsys = { SYS_ISDBS },
0738     .info = {
0739         .name = "Toshiba TC90522 ISDB-S module",
0740         .frequency_min_hz =  950 * MHz,
0741         .frequency_max_hz = 2150 * MHz,
0742         .caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO |
0743             FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
0744             FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
0745     },
0746 
0747     .init = tc90522_init,
0748     .sleep = tc90522_sleep,
0749     .set_frontend = tc90522_set_frontend,
0750     .get_tune_settings = tc90522_get_tune_settings,
0751 
0752     .get_frontend = tc90522s_get_frontend,
0753     .read_status = tc90522s_read_status,
0754 };
0755 
0756 static const struct dvb_frontend_ops tc90522_ops_ter = {
0757     .delsys = { SYS_ISDBT },
0758     .info = {
0759         .name = "Toshiba TC90522 ISDB-T module",
0760         .frequency_min_hz = 470 * MHz,
0761         .frequency_max_hz = 770 * MHz,
0762         .frequency_stepsize_hz = 142857,
0763         .caps = FE_CAN_INVERSION_AUTO |
0764             FE_CAN_FEC_1_2  | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
0765             FE_CAN_FEC_5_6  | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
0766             FE_CAN_QPSK     | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
0767             FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
0768             FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
0769             FE_CAN_HIERARCHY_AUTO,
0770     },
0771 
0772     .init = tc90522_init,
0773     .sleep = tc90522_sleep,
0774     .set_frontend = tc90522_set_frontend,
0775     .get_tune_settings = tc90522_get_tune_settings,
0776 
0777     .get_frontend = tc90522t_get_frontend,
0778     .read_status = tc90522t_read_status,
0779 };
0780 
0781 
0782 static int tc90522_probe(struct i2c_client *client,
0783              const struct i2c_device_id *id)
0784 {
0785     struct tc90522_state *state;
0786     struct tc90522_config *cfg;
0787     const struct dvb_frontend_ops *ops;
0788     struct i2c_adapter *adap;
0789     int ret;
0790 
0791     state = kzalloc(sizeof(*state), GFP_KERNEL);
0792     if (!state)
0793         return -ENOMEM;
0794     state->i2c_client = client;
0795 
0796     cfg = client->dev.platform_data;
0797     memcpy(&state->cfg, cfg, sizeof(state->cfg));
0798     cfg->fe = state->cfg.fe = &state->fe;
0799     ops =  id->driver_data == 0 ? &tc90522_ops_sat : &tc90522_ops_ter;
0800     memcpy(&state->fe.ops, ops, sizeof(*ops));
0801     state->fe.demodulator_priv = state;
0802 
0803     adap = &state->tuner_i2c;
0804     adap->owner = THIS_MODULE;
0805     adap->algo = &tc90522_tuner_i2c_algo;
0806     adap->dev.parent = &client->dev;
0807     strscpy(adap->name, "tc90522_sub", sizeof(adap->name));
0808     i2c_set_adapdata(adap, state);
0809     ret = i2c_add_adapter(adap);
0810     if (ret < 0)
0811         goto free_state;
0812     cfg->tuner_i2c = state->cfg.tuner_i2c = adap;
0813 
0814     i2c_set_clientdata(client, &state->cfg);
0815     dev_info(&client->dev, "Toshiba TC90522 attached.\n");
0816     return 0;
0817 free_state:
0818     kfree(state);
0819     return ret;
0820 }
0821 
0822 static int tc90522_remove(struct i2c_client *client)
0823 {
0824     struct tc90522_state *state;
0825 
0826     state = cfg_to_state(i2c_get_clientdata(client));
0827     i2c_del_adapter(&state->tuner_i2c);
0828     kfree(state);
0829     return 0;
0830 }
0831 
0832 
0833 static const struct i2c_device_id tc90522_id[] = {
0834     { TC90522_I2C_DEV_SAT, 0 },
0835     { TC90522_I2C_DEV_TER, 1 },
0836     {}
0837 };
0838 MODULE_DEVICE_TABLE(i2c, tc90522_id);
0839 
0840 static struct i2c_driver tc90522_driver = {
0841     .driver = {
0842         .name   = "tc90522",
0843     },
0844     .probe      = tc90522_probe,
0845     .remove     = tc90522_remove,
0846     .id_table   = tc90522_id,
0847 };
0848 
0849 module_i2c_driver(tc90522_driver);
0850 
0851 MODULE_DESCRIPTION("Toshiba TC90522 frontend");
0852 MODULE_AUTHOR("Akihiro TSUKADA");
0853 MODULE_LICENSE("GPL");
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