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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for the ST STV0910 DVB-S/S2 demodulator.
0004  *
0005  * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
0006  *                         Marcus Metzler <mocm@metzlerbros.de>
0007  *                         developed for Digital Devices GmbH
0008  */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/moduleparam.h>
0013 #include <linux/init.h>
0014 #include <linux/delay.h>
0015 #include <linux/firmware.h>
0016 #include <linux/i2c.h>
0017 #include <asm/div64.h>
0018 
0019 #include <media/dvb_frontend.h>
0020 #include "stv0910.h"
0021 #include "stv0910_regs.h"
0022 
0023 #define EXT_CLOCK    30000000
0024 #define TUNING_DELAY 200
0025 #define BER_SRC_S    0x20
0026 #define BER_SRC_S2   0x20
0027 
0028 static LIST_HEAD(stvlist);
0029 
0030 enum receive_mode { RCVMODE_NONE, RCVMODE_DVBS, RCVMODE_DVBS2, RCVMODE_AUTO };
0031 
0032 enum dvbs2_fectype { DVBS2_64K, DVBS2_16K };
0033 
0034 enum dvbs2_mod_cod {
0035     DVBS2_DUMMY_PLF, DVBS2_QPSK_1_4, DVBS2_QPSK_1_3, DVBS2_QPSK_2_5,
0036     DVBS2_QPSK_1_2, DVBS2_QPSK_3_5, DVBS2_QPSK_2_3, DVBS2_QPSK_3_4,
0037     DVBS2_QPSK_4_5, DVBS2_QPSK_5_6, DVBS2_QPSK_8_9, DVBS2_QPSK_9_10,
0038     DVBS2_8PSK_3_5, DVBS2_8PSK_2_3, DVBS2_8PSK_3_4, DVBS2_8PSK_5_6,
0039     DVBS2_8PSK_8_9, DVBS2_8PSK_9_10, DVBS2_16APSK_2_3, DVBS2_16APSK_3_4,
0040     DVBS2_16APSK_4_5, DVBS2_16APSK_5_6, DVBS2_16APSK_8_9, DVBS2_16APSK_9_10,
0041     DVBS2_32APSK_3_4, DVBS2_32APSK_4_5, DVBS2_32APSK_5_6, DVBS2_32APSK_8_9,
0042     DVBS2_32APSK_9_10
0043 };
0044 
0045 enum fe_stv0910_mod_cod {
0046     FE_DUMMY_PLF, FE_QPSK_14, FE_QPSK_13, FE_QPSK_25,
0047     FE_QPSK_12, FE_QPSK_35, FE_QPSK_23, FE_QPSK_34,
0048     FE_QPSK_45, FE_QPSK_56, FE_QPSK_89, FE_QPSK_910,
0049     FE_8PSK_35, FE_8PSK_23, FE_8PSK_34, FE_8PSK_56,
0050     FE_8PSK_89, FE_8PSK_910, FE_16APSK_23, FE_16APSK_34,
0051     FE_16APSK_45, FE_16APSK_56, FE_16APSK_89, FE_16APSK_910,
0052     FE_32APSK_34, FE_32APSK_45, FE_32APSK_56, FE_32APSK_89,
0053     FE_32APSK_910
0054 };
0055 
0056 enum fe_stv0910_roll_off { FE_SAT_35, FE_SAT_25, FE_SAT_20, FE_SAT_15 };
0057 
0058 static inline u32 muldiv32(u32 a, u32 b, u32 c)
0059 {
0060     u64 tmp64;
0061 
0062     tmp64 = (u64)a * (u64)b;
0063     do_div(tmp64, c);
0064 
0065     return (u32)tmp64;
0066 }
0067 
0068 struct stv_base {
0069     struct list_head     stvlist;
0070 
0071     u8                   adr;
0072     struct i2c_adapter  *i2c;
0073     struct mutex         i2c_lock; /* shared I2C access protect */
0074     struct mutex         reg_lock; /* shared register write protect */
0075     int                  count;
0076 
0077     u32                  extclk;
0078     u32                  mclk;
0079 };
0080 
0081 struct stv {
0082     struct stv_base     *base;
0083     struct dvb_frontend  fe;
0084     int                  nr;
0085     u16                  regoff;
0086     u8                   i2crpt;
0087     u8                   tscfgh;
0088     u8                   tsgeneral;
0089     u8                   tsspeed;
0090     u8                   single;
0091     unsigned long        tune_time;
0092 
0093     s32                  search_range;
0094     u32                  started;
0095     u32                  demod_lock_time;
0096     enum receive_mode    receive_mode;
0097     u32                  demod_timeout;
0098     u32                  fec_timeout;
0099     u32                  first_time_lock;
0100     u8                   demod_bits;
0101     u32                  symbol_rate;
0102 
0103     u8                       last_viterbi_rate;
0104     enum fe_code_rate        puncture_rate;
0105     enum fe_stv0910_mod_cod  mod_cod;
0106     enum dvbs2_fectype       fectype;
0107     u32                      pilots;
0108     enum fe_stv0910_roll_off feroll_off;
0109 
0110     int   is_standard_broadcast;
0111     int   is_vcm;
0112 
0113     u32   cur_scrambling_code;
0114 
0115     u32   last_bernumerator;
0116     u32   last_berdenominator;
0117     u8    berscale;
0118 
0119     u8    vth[6];
0120 };
0121 
0122 struct sinit_table {
0123     u16  address;
0124     u8   data;
0125 };
0126 
0127 struct slookup {
0128     s16  value;
0129     u32  reg_value;
0130 };
0131 
0132 static int write_reg(struct stv *state, u16 reg, u8 val)
0133 {
0134     struct i2c_adapter *adap = state->base->i2c;
0135     u8 data[3] = {reg >> 8, reg & 0xff, val};
0136     struct i2c_msg msg = {.addr = state->base->adr, .flags = 0,
0137                   .buf = data, .len = 3};
0138 
0139     if (i2c_transfer(adap, &msg, 1) != 1) {
0140         dev_warn(&adap->dev, "i2c write error ([%02x] %04x: %02x)\n",
0141              state->base->adr, reg, val);
0142         return -EIO;
0143     }
0144     return 0;
0145 }
0146 
0147 static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr,
0148                   u16 reg, u8 *val, int count)
0149 {
0150     u8 msg[2] = {reg >> 8, reg & 0xff};
0151     struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
0152                    .buf  = msg, .len   = 2},
0153                   {.addr = adr, .flags = I2C_M_RD,
0154                    .buf  = val, .len   = count } };
0155 
0156     if (i2c_transfer(adapter, msgs, 2) != 2) {
0157         dev_warn(&adapter->dev, "i2c read error ([%02x] %04x)\n",
0158              adr, reg);
0159         return -EIO;
0160     }
0161     return 0;
0162 }
0163 
0164 static int read_reg(struct stv *state, u16 reg, u8 *val)
0165 {
0166     return i2c_read_regs16(state->base->i2c, state->base->adr,
0167                    reg, val, 1);
0168 }
0169 
0170 static int read_regs(struct stv *state, u16 reg, u8 *val, int len)
0171 {
0172     return i2c_read_regs16(state->base->i2c, state->base->adr,
0173                    reg, val, len);
0174 }
0175 
0176 static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val)
0177 {
0178     int status;
0179     u8 tmp;
0180 
0181     mutex_lock(&state->base->reg_lock);
0182     status = read_reg(state, reg, &tmp);
0183     if (!status)
0184         status = write_reg(state, reg, (tmp & ~mask) | (val & mask));
0185     mutex_unlock(&state->base->reg_lock);
0186     return status;
0187 }
0188 
0189 static int write_field(struct stv *state, u32 field, u8 val)
0190 {
0191     int status;
0192     u8 shift, mask, old, new;
0193 
0194     status = read_reg(state, field >> 16, &old);
0195     if (status)
0196         return status;
0197     mask = field & 0xff;
0198     shift = (field >> 12) & 0xf;
0199     new = ((val << shift) & mask) | (old & ~mask);
0200     if (new == old)
0201         return 0;
0202     return write_reg(state, field >> 16, new);
0203 }
0204 
0205 #define SET_FIELD(_reg, _val)                   \
0206     write_field(state, state->nr ? FSTV0910_P2_##_reg : \
0207             FSTV0910_P1_##_reg, _val)
0208 
0209 #define SET_REG(_reg, _val)                 \
0210     write_reg(state, state->nr ? RSTV0910_P2_##_reg :   \
0211           RSTV0910_P1_##_reg, _val)
0212 
0213 #define GET_REG(_reg, _val)                 \
0214     read_reg(state, state->nr ? RSTV0910_P2_##_reg :    \
0215          RSTV0910_P1_##_reg, _val)
0216 
0217 static const struct slookup s1_sn_lookup[] = {
0218     {   0,    9242  }, /* C/N=   0dB */
0219     {   5,    9105  }, /* C/N= 0.5dB */
0220     {  10,    8950  }, /* C/N= 1.0dB */
0221     {  15,    8780  }, /* C/N= 1.5dB */
0222     {  20,    8566  }, /* C/N= 2.0dB */
0223     {  25,    8366  }, /* C/N= 2.5dB */
0224     {  30,    8146  }, /* C/N= 3.0dB */
0225     {  35,    7908  }, /* C/N= 3.5dB */
0226     {  40,    7666  }, /* C/N= 4.0dB */
0227     {  45,    7405  }, /* C/N= 4.5dB */
0228     {  50,    7136  }, /* C/N= 5.0dB */
0229     {  55,    6861  }, /* C/N= 5.5dB */
0230     {  60,    6576  }, /* C/N= 6.0dB */
0231     {  65,    6330  }, /* C/N= 6.5dB */
0232     {  70,    6048  }, /* C/N= 7.0dB */
0233     {  75,    5768  }, /* C/N= 7.5dB */
0234     {  80,    5492  }, /* C/N= 8.0dB */
0235     {  85,    5224  }, /* C/N= 8.5dB */
0236     {  90,    4959  }, /* C/N= 9.0dB */
0237     {  95,    4709  }, /* C/N= 9.5dB */
0238     {  100,   4467  }, /* C/N=10.0dB */
0239     {  105,   4236  }, /* C/N=10.5dB */
0240     {  110,   4013  }, /* C/N=11.0dB */
0241     {  115,   3800  }, /* C/N=11.5dB */
0242     {  120,   3598  }, /* C/N=12.0dB */
0243     {  125,   3406  }, /* C/N=12.5dB */
0244     {  130,   3225  }, /* C/N=13.0dB */
0245     {  135,   3052  }, /* C/N=13.5dB */
0246     {  140,   2889  }, /* C/N=14.0dB */
0247     {  145,   2733  }, /* C/N=14.5dB */
0248     {  150,   2587  }, /* C/N=15.0dB */
0249     {  160,   2318  }, /* C/N=16.0dB */
0250     {  170,   2077  }, /* C/N=17.0dB */
0251     {  180,   1862  }, /* C/N=18.0dB */
0252     {  190,   1670  }, /* C/N=19.0dB */
0253     {  200,   1499  }, /* C/N=20.0dB */
0254     {  210,   1347  }, /* C/N=21.0dB */
0255     {  220,   1213  }, /* C/N=22.0dB */
0256     {  230,   1095  }, /* C/N=23.0dB */
0257     {  240,    992  }, /* C/N=24.0dB */
0258     {  250,    900  }, /* C/N=25.0dB */
0259     {  260,    826  }, /* C/N=26.0dB */
0260     {  270,    758  }, /* C/N=27.0dB */
0261     {  280,    702  }, /* C/N=28.0dB */
0262     {  290,    653  }, /* C/N=29.0dB */
0263     {  300,    613  }, /* C/N=30.0dB */
0264     {  310,    579  }, /* C/N=31.0dB */
0265     {  320,    550  }, /* C/N=32.0dB */
0266     {  330,    526  }, /* C/N=33.0dB */
0267     {  350,    490  }, /* C/N=33.0dB */
0268     {  400,    445  }, /* C/N=40.0dB */
0269     {  450,    430  }, /* C/N=45.0dB */
0270     {  500,    426  }, /* C/N=50.0dB */
0271     {  510,    425  }  /* C/N=51.0dB */
0272 };
0273 
0274 static const struct slookup s2_sn_lookup[] = {
0275     {  -30,  13950  }, /* C/N=-2.5dB */
0276     {  -25,  13580  }, /* C/N=-2.5dB */
0277     {  -20,  13150  }, /* C/N=-2.0dB */
0278     {  -15,  12760  }, /* C/N=-1.5dB */
0279     {  -10,  12345  }, /* C/N=-1.0dB */
0280     {   -5,  11900  }, /* C/N=-0.5dB */
0281     {    0,  11520  }, /* C/N=   0dB */
0282     {    5,  11080  }, /* C/N= 0.5dB */
0283     {   10,  10630  }, /* C/N= 1.0dB */
0284     {   15,  10210  }, /* C/N= 1.5dB */
0285     {   20,   9790  }, /* C/N= 2.0dB */
0286     {   25,   9390  }, /* C/N= 2.5dB */
0287     {   30,   8970  }, /* C/N= 3.0dB */
0288     {   35,   8575  }, /* C/N= 3.5dB */
0289     {   40,   8180  }, /* C/N= 4.0dB */
0290     {   45,   7800  }, /* C/N= 4.5dB */
0291     {   50,   7430  }, /* C/N= 5.0dB */
0292     {   55,   7080  }, /* C/N= 5.5dB */
0293     {   60,   6720  }, /* C/N= 6.0dB */
0294     {   65,   6320  }, /* C/N= 6.5dB */
0295     {   70,   6060  }, /* C/N= 7.0dB */
0296     {   75,   5760  }, /* C/N= 7.5dB */
0297     {   80,   5480  }, /* C/N= 8.0dB */
0298     {   85,   5200  }, /* C/N= 8.5dB */
0299     {   90,   4930  }, /* C/N= 9.0dB */
0300     {   95,   4680  }, /* C/N= 9.5dB */
0301     {  100,   4425  }, /* C/N=10.0dB */
0302     {  105,   4210  }, /* C/N=10.5dB */
0303     {  110,   3980  }, /* C/N=11.0dB */
0304     {  115,   3765  }, /* C/N=11.5dB */
0305     {  120,   3570  }, /* C/N=12.0dB */
0306     {  125,   3315  }, /* C/N=12.5dB */
0307     {  130,   3140  }, /* C/N=13.0dB */
0308     {  135,   2980  }, /* C/N=13.5dB */
0309     {  140,   2820  }, /* C/N=14.0dB */
0310     {  145,   2670  }, /* C/N=14.5dB */
0311     {  150,   2535  }, /* C/N=15.0dB */
0312     {  160,   2270  }, /* C/N=16.0dB */
0313     {  170,   2035  }, /* C/N=17.0dB */
0314     {  180,   1825  }, /* C/N=18.0dB */
0315     {  190,   1650  }, /* C/N=19.0dB */
0316     {  200,   1485  }, /* C/N=20.0dB */
0317     {  210,   1340  }, /* C/N=21.0dB */
0318     {  220,   1212  }, /* C/N=22.0dB */
0319     {  230,   1100  }, /* C/N=23.0dB */
0320     {  240,   1000  }, /* C/N=24.0dB */
0321     {  250,    910  }, /* C/N=25.0dB */
0322     {  260,    836  }, /* C/N=26.0dB */
0323     {  270,    772  }, /* C/N=27.0dB */
0324     {  280,    718  }, /* C/N=28.0dB */
0325     {  290,    671  }, /* C/N=29.0dB */
0326     {  300,    635  }, /* C/N=30.0dB */
0327     {  310,    602  }, /* C/N=31.0dB */
0328     {  320,    575  }, /* C/N=32.0dB */
0329     {  330,    550  }, /* C/N=33.0dB */
0330     {  350,    517  }, /* C/N=35.0dB */
0331     {  400,    480  }, /* C/N=40.0dB */
0332     {  450,    466  }, /* C/N=45.0dB */
0333     {  500,    464  }, /* C/N=50.0dB */
0334     {  510,    463  }, /* C/N=51.0dB */
0335 };
0336 
0337 static const struct slookup padc_lookup[] = {
0338     {    0,  118000 }, /* PADC= +0dBm */
0339     { -100,  93600  }, /* PADC= -1dBm */
0340     { -200,  74500  }, /* PADC= -2dBm */
0341     { -300,  59100  }, /* PADC= -3dBm */
0342     { -400,  47000  }, /* PADC= -4dBm */
0343     { -500,  37300  }, /* PADC= -5dBm */
0344     { -600,  29650  }, /* PADC= -6dBm */
0345     { -700,  23520  }, /* PADC= -7dBm */
0346     { -900,  14850  }, /* PADC= -9dBm */
0347     { -1100, 9380   }, /* PADC=-11dBm */
0348     { -1300, 5910   }, /* PADC=-13dBm */
0349     { -1500, 3730   }, /* PADC=-15dBm */
0350     { -1700, 2354   }, /* PADC=-17dBm */
0351     { -1900, 1485   }, /* PADC=-19dBm */
0352     { -2000, 1179   }, /* PADC=-20dBm */
0353     { -2100, 1000   }, /* PADC=-21dBm */
0354 };
0355 
0356 /*********************************************************************
0357  * Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame
0358  *********************************************************************/
0359 static const u8 s2car_loop[] =  {
0360     /*
0361      * Modcod  2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff
0362      * 20MPon 20MPoff 30MPon 30MPoff
0363      */
0364 
0365     /* FE_QPSK_14  */
0366     0x0C,  0x3C,  0x0B,  0x3C,  0x2A,  0x2C,  0x2A,  0x1C,  0x3A,  0x3B,
0367     /* FE_QPSK_13  */
0368     0x0C,  0x3C,  0x0B,  0x3C,  0x2A,  0x2C,  0x3A,  0x0C,  0x3A,  0x2B,
0369     /* FE_QPSK_25  */
0370     0x1C,  0x3C,  0x1B,  0x3C,  0x3A,  0x1C,  0x3A,  0x3B,  0x3A,  0x2B,
0371     /* FE_QPSK_12  */
0372     0x0C,  0x1C,  0x2B,  0x1C,  0x0B,  0x2C,  0x0B,  0x0C,  0x2A,  0x2B,
0373     /* FE_QPSK_35  */
0374     0x1C,  0x1C,  0x2B,  0x1C,  0x0B,  0x2C,  0x0B,  0x0C,  0x2A,  0x2B,
0375     /* FE_QPSK_23  */
0376     0x2C,  0x2C,  0x2B,  0x1C,  0x0B,  0x2C,  0x0B,  0x0C,  0x2A,  0x2B,
0377     /* FE_QPSK_34  */
0378     0x3C,  0x2C,  0x3B,  0x2C,  0x1B,  0x1C,  0x1B,  0x3B,  0x3A,  0x1B,
0379     /* FE_QPSK_45  */
0380     0x0D,  0x3C,  0x3B,  0x2C,  0x1B,  0x1C,  0x1B,  0x3B,  0x3A,  0x1B,
0381     /* FE_QPSK_56  */
0382     0x1D,  0x3C,  0x0C,  0x2C,  0x2B,  0x1C,  0x1B,  0x3B,  0x0B,  0x1B,
0383     /* FE_QPSK_89  */
0384     0x3D,  0x0D,  0x0C,  0x2C,  0x2B,  0x0C,  0x2B,  0x2B,  0x0B,  0x0B,
0385     /* FE_QPSK_910 */
0386     0x1E,  0x0D,  0x1C,  0x2C,  0x3B,  0x0C,  0x2B,  0x2B,  0x1B,  0x0B,
0387     /* FE_8PSK_35  */
0388     0x28,  0x09,  0x28,  0x09,  0x28,  0x09,  0x28,  0x08,  0x28,  0x27,
0389     /* FE_8PSK_23  */
0390     0x19,  0x29,  0x19,  0x29,  0x19,  0x29,  0x38,  0x19,  0x28,  0x09,
0391     /* FE_8PSK_34  */
0392     0x1A,  0x0B,  0x1A,  0x3A,  0x0A,  0x2A,  0x39,  0x2A,  0x39,  0x1A,
0393     /* FE_8PSK_56  */
0394     0x2B,  0x2B,  0x1B,  0x1B,  0x0B,  0x1B,  0x1A,  0x0B,  0x1A,  0x1A,
0395     /* FE_8PSK_89  */
0396     0x0C,  0x0C,  0x3B,  0x3B,  0x1B,  0x1B,  0x2A,  0x0B,  0x2A,  0x2A,
0397     /* FE_8PSK_910 */
0398     0x0C,  0x1C,  0x0C,  0x3B,  0x2B,  0x1B,  0x3A,  0x0B,  0x2A,  0x2A,
0399 
0400     /**********************************************************************
0401      * Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame
0402      **********************************************************************/
0403 
0404     /*
0405      * Modcod 2MPon  2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon
0406      * 20MPoff 30MPon 30MPoff
0407      */
0408 
0409     /* FE_16APSK_23  */
0410     0x0A,  0x0A,  0x0A,  0x0A,  0x1A,  0x0A,  0x39,  0x0A,  0x29,  0x0A,
0411     /* FE_16APSK_34  */
0412     0x0A,  0x0A,  0x0A,  0x0A,  0x0B,  0x0A,  0x2A,  0x0A,  0x1A,  0x0A,
0413     /* FE_16APSK_45  */
0414     0x0A,  0x0A,  0x0A,  0x0A,  0x1B,  0x0A,  0x3A,  0x0A,  0x2A,  0x0A,
0415     /* FE_16APSK_56  */
0416     0x0A,  0x0A,  0x0A,  0x0A,  0x1B,  0x0A,  0x3A,  0x0A,  0x2A,  0x0A,
0417     /* FE_16APSK_89  */
0418     0x0A,  0x0A,  0x0A,  0x0A,  0x2B,  0x0A,  0x0B,  0x0A,  0x3A,  0x0A,
0419     /* FE_16APSK_910 */
0420     0x0A,  0x0A,  0x0A,  0x0A,  0x2B,  0x0A,  0x0B,  0x0A,  0x3A,  0x0A,
0421     /* FE_32APSK_34  */
0422     0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,
0423     /* FE_32APSK_45  */
0424     0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,
0425     /* FE_32APSK_56  */
0426     0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,
0427     /* FE_32APSK_89  */
0428     0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,
0429     /* FE_32APSK_910 */
0430     0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,  0x09,
0431 };
0432 
0433 static u8 get_optim_cloop(struct stv *state,
0434               enum fe_stv0910_mod_cod mod_cod, u32 pilots)
0435 {
0436     int i = 0;
0437 
0438     if (mod_cod >= FE_32APSK_910)
0439         i = ((int)FE_32APSK_910 - (int)FE_QPSK_14) * 10;
0440     else if (mod_cod >= FE_QPSK_14)
0441         i = ((int)mod_cod - (int)FE_QPSK_14) * 10;
0442 
0443     if (state->symbol_rate <= 3000000)
0444         i += 0;
0445     else if (state->symbol_rate <=  7000000)
0446         i += 2;
0447     else if (state->symbol_rate <= 15000000)
0448         i += 4;
0449     else if (state->symbol_rate <= 25000000)
0450         i += 6;
0451     else
0452         i += 8;
0453 
0454     if (!pilots)
0455         i += 1;
0456 
0457     return s2car_loop[i];
0458 }
0459 
0460 static int get_cur_symbol_rate(struct stv *state, u32 *p_symbol_rate)
0461 {
0462     int status = 0;
0463     u8 symb_freq0;
0464     u8 symb_freq1;
0465     u8 symb_freq2;
0466     u8 symb_freq3;
0467     u8 tim_offs0;
0468     u8 tim_offs1;
0469     u8 tim_offs2;
0470     u32 symbol_rate;
0471     s32 timing_offset;
0472 
0473     *p_symbol_rate = 0;
0474     if (!state->started)
0475         return status;
0476 
0477     read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3);
0478     read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2);
0479     read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1);
0480     read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0);
0481     read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2);
0482     read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1);
0483     read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0);
0484 
0485     symbol_rate = ((u32)symb_freq3 << 24) | ((u32)symb_freq2 << 16) |
0486         ((u32)symb_freq1 << 8) | (u32)symb_freq0;
0487     timing_offset = ((u32)tim_offs2 << 16) | ((u32)tim_offs1 << 8) |
0488         (u32)tim_offs0;
0489 
0490     if ((timing_offset & (1 << 23)) != 0)
0491         timing_offset |= 0xFF000000; /* Sign extent */
0492 
0493     symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32);
0494     timing_offset = (s32)(((s64)symbol_rate * (s64)timing_offset) >> 29);
0495 
0496     *p_symbol_rate = symbol_rate + timing_offset;
0497 
0498     return 0;
0499 }
0500 
0501 static int get_signal_parameters(struct stv *state)
0502 {
0503     u8 tmp;
0504 
0505     if (!state->started)
0506         return -EINVAL;
0507 
0508     if (state->receive_mode == RCVMODE_DVBS2) {
0509         read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
0510         state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
0511         state->pilots = (tmp & 0x01) != 0;
0512         state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1);
0513 
0514     } else if (state->receive_mode == RCVMODE_DVBS) {
0515         read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
0516         state->puncture_rate = FEC_NONE;
0517         switch (tmp & 0x1F) {
0518         case 0x0d:
0519             state->puncture_rate = FEC_1_2;
0520             break;
0521         case 0x12:
0522             state->puncture_rate = FEC_2_3;
0523             break;
0524         case 0x15:
0525             state->puncture_rate = FEC_3_4;
0526             break;
0527         case 0x18:
0528             state->puncture_rate = FEC_5_6;
0529             break;
0530         case 0x1a:
0531             state->puncture_rate = FEC_7_8;
0532             break;
0533         }
0534         state->is_vcm = 0;
0535         state->is_standard_broadcast = 1;
0536         state->feroll_off = FE_SAT_35;
0537     }
0538     return 0;
0539 }
0540 
0541 static int tracking_optimization(struct stv *state)
0542 {
0543     u8 tmp;
0544 
0545     read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp);
0546     tmp &= ~0xC0;
0547 
0548     switch (state->receive_mode) {
0549     case RCVMODE_DVBS:
0550         tmp |= 0x40;
0551         break;
0552     case RCVMODE_DVBS2:
0553         tmp |= 0x80;
0554         break;
0555     default:
0556         tmp |= 0xC0;
0557         break;
0558     }
0559     write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp);
0560 
0561     if (state->receive_mode == RCVMODE_DVBS2) {
0562         /* Disable Reed-Solomon */
0563         write_shared_reg(state,
0564                  RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01,
0565                  0x03);
0566 
0567         if (state->fectype == DVBS2_64K) {
0568             u8 aclc = get_optim_cloop(state, state->mod_cod,
0569                           state->pilots);
0570 
0571             if (state->mod_cod <= FE_QPSK_910) {
0572                 write_reg(state, RSTV0910_P2_ACLC2S2Q +
0573                       state->regoff, aclc);
0574             } else if (state->mod_cod <= FE_8PSK_910) {
0575                 write_reg(state, RSTV0910_P2_ACLC2S2Q +
0576                       state->regoff, 0x2a);
0577                 write_reg(state, RSTV0910_P2_ACLC2S28 +
0578                       state->regoff, aclc);
0579             } else if (state->mod_cod <= FE_16APSK_910) {
0580                 write_reg(state, RSTV0910_P2_ACLC2S2Q +
0581                       state->regoff, 0x2a);
0582                 write_reg(state, RSTV0910_P2_ACLC2S216A +
0583                       state->regoff, aclc);
0584             } else if (state->mod_cod <= FE_32APSK_910) {
0585                 write_reg(state, RSTV0910_P2_ACLC2S2Q +
0586                       state->regoff, 0x2a);
0587                 write_reg(state, RSTV0910_P2_ACLC2S232A +
0588                       state->regoff, aclc);
0589             }
0590         }
0591     }
0592     return 0;
0593 }
0594 
0595 static s32 table_lookup(const struct slookup *table,
0596             int table_size, u32 reg_value)
0597 {
0598     s32 value;
0599     int imin = 0;
0600     int imax = table_size - 1;
0601     int i;
0602     s32 reg_diff;
0603 
0604     /* Assumes Table[0].RegValue > Table[imax].RegValue */
0605     if (reg_value >= table[0].reg_value) {
0606         value = table[0].value;
0607     } else if (reg_value <= table[imax].reg_value) {
0608         value = table[imax].value;
0609     } else {
0610         while ((imax - imin) > 1) {
0611             i = (imax + imin) / 2;
0612             if ((table[imin].reg_value >= reg_value) &&
0613                 (reg_value >= table[i].reg_value))
0614                 imax = i;
0615             else
0616                 imin = i;
0617         }
0618 
0619         reg_diff = table[imax].reg_value - table[imin].reg_value;
0620         value = table[imin].value;
0621         if (reg_diff != 0)
0622             value += ((s32)(reg_value - table[imin].reg_value) *
0623                   (s32)(table[imax].value
0624                     - table[imin].value))
0625                     / (reg_diff);
0626     }
0627 
0628     return value;
0629 }
0630 
0631 static int get_signal_to_noise(struct stv *state, s32 *signal_to_noise)
0632 {
0633     u8 data0;
0634     u8 data1;
0635     u16 data;
0636     int n_lookup;
0637     const struct slookup *lookup;
0638 
0639     *signal_to_noise = 0;
0640 
0641     if (!state->started)
0642         return -EINVAL;
0643 
0644     if (state->receive_mode == RCVMODE_DVBS2) {
0645         read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff,
0646              &data1);
0647         read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff,
0648              &data0);
0649         n_lookup = ARRAY_SIZE(s2_sn_lookup);
0650         lookup = s2_sn_lookup;
0651     } else {
0652         read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff,
0653              &data1);
0654         read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff,
0655              &data0);
0656         n_lookup = ARRAY_SIZE(s1_sn_lookup);
0657         lookup = s1_sn_lookup;
0658     }
0659     data = (((u16)data1) << 8) | (u16)data0;
0660     *signal_to_noise = table_lookup(lookup, n_lookup, data);
0661     return 0;
0662 }
0663 
0664 static int get_bit_error_rate_s(struct stv *state, u32 *bernumerator,
0665                 u32 *berdenominator)
0666 {
0667     u8 regs[3];
0668 
0669     int status = read_regs(state,
0670                    RSTV0910_P2_ERRCNT12 + state->regoff,
0671                    regs, 3);
0672 
0673     if (status)
0674         return -EINVAL;
0675 
0676     if ((regs[0] & 0x80) == 0) {
0677         state->last_berdenominator = 1ULL << ((state->berscale * 2) +
0678                              10 + 3);
0679         state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) |
0680             ((u32)regs[1] << 8) | regs[2];
0681         if (state->last_bernumerator < 256 && state->berscale < 6) {
0682             state->berscale += 1;
0683             status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
0684                        state->regoff,
0685                        0x20 | state->berscale);
0686         } else if (state->last_bernumerator > 1024 &&
0687                state->berscale > 2) {
0688             state->berscale -= 1;
0689             status = write_reg(state, RSTV0910_P2_ERRCTRL1 +
0690                        state->regoff, 0x20 |
0691                        state->berscale);
0692         }
0693     }
0694     *bernumerator = state->last_bernumerator;
0695     *berdenominator = state->last_berdenominator;
0696     return 0;
0697 }
0698 
0699 static u32 dvbs2_nbch(enum dvbs2_mod_cod mod_cod, enum dvbs2_fectype fectype)
0700 {
0701     static const u32 nbch[][2] = {
0702         {    0,     0}, /* DUMMY_PLF   */
0703         {16200,  3240}, /* QPSK_1_4,   */
0704         {21600,  5400}, /* QPSK_1_3,   */
0705         {25920,  6480}, /* QPSK_2_5,   */
0706         {32400,  7200}, /* QPSK_1_2,   */
0707         {38880,  9720}, /* QPSK_3_5,   */
0708         {43200, 10800}, /* QPSK_2_3,   */
0709         {48600, 11880}, /* QPSK_3_4,   */
0710         {51840, 12600}, /* QPSK_4_5,   */
0711         {54000, 13320}, /* QPSK_5_6,   */
0712         {57600, 14400}, /* QPSK_8_9,   */
0713         {58320, 16000}, /* QPSK_9_10,  */
0714         {43200,  9720}, /* 8PSK_3_5,   */
0715         {48600, 10800}, /* 8PSK_2_3,   */
0716         {51840, 11880}, /* 8PSK_3_4,   */
0717         {54000, 13320}, /* 8PSK_5_6,   */
0718         {57600, 14400}, /* 8PSK_8_9,   */
0719         {58320, 16000}, /* 8PSK_9_10,  */
0720         {43200, 10800}, /* 16APSK_2_3, */
0721         {48600, 11880}, /* 16APSK_3_4, */
0722         {51840, 12600}, /* 16APSK_4_5, */
0723         {54000, 13320}, /* 16APSK_5_6, */
0724         {57600, 14400}, /* 16APSK_8_9, */
0725         {58320, 16000}, /* 16APSK_9_10 */
0726         {48600, 11880}, /* 32APSK_3_4, */
0727         {51840, 12600}, /* 32APSK_4_5, */
0728         {54000, 13320}, /* 32APSK_5_6, */
0729         {57600, 14400}, /* 32APSK_8_9, */
0730         {58320, 16000}, /* 32APSK_9_10 */
0731     };
0732 
0733     if (mod_cod >= DVBS2_QPSK_1_4 &&
0734         mod_cod <= DVBS2_32APSK_9_10 && fectype <= DVBS2_16K)
0735         return nbch[mod_cod][fectype];
0736     return 64800;
0737 }
0738 
0739 static int get_bit_error_rate_s2(struct stv *state, u32 *bernumerator,
0740                  u32 *berdenominator)
0741 {
0742     u8 regs[3];
0743 
0744     int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff,
0745                    regs, 3);
0746 
0747     if (status)
0748         return -EINVAL;
0749 
0750     if ((regs[0] & 0x80) == 0) {
0751         state->last_berdenominator =
0752             dvbs2_nbch((enum dvbs2_mod_cod)state->mod_cod,
0753                    state->fectype) <<
0754             (state->berscale * 2);
0755         state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) |
0756             ((u32)regs[1] << 8) | regs[2];
0757         if (state->last_bernumerator < 256 && state->berscale < 6) {
0758             state->berscale += 1;
0759             write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
0760                   0x20 | state->berscale);
0761         } else if (state->last_bernumerator > 1024 &&
0762                state->berscale > 2) {
0763             state->berscale -= 1;
0764             write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,
0765                   0x20 | state->berscale);
0766         }
0767     }
0768     *bernumerator = state->last_bernumerator;
0769     *berdenominator = state->last_berdenominator;
0770     return status;
0771 }
0772 
0773 static int get_bit_error_rate(struct stv *state, u32 *bernumerator,
0774                   u32 *berdenominator)
0775 {
0776     *bernumerator = 0;
0777     *berdenominator = 1;
0778 
0779     switch (state->receive_mode) {
0780     case RCVMODE_DVBS:
0781         return get_bit_error_rate_s(state,
0782                         bernumerator, berdenominator);
0783     case RCVMODE_DVBS2:
0784         return get_bit_error_rate_s2(state,
0785                          bernumerator, berdenominator);
0786     default:
0787         break;
0788     }
0789     return 0;
0790 }
0791 
0792 static int set_mclock(struct stv *state, u32 master_clock)
0793 {
0794     u32 idf = 1;
0795     u32 odf = 4;
0796     u32 quartz = state->base->extclk / 1000000;
0797     u32 fphi = master_clock / 1000000;
0798     u32 ndiv = (fphi * odf * idf) / quartz;
0799     u32 cp = 7;
0800     u32 fvco;
0801 
0802     if (ndiv >= 7 && ndiv <= 71)
0803         cp = 7;
0804     else if (ndiv >=  72 && ndiv <=  79)
0805         cp = 8;
0806     else if (ndiv >=  80 && ndiv <=  87)
0807         cp = 9;
0808     else if (ndiv >=  88 && ndiv <=  95)
0809         cp = 10;
0810     else if (ndiv >=  96 && ndiv <= 103)
0811         cp = 11;
0812     else if (ndiv >= 104 && ndiv <= 111)
0813         cp = 12;
0814     else if (ndiv >= 112 && ndiv <= 119)
0815         cp = 13;
0816     else if (ndiv >= 120 && ndiv <= 127)
0817         cp = 14;
0818     else if (ndiv >= 128 && ndiv <= 135)
0819         cp = 15;
0820     else if (ndiv >= 136 && ndiv <= 143)
0821         cp = 16;
0822     else if (ndiv >= 144 && ndiv <= 151)
0823         cp = 17;
0824     else if (ndiv >= 152 && ndiv <= 159)
0825         cp = 18;
0826     else if (ndiv >= 160 && ndiv <= 167)
0827         cp = 19;
0828     else if (ndiv >= 168 && ndiv <= 175)
0829         cp = 20;
0830     else if (ndiv >= 176 && ndiv <= 183)
0831         cp = 21;
0832     else if (ndiv >= 184 && ndiv <= 191)
0833         cp = 22;
0834     else if (ndiv >= 192 && ndiv <= 199)
0835         cp = 23;
0836     else if (ndiv >= 200 && ndiv <= 207)
0837         cp = 24;
0838     else if (ndiv >= 208 && ndiv <= 215)
0839         cp = 25;
0840     else if (ndiv >= 216 && ndiv <= 223)
0841         cp = 26;
0842     else if (ndiv >= 224 && ndiv <= 225)
0843         cp = 27;
0844 
0845     write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf);
0846     write_reg(state, RSTV0910_NCOARSE2, odf);
0847     write_reg(state, RSTV0910_NCOARSE1, ndiv);
0848 
0849     fvco = (quartz * 2 * ndiv) / idf;
0850     state->base->mclk = fvco / (2 * odf) * 1000000;
0851 
0852     return 0;
0853 }
0854 
0855 static int stop(struct stv *state)
0856 {
0857     if (state->started) {
0858         u8 tmp;
0859 
0860         write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
0861               state->tscfgh | 0x01);
0862         read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp);
0863         tmp &= ~0x01; /* release reset DVBS2 packet delin */
0864         write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp);
0865         /* Blind optim*/
0866         write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B);
0867         /* Stop the demod */
0868         write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c);
0869         state->started = 0;
0870     }
0871     state->receive_mode = RCVMODE_NONE;
0872     return 0;
0873 }
0874 
0875 static void set_pls(struct stv *state, u32 pls_code)
0876 {
0877     if (pls_code == state->cur_scrambling_code)
0878         return;
0879 
0880     /* PLROOT2 bit 2 = gold code */
0881     write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff,
0882           pls_code & 0xff);
0883     write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff,
0884           (pls_code >> 8) & 0xff);
0885     write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff,
0886           0x04 | ((pls_code >> 16) & 0x03));
0887     state->cur_scrambling_code = pls_code;
0888 }
0889 
0890 static void set_isi(struct stv *state, u32 isi)
0891 {
0892     if (isi == NO_STREAM_ID_FILTER)
0893         return;
0894     if (isi == 0x80000000) {
0895         SET_FIELD(FORCE_CONTINUOUS, 1);
0896         SET_FIELD(TSOUT_NOSYNC, 1);
0897     } else {
0898         SET_FIELD(FILTER_EN, 1);
0899         write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff,
0900               isi & 0xff);
0901         write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff);
0902     }
0903     SET_FIELD(ALGOSWRST, 1);
0904     SET_FIELD(ALGOSWRST, 0);
0905 }
0906 
0907 static void set_stream_modes(struct stv *state,
0908                  struct dtv_frontend_properties *p)
0909 {
0910     set_isi(state, p->stream_id);
0911     set_pls(state, p->scrambling_sequence_index);
0912 }
0913 
0914 static int init_search_param(struct stv *state,
0915                  struct dtv_frontend_properties *p)
0916 {
0917     SET_FIELD(FORCE_CONTINUOUS, 0);
0918     SET_FIELD(FRAME_MODE, 0);
0919     SET_FIELD(FILTER_EN, 0);
0920     SET_FIELD(TSOUT_NOSYNC, 0);
0921     SET_FIELD(TSFIFO_EMBINDVB, 0);
0922     SET_FIELD(TSDEL_SYNCBYTE, 0);
0923     SET_REG(UPLCCST0, 0xe0);
0924     SET_FIELD(TSINS_TOKEN, 0);
0925     SET_FIELD(HYSTERESIS_THRESHOLD, 0);
0926     SET_FIELD(ISIOBS_MODE, 1);
0927 
0928     set_stream_modes(state, p);
0929     return 0;
0930 }
0931 
0932 static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate)
0933 {
0934     u8 val;
0935 
0936     switch (rate) {
0937     case FEC_1_2:
0938         val = 0x01;
0939         break;
0940     case FEC_2_3:
0941         val = 0x02;
0942         break;
0943     case FEC_3_4:
0944         val = 0x04;
0945         break;
0946     case FEC_5_6:
0947         val = 0x08;
0948         break;
0949     case FEC_7_8:
0950         val = 0x20;
0951         break;
0952     case FEC_NONE:
0953     default:
0954         val = 0x2f;
0955         break;
0956     }
0957 
0958     return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val);
0959 }
0960 
0961 static int set_vth_default(struct stv *state)
0962 {
0963     state->vth[0] = 0xd7;
0964     state->vth[1] = 0x85;
0965     state->vth[2] = 0x58;
0966     state->vth[3] = 0x3a;
0967     state->vth[4] = 0x34;
0968     state->vth[5] = 0x28;
0969     write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
0970     write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
0971     write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
0972     write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
0973     write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
0974     write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
0975     return 0;
0976 }
0977 
0978 static int set_vth(struct stv *state)
0979 {
0980     static const struct slookup vthlookup_table[] = {
0981         {250,   8780}, /* C/N= 1.5dB */
0982         {100,   7405}, /* C/N= 4.5dB */
0983         {40,    6330}, /* C/N= 6.5dB */
0984         {12,    5224}, /* C/N= 8.5dB */
0985         {5, 4236}  /* C/N=10.5dB */
0986     };
0987 
0988     int i;
0989     u8 tmp[2];
0990     int status = read_regs(state,
0991                    RSTV0910_P2_NNOSDATAT1 + state->regoff,
0992                    tmp, 2);
0993     u16 reg_value = (tmp[0] << 8) | tmp[1];
0994     s32 vth = table_lookup(vthlookup_table, ARRAY_SIZE(vthlookup_table),
0995                   reg_value);
0996 
0997     for (i = 0; i < 6; i += 1)
0998         if (state->vth[i] > vth)
0999             state->vth[i] = vth;
1000 
1001     write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
1002     write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
1003     write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
1004     write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
1005     write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
1006     write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
1007     return status;
1008 }
1009 
1010 static int start(struct stv *state, struct dtv_frontend_properties *p)
1011 {
1012     s32 freq;
1013     u8  reg_dmdcfgmd;
1014     u16 symb;
1015 
1016     if (p->symbol_rate < 100000 || p->symbol_rate > 70000000)
1017         return -EINVAL;
1018 
1019     state->receive_mode = RCVMODE_NONE;
1020     state->demod_lock_time = 0;
1021 
1022     /* Demod Stop */
1023     if (state->started)
1024         write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C);
1025 
1026     init_search_param(state, p);
1027 
1028     if (p->symbol_rate <= 1000000) { /* SR <=1Msps */
1029         state->demod_timeout = 3000;
1030         state->fec_timeout = 2000;
1031     } else if (p->symbol_rate <= 2000000) { /* 1Msps < SR <=2Msps */
1032         state->demod_timeout = 2500;
1033         state->fec_timeout = 1300;
1034     } else if (p->symbol_rate <= 5000000) { /* 2Msps< SR <=5Msps */
1035         state->demod_timeout = 1000;
1036         state->fec_timeout = 650;
1037     } else if (p->symbol_rate <= 10000000) { /* 5Msps< SR <=10Msps */
1038         state->demod_timeout = 700;
1039         state->fec_timeout = 350;
1040     } else if (p->symbol_rate < 20000000) { /* 10Msps< SR <=20Msps */
1041         state->demod_timeout = 400;
1042         state->fec_timeout = 200;
1043     } else { /* SR >=20Msps */
1044         state->demod_timeout = 300;
1045         state->fec_timeout = 200;
1046     }
1047 
1048     /* Set the Init Symbol rate */
1049     symb = muldiv32(p->symbol_rate, 65536, state->base->mclk);
1050     write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff,
1051           ((symb >> 8) & 0x7F));
1052     write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF));
1053 
1054     state->demod_bits |= 0x80;
1055     write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits);
1056 
1057     /* FE_STV0910_SetSearchStandard */
1058     read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &reg_dmdcfgmd);
1059     write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff,
1060           reg_dmdcfgmd |= 0xC0);
1061 
1062     write_shared_reg(state,
1063              RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00);
1064 
1065     /* Disable DSS */
1066     write_reg(state, RSTV0910_P2_FECM  + state->regoff, 0x00);
1067     write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F);
1068 
1069     enable_puncture_rate(state, FEC_NONE);
1070 
1071     /* 8PSK 3/5, 8PSK 2/3 Poff tracking optimization WA */
1072     write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B);
1073     write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A);
1074     write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84);
1075     write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84);
1076     write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C);
1077     write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79);
1078 
1079     write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29);
1080     write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09);
1081     write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84);
1082     write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84);
1083 
1084     /*
1085      * Reset CAR3, bug DVBS2->DVBS1 lock
1086      * Note: The bit is only pulsed -> no lock on shared register needed
1087      */
1088     write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08);
1089     write_reg(state, RSTV0910_TSTRES0, 0);
1090 
1091     set_vth_default(state);
1092     /* Reset demod */
1093     write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1094 
1095     write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46);
1096 
1097     if (p->symbol_rate <= 5000000)
1098         freq = (state->search_range / 2000) + 80;
1099     else
1100         freq = (state->search_range / 2000) + 1600;
1101     freq = (freq << 16) / (state->base->mclk / 1000);
1102 
1103     write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff,
1104           (freq >> 8) & 0xff);
1105     write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff));
1106     /* CFR Low Setting */
1107     freq = -freq;
1108     write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff,
1109           (freq >> 8) & 0xff);
1110     write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff));
1111 
1112     /* init the demod frequency offset to 0 */
1113     write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0);
1114     write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0);
1115 
1116     write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);
1117     /* Trigger acq */
1118     write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15);
1119 
1120     state->demod_lock_time += TUNING_DELAY;
1121     state->started = 1;
1122 
1123     return 0;
1124 }
1125 
1126 static int init_diseqc(struct stv *state)
1127 {
1128     u16 offs = state->nr ? 0x40 : 0; /* Address offset */
1129     u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32));
1130 
1131     /* Disable receiver */
1132     write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00);
1133     write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */
1134     write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */
1135     write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq);
1136     return 0;
1137 }
1138 
1139 static int probe(struct stv *state)
1140 {
1141     u8 id;
1142 
1143     state->receive_mode = RCVMODE_NONE;
1144     state->started = 0;
1145 
1146     if (read_reg(state, RSTV0910_MID, &id) < 0)
1147         return -ENODEV;
1148 
1149     if (id != 0x51)
1150         return -EINVAL;
1151 
1152     /* Configure the I2C repeater to off */
1153     write_reg(state, RSTV0910_P1_I2CRPT, 0x24);
1154     /* Configure the I2C repeater to off */
1155     write_reg(state, RSTV0910_P2_I2CRPT, 0x24);
1156     /* Set the I2C to oversampling ratio */
1157     write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */
1158 
1159     write_reg(state, RSTV0910_OUTCFG,    0x00); /* OUTCFG */
1160     write_reg(state, RSTV0910_PADCFG,    0x05); /* RFAGC Pads Dev = 05 */
1161     write_reg(state, RSTV0910_SYNTCTRL,  0x02); /* SYNTCTRL */
1162     write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */
1163     write_reg(state, RSTV0910_CFGEXT,    0x02); /* CFGEXT */
1164 
1165     if (state->single)
1166         write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */
1167     else
1168         write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */
1169 
1170     write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */
1171     write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */
1172 
1173     write_reg(state, RSTV0910_P1_CAR3CFG, 0x02);
1174     write_reg(state, RSTV0910_P2_CAR3CFG, 0x02);
1175     write_reg(state, RSTV0910_P1_DMDCFG4, 0x04);
1176     write_reg(state, RSTV0910_P2_DMDCFG4, 0x04);
1177 
1178     write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */
1179     write_reg(state, RSTV0910_TSTRES0, 0x00);
1180 
1181     write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00);
1182     write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00);
1183 
1184     write_reg(state, RSTV0910_P1_TMGCFG2, 0x80);
1185     write_reg(state, RSTV0910_P2_TMGCFG2, 0x80);
1186 
1187     set_mclock(state, 135000000);
1188 
1189     /* TS output */
1190     write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1191     write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1192     write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */
1193     write_reg(state, RSTV0910_P1_TSCFGL, 0x20);
1194 
1195     write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed);
1196 
1197     write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1198     write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1199     write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */
1200     write_reg(state, RSTV0910_P2_TSCFGL, 0x20);
1201 
1202     write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed);
1203 
1204     /* Reset stream merger */
1205     write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);
1206     write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);
1207     write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);
1208     write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);
1209 
1210     write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt);
1211     write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt);
1212 
1213     write_reg(state, RSTV0910_P1_TSINSDELM, 0x17);
1214     write_reg(state, RSTV0910_P1_TSINSDELL, 0xff);
1215 
1216     write_reg(state, RSTV0910_P2_TSINSDELM, 0x17);
1217     write_reg(state, RSTV0910_P2_TSINSDELL, 0xff);
1218 
1219     init_diseqc(state);
1220     return 0;
1221 }
1222 
1223 static int gate_ctrl(struct dvb_frontend *fe, int enable)
1224 {
1225     struct stv *state = fe->demodulator_priv;
1226     u8 i2crpt = state->i2crpt & ~0x86;
1227 
1228     /*
1229      * mutex_lock note: Concurrent I2C gate bus accesses must be
1230      * prevented (STV0910 = dual demod on a single IC with a single I2C
1231      * gate/bus, and two tuners attached), similar to most (if not all)
1232      * other I2C host interfaces/buses.
1233      *
1234      * enable=1 (open I2C gate) will grab the lock
1235      * enable=0 (close I2C gate) releases the lock
1236      */
1237 
1238     if (enable) {
1239         mutex_lock(&state->base->i2c_lock);
1240         i2crpt |= 0x80;
1241     } else {
1242         i2crpt |= 0x02;
1243     }
1244 
1245     if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT :
1246               RSTV0910_P1_I2CRPT, i2crpt) < 0) {
1247         /* don't hold the I2C bus lock on failure */
1248         if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1249             mutex_unlock(&state->base->i2c_lock);
1250         dev_err(&state->base->i2c->dev,
1251             "%s() write_reg failure (enable=%d)\n",
1252             __func__, enable);
1253         return -EIO;
1254     }
1255 
1256     state->i2crpt = i2crpt;
1257 
1258     if (!enable)
1259         if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))
1260             mutex_unlock(&state->base->i2c_lock);
1261     return 0;
1262 }
1263 
1264 static void release(struct dvb_frontend *fe)
1265 {
1266     struct stv *state = fe->demodulator_priv;
1267 
1268     state->base->count--;
1269     if (state->base->count == 0) {
1270         list_del(&state->base->stvlist);
1271         kfree(state->base);
1272     }
1273     kfree(state);
1274 }
1275 
1276 static int set_parameters(struct dvb_frontend *fe)
1277 {
1278     int stat = 0;
1279     struct stv *state = fe->demodulator_priv;
1280     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1281 
1282     stop(state);
1283     if (fe->ops.tuner_ops.set_params)
1284         fe->ops.tuner_ops.set_params(fe);
1285     state->symbol_rate = p->symbol_rate;
1286     stat = start(state, p);
1287     return stat;
1288 }
1289 
1290 static int manage_matype_info(struct stv *state)
1291 {
1292     if (!state->started)
1293         return -EINVAL;
1294     if (state->receive_mode == RCVMODE_DVBS2) {
1295         u8 bbheader[2];
1296 
1297         read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff,
1298               bbheader, 2);
1299         state->feroll_off =
1300             (enum fe_stv0910_roll_off)(bbheader[0] & 0x03);
1301         state->is_vcm = (bbheader[0] & 0x10) == 0;
1302         state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0;
1303     } else if (state->receive_mode == RCVMODE_DVBS) {
1304         state->is_vcm = 0;
1305         state->is_standard_broadcast = 1;
1306         state->feroll_off = FE_SAT_35;
1307     }
1308     return 0;
1309 }
1310 
1311 static int read_snr(struct dvb_frontend *fe)
1312 {
1313     struct stv *state = fe->demodulator_priv;
1314     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1315     s32 snrval;
1316 
1317     if (!get_signal_to_noise(state, &snrval)) {
1318         p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1319         p->cnr.stat[0].svalue = 100 * snrval; /* fix scale */
1320     } else {
1321         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1322     }
1323 
1324     return 0;
1325 }
1326 
1327 static int read_ber(struct dvb_frontend *fe)
1328 {
1329     struct stv *state = fe->demodulator_priv;
1330     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1331     u32 n, d;
1332 
1333     get_bit_error_rate(state, &n, &d);
1334 
1335     p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1336     p->pre_bit_error.stat[0].uvalue = n;
1337     p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1338     p->pre_bit_count.stat[0].uvalue = d;
1339 
1340     return 0;
1341 }
1342 
1343 static void read_signal_strength(struct dvb_frontend *fe)
1344 {
1345     struct stv *state = fe->demodulator_priv;
1346     struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
1347     u8 reg[2];
1348     u16 agc;
1349     s32 padc, power = 0;
1350     int i;
1351 
1352     read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2);
1353 
1354     agc = (((u32)reg[0]) << 8) | reg[1];
1355 
1356     for (i = 0; i < 5; i += 1) {
1357         read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2);
1358         power += (u32)reg[0] * (u32)reg[0]
1359             + (u32)reg[1] * (u32)reg[1];
1360         usleep_range(3000, 4000);
1361     }
1362     power /= 5;
1363 
1364     padc = table_lookup(padc_lookup, ARRAY_SIZE(padc_lookup), power) + 352;
1365 
1366     p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1367     p->strength.stat[0].svalue = (padc - agc);
1368 }
1369 
1370 static int read_status(struct dvb_frontend *fe, enum fe_status *status)
1371 {
1372     struct stv *state = fe->demodulator_priv;
1373     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1374     u8 dmd_state = 0;
1375     u8 dstatus  = 0;
1376     enum receive_mode cur_receive_mode = RCVMODE_NONE;
1377     u32 feclock = 0;
1378 
1379     *status = 0;
1380 
1381     read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state);
1382 
1383     if (dmd_state & 0x40) {
1384         read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus);
1385         if (dstatus & 0x08)
1386             cur_receive_mode = (dmd_state & 0x20) ?
1387                 RCVMODE_DVBS : RCVMODE_DVBS2;
1388     }
1389     if (cur_receive_mode == RCVMODE_NONE) {
1390         set_vth(state);
1391 
1392         /* reset signal statistics */
1393         p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1394         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1395         p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1396         p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1397 
1398         return 0;
1399     }
1400 
1401     *status |= (FE_HAS_SIGNAL
1402         | FE_HAS_CARRIER
1403         | FE_HAS_VITERBI
1404         | FE_HAS_SYNC);
1405 
1406     if (state->receive_mode == RCVMODE_NONE) {
1407         state->receive_mode = cur_receive_mode;
1408         state->demod_lock_time = jiffies;
1409         state->first_time_lock = 1;
1410 
1411         get_signal_parameters(state);
1412         tracking_optimization(state);
1413 
1414         write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1415               state->tscfgh);
1416         usleep_range(3000, 4000);
1417         write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1418               state->tscfgh | 0x01);
1419         write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,
1420               state->tscfgh);
1421     }
1422     if (dmd_state & 0x40) {
1423         if (state->receive_mode == RCVMODE_DVBS2) {
1424             u8 pdelstatus;
1425 
1426             read_reg(state,
1427                  RSTV0910_P2_PDELSTATUS1 + state->regoff,
1428                  &pdelstatus);
1429             feclock = (pdelstatus & 0x02) != 0;
1430         } else {
1431             u8 vstatus;
1432 
1433             read_reg(state,
1434                  RSTV0910_P2_VSTATUSVIT + state->regoff,
1435                  &vstatus);
1436             feclock = (vstatus & 0x08) != 0;
1437         }
1438     }
1439 
1440     if (feclock) {
1441         *status |= FE_HAS_LOCK;
1442 
1443         if (state->first_time_lock) {
1444             u8 tmp;
1445 
1446             state->first_time_lock = 0;
1447 
1448             manage_matype_info(state);
1449 
1450             if (state->receive_mode == RCVMODE_DVBS2) {
1451                 /*
1452                  * FSTV0910_P2_MANUALSX_ROLLOFF,
1453                  * FSTV0910_P2_MANUALS2_ROLLOFF = 0
1454                  */
1455                 state->demod_bits &= ~0x84;
1456                 write_reg(state,
1457                       RSTV0910_P2_DEMOD + state->regoff,
1458                       state->demod_bits);
1459                 read_reg(state,
1460                      RSTV0910_P2_PDELCTRL2 + state->regoff,
1461                      &tmp);
1462                 /* reset DVBS2 packet delinator error counter */
1463                 tmp |= 0x40;
1464                 write_reg(state,
1465                       RSTV0910_P2_PDELCTRL2 + state->regoff,
1466                       tmp);
1467                 /* reset DVBS2 packet delinator error counter */
1468                 tmp &= ~0x40;
1469                 write_reg(state,
1470                       RSTV0910_P2_PDELCTRL2 + state->regoff,
1471                       tmp);
1472 
1473                 state->berscale = 2;
1474                 state->last_bernumerator = 0;
1475                 state->last_berdenominator = 1;
1476                 /* force to PRE BCH Rate */
1477                 write_reg(state,
1478                       RSTV0910_P2_ERRCTRL1 + state->regoff,
1479                       BER_SRC_S2 | state->berscale);
1480             } else {
1481                 state->berscale = 2;
1482                 state->last_bernumerator = 0;
1483                 state->last_berdenominator = 1;
1484                 /* force to PRE RS Rate */
1485                 write_reg(state,
1486                       RSTV0910_P2_ERRCTRL1 + state->regoff,
1487                       BER_SRC_S | state->berscale);
1488             }
1489             /* Reset the Total packet counter */
1490             write_reg(state,
1491                   RSTV0910_P2_FBERCPT4 + state->regoff, 0x00);
1492             /*
1493              * Reset the packet Error counter2 (and Set it to
1494              * infinite error count mode)
1495              */
1496             write_reg(state,
1497                   RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1);
1498 
1499             set_vth_default(state);
1500             if (state->receive_mode == RCVMODE_DVBS)
1501                 enable_puncture_rate(state,
1502                              state->puncture_rate);
1503         }
1504 
1505         /* Use highest signaled ModCod for quality */
1506         if (state->is_vcm) {
1507             u8 tmp;
1508             enum fe_stv0910_mod_cod mod_cod;
1509 
1510             read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff,
1511                  &tmp);
1512             mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);
1513 
1514             if (mod_cod > state->mod_cod)
1515                 state->mod_cod = mod_cod;
1516         }
1517     }
1518 
1519     /* read signal statistics */
1520 
1521     /* read signal strength */
1522     read_signal_strength(fe);
1523 
1524     /* read carrier/noise on FE_HAS_CARRIER */
1525     if (*status & FE_HAS_CARRIER)
1526         read_snr(fe);
1527     else
1528         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1529 
1530     /* read ber */
1531     if (*status & FE_HAS_VITERBI) {
1532         read_ber(fe);
1533     } else {
1534         p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1535         p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1536     }
1537 
1538     return 0;
1539 }
1540 
1541 static int get_frontend(struct dvb_frontend *fe,
1542             struct dtv_frontend_properties *p)
1543 {
1544     struct stv *state = fe->demodulator_priv;
1545     u8 tmp;
1546     u32 symbolrate;
1547 
1548     if (state->receive_mode == RCVMODE_DVBS2) {
1549         u32 mc;
1550         const enum fe_modulation modcod2mod[0x20] = {
1551             QPSK, QPSK, QPSK, QPSK,
1552             QPSK, QPSK, QPSK, QPSK,
1553             QPSK, QPSK, QPSK, QPSK,
1554             PSK_8, PSK_8, PSK_8, PSK_8,
1555             PSK_8, PSK_8, APSK_16, APSK_16,
1556             APSK_16, APSK_16, APSK_16, APSK_16,
1557             APSK_32, APSK_32, APSK_32, APSK_32,
1558             APSK_32,
1559         };
1560         const enum fe_code_rate modcod2fec[0x20] = {
1561             FEC_NONE, FEC_NONE, FEC_NONE, FEC_2_5,
1562             FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4,
1563             FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
1564             FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6,
1565             FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4,
1566             FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,
1567             FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9,
1568             FEC_9_10
1569         };
1570         read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);
1571         mc = ((tmp & 0x7c) >> 2);
1572         p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF;
1573         p->modulation = modcod2mod[mc];
1574         p->fec_inner = modcod2fec[mc];
1575     } else if (state->receive_mode == RCVMODE_DVBS) {
1576         read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);
1577         switch (tmp & 0x1F) {
1578         case 0x0d:
1579             p->fec_inner = FEC_1_2;
1580             break;
1581         case 0x12:
1582             p->fec_inner = FEC_2_3;
1583             break;
1584         case 0x15:
1585             p->fec_inner = FEC_3_4;
1586             break;
1587         case 0x18:
1588             p->fec_inner = FEC_5_6;
1589             break;
1590         case 0x1a:
1591             p->fec_inner = FEC_7_8;
1592             break;
1593         default:
1594             p->fec_inner = FEC_NONE;
1595             break;
1596         }
1597         p->rolloff = ROLLOFF_35;
1598     }
1599 
1600     if (state->receive_mode != RCVMODE_NONE) {
1601         get_cur_symbol_rate(state, &symbolrate);
1602         p->symbol_rate = symbolrate;
1603     }
1604     return 0;
1605 }
1606 
1607 static int tune(struct dvb_frontend *fe, bool re_tune,
1608         unsigned int mode_flags,
1609         unsigned int *delay, enum fe_status *status)
1610 {
1611     struct stv *state = fe->demodulator_priv;
1612     int r;
1613 
1614     if (re_tune) {
1615         r = set_parameters(fe);
1616         if (r)
1617             return r;
1618         state->tune_time = jiffies;
1619     }
1620 
1621     r = read_status(fe, status);
1622     if (r)
1623         return r;
1624 
1625     if (*status & FE_HAS_LOCK)
1626         return 0;
1627     *delay = HZ;
1628 
1629     return 0;
1630 }
1631 
1632 static enum dvbfe_algo get_algo(struct dvb_frontend *fe)
1633 {
1634     return DVBFE_ALGO_HW;
1635 }
1636 
1637 static int set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
1638 {
1639     struct stv *state = fe->demodulator_priv;
1640     u16 offs = state->nr ? 0x40 : 0;
1641 
1642     switch (tone) {
1643     case SEC_TONE_ON:
1644         return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38);
1645     case SEC_TONE_OFF:
1646         return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a);
1647     default:
1648         break;
1649     }
1650     return -EINVAL;
1651 }
1652 
1653 static int wait_dis(struct stv *state, u8 flag, u8 val)
1654 {
1655     int i;
1656     u8 stat;
1657     u16 offs = state->nr ? 0x40 : 0;
1658 
1659     for (i = 0; i < 10; i++) {
1660         read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, &stat);
1661         if ((stat & flag) == val)
1662             return 0;
1663         usleep_range(10000, 11000);
1664     }
1665     return -ETIMEDOUT;
1666 }
1667 
1668 static int send_master_cmd(struct dvb_frontend *fe,
1669                struct dvb_diseqc_master_cmd *cmd)
1670 {
1671     struct stv *state = fe->demodulator_priv;
1672     int i;
1673 
1674     SET_FIELD(DISEQC_MODE, 2);
1675     SET_FIELD(DIS_PRECHARGE, 1);
1676     for (i = 0; i < cmd->msg_len; i++) {
1677         wait_dis(state, 0x40, 0x00);
1678         SET_REG(DISTXFIFO, cmd->msg[i]);
1679     }
1680     SET_FIELD(DIS_PRECHARGE, 0);
1681     wait_dis(state, 0x20, 0x20);
1682     return 0;
1683 }
1684 
1685 static int send_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst)
1686 {
1687     struct stv *state = fe->demodulator_priv;
1688     u8 value;
1689 
1690     if (burst == SEC_MINI_A) {
1691         SET_FIELD(DISEQC_MODE, 3);
1692         value = 0x00;
1693     } else {
1694         SET_FIELD(DISEQC_MODE, 2);
1695         value = 0xFF;
1696     }
1697 
1698     SET_FIELD(DIS_PRECHARGE, 1);
1699     wait_dis(state, 0x40, 0x00);
1700     SET_REG(DISTXFIFO, value);
1701     SET_FIELD(DIS_PRECHARGE, 0);
1702     wait_dis(state, 0x20, 0x20);
1703 
1704     return 0;
1705 }
1706 
1707 static int sleep(struct dvb_frontend *fe)
1708 {
1709     struct stv *state = fe->demodulator_priv;
1710 
1711     stop(state);
1712     return 0;
1713 }
1714 
1715 static const struct dvb_frontend_ops stv0910_ops = {
1716     .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
1717     .info = {
1718         .name           = "ST STV0910",
1719         .frequency_min_hz   =  950 * MHz,
1720         .frequency_max_hz   = 2150 * MHz,
1721         .symbol_rate_min    = 100000,
1722         .symbol_rate_max    = 70000000,
1723         .caps           = FE_CAN_INVERSION_AUTO |
1724                       FE_CAN_FEC_AUTO       |
1725                       FE_CAN_QPSK           |
1726                       FE_CAN_2G_MODULATION  |
1727                       FE_CAN_MULTISTREAM
1728     },
1729     .sleep              = sleep,
1730     .release            = release,
1731     .i2c_gate_ctrl          = gate_ctrl,
1732     .set_frontend           = set_parameters,
1733     .get_frontend_algo      = get_algo,
1734     .get_frontend           = get_frontend,
1735     .tune               = tune,
1736     .read_status            = read_status,
1737     .set_tone           = set_tone,
1738 
1739     .diseqc_send_master_cmd     = send_master_cmd,
1740     .diseqc_send_burst      = send_burst,
1741 };
1742 
1743 static struct stv_base *match_base(struct i2c_adapter *i2c, u8 adr)
1744 {
1745     struct stv_base *p;
1746 
1747     list_for_each_entry(p, &stvlist, stvlist)
1748         if (p->i2c == i2c && p->adr == adr)
1749             return p;
1750     return NULL;
1751 }
1752 
1753 static void stv0910_init_stats(struct stv *state)
1754 {
1755     struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
1756 
1757     p->strength.len = 1;
1758     p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1759     p->cnr.len = 1;
1760     p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1761     p->pre_bit_error.len = 1;
1762     p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1763     p->pre_bit_count.len = 1;
1764     p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1765 }
1766 
1767 struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c,
1768                     struct stv0910_cfg *cfg,
1769                     int nr)
1770 {
1771     struct stv *state;
1772     struct stv_base *base;
1773 
1774     state = kzalloc(sizeof(*state), GFP_KERNEL);
1775     if (!state)
1776         return NULL;
1777 
1778     state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40);
1779     state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00;
1780     state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4);
1781     /* use safe tsspeed value if unspecified through stv0910_cfg */
1782     state->tsspeed = (cfg->tsspeed ? cfg->tsspeed : 0x28);
1783     state->nr = nr;
1784     state->regoff = state->nr ? 0 : 0x200;
1785     state->search_range = 16000000;
1786     state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */
1787     state->receive_mode = RCVMODE_NONE;
1788     state->cur_scrambling_code = (~0U);
1789     state->single = cfg->single ? 1 : 0;
1790 
1791     base = match_base(i2c, cfg->adr);
1792     if (base) {
1793         base->count++;
1794         state->base = base;
1795     } else {
1796         base = kzalloc(sizeof(*base), GFP_KERNEL);
1797         if (!base)
1798             goto fail;
1799         base->i2c = i2c;
1800         base->adr = cfg->adr;
1801         base->count = 1;
1802         base->extclk = cfg->clk ? cfg->clk : 30000000;
1803 
1804         mutex_init(&base->i2c_lock);
1805         mutex_init(&base->reg_lock);
1806         state->base = base;
1807         if (probe(state) < 0) {
1808             dev_info(&i2c->dev, "No demod found at adr %02X on %s\n",
1809                  cfg->adr, dev_name(&i2c->dev));
1810             kfree(base);
1811             goto fail;
1812         }
1813         list_add(&base->stvlist, &stvlist);
1814     }
1815     state->fe.ops = stv0910_ops;
1816     state->fe.demodulator_priv = state;
1817     state->nr = nr;
1818 
1819     dev_info(&i2c->dev, "%s demod found at adr %02X on %s\n",
1820          state->fe.ops.info.name, cfg->adr, dev_name(&i2c->dev));
1821 
1822     stv0910_init_stats(state);
1823 
1824     return &state->fe;
1825 
1826 fail:
1827     kfree(state);
1828     return NULL;
1829 }
1830 EXPORT_SYMBOL_GPL(stv0910_attach);
1831 
1832 MODULE_DESCRIPTION("ST STV0910 multistandard frontend driver");
1833 MODULE_AUTHOR("Ralph and Marcus Metzler, Manfred Voelkel");
1834 MODULE_LICENSE("GPL v2");
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