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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * stv0900_sw.c
0004  *
0005  * Driver for ST STV0900 satellite demodulator IC.
0006  *
0007  * Copyright (C) ST Microelectronics.
0008  * Copyright (C) 2009 NetUP Inc.
0009  * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
0010  */
0011 
0012 #include "stv0900.h"
0013 #include "stv0900_reg.h"
0014 #include "stv0900_priv.h"
0015 
0016 s32 shiftx(s32 x, int demod, s32 shift)
0017 {
0018     if (demod == 1)
0019         return x - shift;
0020 
0021     return x;
0022 }
0023 
0024 int stv0900_check_signal_presence(struct stv0900_internal *intp,
0025                     enum fe_stv0900_demod_num demod)
0026 {
0027     s32 carr_offset,
0028         agc2_integr,
0029         max_carrier;
0030 
0031     int no_signal = FALSE;
0032 
0033     carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
0034                     | stv0900_read_reg(intp, CFR1);
0035     carr_offset = ge2comp(carr_offset, 16);
0036     agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
0037                     | stv0900_read_reg(intp, AGC2I0);
0038     max_carrier = intp->srch_range[demod] / 1000;
0039 
0040     max_carrier += (max_carrier / 10);
0041     max_carrier = 65536 * (max_carrier / 2);
0042     max_carrier /= intp->mclk / 1000;
0043     if (max_carrier > 0x4000)
0044         max_carrier = 0x4000;
0045 
0046     if ((agc2_integr > 0x2000)
0047             || (carr_offset > (2 * max_carrier))
0048             || (carr_offset < (-2 * max_carrier)))
0049         no_signal = TRUE;
0050 
0051     return no_signal;
0052 }
0053 
0054 static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
0055                 s32 *frequency_inc, s32 *sw_timeout,
0056                 s32 *steps,
0057                 enum fe_stv0900_demod_num demod)
0058 {
0059     s32 timeout, freq_inc, max_steps, srate, max_carrier;
0060 
0061     enum fe_stv0900_search_standard standard;
0062 
0063     srate = intp->symbol_rate[demod];
0064     max_carrier = intp->srch_range[demod] / 1000;
0065     max_carrier += max_carrier / 10;
0066     standard = intp->srch_standard[demod];
0067 
0068     max_carrier = 65536 * (max_carrier / 2);
0069     max_carrier /= intp->mclk / 1000;
0070 
0071     if (max_carrier > 0x4000)
0072         max_carrier = 0x4000;
0073 
0074     freq_inc = srate;
0075     freq_inc /= intp->mclk >> 10;
0076     freq_inc = freq_inc << 6;
0077 
0078     switch (standard) {
0079     case STV0900_SEARCH_DVBS1:
0080     case STV0900_SEARCH_DSS:
0081         freq_inc *= 3;
0082         timeout = 20;
0083         break;
0084     case STV0900_SEARCH_DVBS2:
0085         freq_inc *= 4;
0086         timeout = 25;
0087         break;
0088     case STV0900_AUTO_SEARCH:
0089     default:
0090         freq_inc *= 3;
0091         timeout = 25;
0092         break;
0093     }
0094 
0095     freq_inc /= 100;
0096 
0097     if ((freq_inc > max_carrier) || (freq_inc < 0))
0098         freq_inc = max_carrier / 2;
0099 
0100     timeout *= 27500;
0101 
0102     if (srate > 0)
0103         timeout /= srate / 1000;
0104 
0105     if ((timeout > 100) || (timeout < 0))
0106         timeout = 100;
0107 
0108     max_steps = (max_carrier / freq_inc) + 1;
0109 
0110     if ((max_steps > 100) || (max_steps < 0)) {
0111         max_steps =  100;
0112         freq_inc = max_carrier / max_steps;
0113     }
0114 
0115     *frequency_inc = freq_inc;
0116     *sw_timeout = timeout;
0117     *steps = max_steps;
0118 
0119 }
0120 
0121 static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
0122                 s32 FreqIncr, s32 Timeout, int zigzag,
0123                 s32 MaxStep, enum fe_stv0900_demod_num demod)
0124 {
0125     int no_signal,
0126         lock = FALSE;
0127     s32 stepCpt,
0128         freqOffset,
0129         max_carrier;
0130 
0131     max_carrier = intp->srch_range[demod] / 1000;
0132     max_carrier += (max_carrier / 10);
0133 
0134     max_carrier = 65536 * (max_carrier / 2);
0135     max_carrier /= intp->mclk / 1000;
0136 
0137     if (max_carrier > 0x4000)
0138         max_carrier = 0x4000;
0139 
0140     if (zigzag == TRUE)
0141         freqOffset = 0;
0142     else
0143         freqOffset = -max_carrier + FreqIncr;
0144 
0145     stepCpt = 0;
0146 
0147     do {
0148         stv0900_write_reg(intp, DMDISTATE, 0x1c);
0149         stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
0150         stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
0151         stv0900_write_reg(intp, DMDISTATE, 0x18);
0152         stv0900_write_bits(intp, ALGOSWRST, 1);
0153 
0154         if (intp->chip_id == 0x12) {
0155             stv0900_write_bits(intp, RST_HWARE, 1);
0156             stv0900_write_bits(intp, RST_HWARE, 0);
0157         }
0158 
0159         if (zigzag == TRUE) {
0160             if (freqOffset >= 0)
0161                 freqOffset = -freqOffset - 2 * FreqIncr;
0162             else
0163                 freqOffset = -freqOffset;
0164         } else
0165             freqOffset += + 2 * FreqIncr;
0166 
0167         stepCpt++;
0168         lock = stv0900_get_demod_lock(intp, demod, Timeout);
0169         no_signal = stv0900_check_signal_presence(intp, demod);
0170 
0171     } while ((lock == FALSE)
0172             && (no_signal == FALSE)
0173             && ((freqOffset - FreqIncr) <  max_carrier)
0174             && ((freqOffset + FreqIncr) > -max_carrier)
0175             && (stepCpt < MaxStep));
0176 
0177     stv0900_write_bits(intp, ALGOSWRST, 0);
0178 
0179     return lock;
0180 }
0181 
0182 static int stv0900_sw_algo(struct stv0900_internal *intp,
0183                 enum fe_stv0900_demod_num demod)
0184 {
0185     int lock = FALSE,
0186         no_signal,
0187         zigzag;
0188     s32 s2fw,
0189         fqc_inc,
0190         sft_stp_tout,
0191         trial_cntr,
0192         max_steps;
0193 
0194     stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
0195                     &max_steps, demod);
0196     switch (intp->srch_standard[demod]) {
0197     case STV0900_SEARCH_DVBS1:
0198     case STV0900_SEARCH_DSS:
0199         if (intp->chip_id >= 0x20)
0200             stv0900_write_reg(intp, CARFREQ, 0x3b);
0201         else
0202             stv0900_write_reg(intp, CARFREQ, 0xef);
0203 
0204         stv0900_write_reg(intp, DMDCFGMD, 0x49);
0205         zigzag = FALSE;
0206         break;
0207     case STV0900_SEARCH_DVBS2:
0208         if (intp->chip_id >= 0x20)
0209             stv0900_write_reg(intp, CORRELABS, 0x79);
0210         else
0211             stv0900_write_reg(intp, CORRELABS, 0x68);
0212 
0213         stv0900_write_reg(intp, DMDCFGMD, 0x89);
0214 
0215         zigzag = TRUE;
0216         break;
0217     case STV0900_AUTO_SEARCH:
0218     default:
0219         if (intp->chip_id >= 0x20) {
0220             stv0900_write_reg(intp, CARFREQ, 0x3b);
0221             stv0900_write_reg(intp, CORRELABS, 0x79);
0222         } else {
0223             stv0900_write_reg(intp, CARFREQ, 0xef);
0224             stv0900_write_reg(intp, CORRELABS, 0x68);
0225         }
0226 
0227         stv0900_write_reg(intp, DMDCFGMD, 0xc9);
0228         zigzag = FALSE;
0229         break;
0230     }
0231 
0232     trial_cntr = 0;
0233     do {
0234         lock = stv0900_search_carr_sw_loop(intp,
0235                         fqc_inc,
0236                         sft_stp_tout,
0237                         zigzag,
0238                         max_steps,
0239                         demod);
0240         no_signal = stv0900_check_signal_presence(intp, demod);
0241         trial_cntr++;
0242         if ((lock == TRUE)
0243                 || (no_signal == TRUE)
0244                 || (trial_cntr == 2)) {
0245 
0246             if (intp->chip_id >= 0x20) {
0247                 stv0900_write_reg(intp, CARFREQ, 0x49);
0248                 stv0900_write_reg(intp, CORRELABS, 0x9e);
0249             } else {
0250                 stv0900_write_reg(intp, CARFREQ, 0xed);
0251                 stv0900_write_reg(intp, CORRELABS, 0x88);
0252             }
0253 
0254             if ((stv0900_get_bits(intp, HEADER_MODE) ==
0255                         STV0900_DVBS2_FOUND) &&
0256                             (lock == TRUE)) {
0257                 msleep(sft_stp_tout);
0258                 s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
0259 
0260                 if (s2fw < 0xd) {
0261                     msleep(sft_stp_tout);
0262                     s2fw = stv0900_get_bits(intp,
0263                                 FLYWHEEL_CPT);
0264                 }
0265 
0266                 if (s2fw < 0xd) {
0267                     lock = FALSE;
0268 
0269                     if (trial_cntr < 2) {
0270                         if (intp->chip_id >= 0x20)
0271                             stv0900_write_reg(intp,
0272                                 CORRELABS,
0273                                 0x79);
0274                         else
0275                             stv0900_write_reg(intp,
0276                                 CORRELABS,
0277                                 0x68);
0278 
0279                         stv0900_write_reg(intp,
0280                                 DMDCFGMD,
0281                                 0x89);
0282                     }
0283                 }
0284             }
0285         }
0286 
0287     } while ((lock == FALSE)
0288         && (trial_cntr < 2)
0289         && (no_signal == FALSE));
0290 
0291     return lock;
0292 }
0293 
0294 static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
0295                     u32 mclk,
0296                     enum fe_stv0900_demod_num demod)
0297 {
0298     s32 rem1, rem2, intval1, intval2, srate;
0299 
0300     srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
0301         (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
0302         (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
0303         (stv0900_get_bits(intp, SYMB_FREQ0));
0304     dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
0305         srate, stv0900_get_bits(intp, SYMB_FREQ0),
0306         stv0900_get_bits(intp, SYMB_FREQ1),
0307         stv0900_get_bits(intp, SYMB_FREQ2),
0308         stv0900_get_bits(intp, SYMB_FREQ3));
0309 
0310     intval1 = (mclk) >> 16;
0311     intval2 = (srate) >> 16;
0312 
0313     rem1 = (mclk) % 0x10000;
0314     rem2 = (srate) % 0x10000;
0315     srate = (intval1 * intval2) +
0316         ((intval1 * rem2) >> 16) +
0317         ((intval2 * rem1) >> 16);
0318 
0319     return srate;
0320 }
0321 
0322 static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
0323                     u32 mclk, u32 srate,
0324                     enum fe_stv0900_demod_num demod)
0325 {
0326     u32 symb;
0327 
0328     dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
0329                             srate, demod);
0330 
0331     if (srate > 60000000) {
0332         symb = srate << 4;
0333         symb /= (mclk >> 12);
0334     } else if (srate > 6000000) {
0335         symb = srate << 6;
0336         symb /= (mclk >> 10);
0337     } else {
0338         symb = srate << 9;
0339         symb /= (mclk >> 7);
0340     }
0341 
0342     stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
0343     stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
0344 }
0345 
0346 static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
0347                     u32 mclk, u32 srate,
0348                     enum fe_stv0900_demod_num demod)
0349 {
0350     u32 symb;
0351 
0352     srate = 105 * (srate / 100);
0353 
0354     if (srate > 60000000) {
0355         symb = srate << 4;
0356         symb /= (mclk >> 12);
0357     } else if (srate > 6000000) {
0358         symb = srate << 6;
0359         symb /= (mclk >> 10);
0360     } else {
0361         symb = srate << 9;
0362         symb /= (mclk >> 7);
0363     }
0364 
0365     if (symb < 0x7fff) {
0366         stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
0367         stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
0368     } else {
0369         stv0900_write_reg(intp, SFRUP1, 0x7f);
0370         stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
0371     }
0372 }
0373 
0374 static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
0375                     u32 mclk, u32 srate,
0376                     enum fe_stv0900_demod_num demod)
0377 {
0378     u32 symb;
0379 
0380     srate = 95 * (srate / 100);
0381     if (srate > 60000000) {
0382         symb = srate << 4;
0383         symb /= (mclk >> 12);
0384 
0385     } else if (srate > 6000000) {
0386         symb = srate << 6;
0387         symb /= (mclk >> 10);
0388 
0389     } else {
0390         symb = srate << 9;
0391         symb /= (mclk >> 7);
0392     }
0393 
0394     stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
0395     stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
0396 }
0397 
0398 static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
0399                     u32 srate,
0400                     enum fe_stv0900_demod_num demod)
0401 {
0402     s32 timingoffset;
0403 
0404 
0405     timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
0406                (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
0407                (stv0900_read_reg(intp, TMGREG2 + 2));
0408 
0409     timingoffset = ge2comp(timingoffset, 24);
0410 
0411 
0412     if (timingoffset == 0)
0413         timingoffset = 1;
0414 
0415     timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
0416     timingoffset /= 320;
0417 
0418     return timingoffset;
0419 }
0420 
0421 static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
0422                     enum fe_stv0900_demod_num demod)
0423 {
0424     s32 rolloff;
0425 
0426     if (intp->chip_id == 0x10) {
0427         stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
0428         rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
0429         stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
0430     } else if (intp->chip_id <= 0x20)
0431         stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
0432     else /* cut 3.0 */
0433         stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
0434 }
0435 
0436 static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
0437 {
0438     u32 rolloff;
0439 
0440     switch (ro) {
0441     case STV0900_20:
0442         rolloff = 20;
0443         break;
0444     case STV0900_25:
0445         rolloff = 25;
0446         break;
0447     case STV0900_35:
0448     default:
0449         rolloff = 35;
0450         break;
0451     }
0452 
0453     return srate  + (srate * rolloff) / 100;
0454 }
0455 
0456 static int stv0900_check_timing_lock(struct stv0900_internal *intp,
0457                 enum fe_stv0900_demod_num demod)
0458 {
0459     int timingLock = FALSE;
0460     s32 i,
0461         timingcpt = 0;
0462     u8  car_freq,
0463         tmg_th_high,
0464         tmg_th_low;
0465 
0466     car_freq = stv0900_read_reg(intp, CARFREQ);
0467     tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
0468     tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
0469     stv0900_write_reg(intp, TMGTHRISE, 0x20);
0470     stv0900_write_reg(intp, TMGTHFALL, 0x0);
0471     stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
0472     stv0900_write_reg(intp, RTC, 0x80);
0473     stv0900_write_reg(intp, RTCS2, 0x40);
0474     stv0900_write_reg(intp, CARFREQ, 0x0);
0475     stv0900_write_reg(intp, CFRINIT1, 0x0);
0476     stv0900_write_reg(intp, CFRINIT0, 0x0);
0477     stv0900_write_reg(intp, AGC2REF, 0x65);
0478     stv0900_write_reg(intp, DMDISTATE, 0x18);
0479     msleep(7);
0480 
0481     for (i = 0; i < 10; i++) {
0482         if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
0483             timingcpt++;
0484 
0485         msleep(1);
0486     }
0487 
0488     if (timingcpt >= 3)
0489         timingLock = TRUE;
0490 
0491     stv0900_write_reg(intp, AGC2REF, 0x38);
0492     stv0900_write_reg(intp, RTC, 0x88);
0493     stv0900_write_reg(intp, RTCS2, 0x68);
0494     stv0900_write_reg(intp, CARFREQ, car_freq);
0495     stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
0496     stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
0497 
0498     return  timingLock;
0499 }
0500 
0501 static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
0502                     s32 demod_timeout)
0503 {
0504     struct stv0900_state *state = fe->demodulator_priv;
0505     struct stv0900_internal *intp = state->internal;
0506     enum fe_stv0900_demod_num demod = state->demod;
0507     int lock = FALSE,
0508         d = demod;
0509     s32 srate,
0510         search_range,
0511         locktimeout,
0512         currier_step,
0513         nb_steps,
0514         current_step,
0515         direction,
0516         tuner_freq,
0517         timeout,
0518         freq;
0519 
0520     srate = intp->symbol_rate[d];
0521     search_range = intp->srch_range[d];
0522 
0523     if (srate >= 10000000)
0524         locktimeout = demod_timeout / 3;
0525     else
0526         locktimeout = demod_timeout / 2;
0527 
0528     lock = stv0900_get_demod_lock(intp, d, locktimeout);
0529 
0530     if (lock != FALSE)
0531         return lock;
0532 
0533     if (srate >= 10000000) {
0534         if (stv0900_check_timing_lock(intp, d) == TRUE) {
0535             stv0900_write_reg(intp, DMDISTATE, 0x1f);
0536             stv0900_write_reg(intp, DMDISTATE, 0x15);
0537             lock = stv0900_get_demod_lock(intp, d, demod_timeout);
0538         } else
0539             lock = FALSE;
0540 
0541         return lock;
0542     }
0543 
0544     if (intp->chip_id <= 0x20) {
0545         if (srate <= 1000000)
0546             currier_step = 500;
0547         else if (srate <= 4000000)
0548             currier_step = 1000;
0549         else if (srate <= 7000000)
0550             currier_step = 2000;
0551         else if (srate <= 10000000)
0552             currier_step = 3000;
0553         else
0554             currier_step = 5000;
0555 
0556         if (srate >= 2000000) {
0557             timeout = (demod_timeout / 3);
0558             if (timeout > 1000)
0559                 timeout = 1000;
0560         } else
0561             timeout = (demod_timeout / 2);
0562     } else {
0563         /*cut 3.0 */
0564         currier_step = srate / 4000;
0565         timeout = (demod_timeout * 3) / 4;
0566     }
0567 
0568     nb_steps = ((search_range / 1000) / currier_step);
0569 
0570     if ((nb_steps % 2) != 0)
0571         nb_steps += 1;
0572 
0573     if (nb_steps <= 0)
0574         nb_steps = 2;
0575     else if (nb_steps > 12)
0576         nb_steps = 12;
0577 
0578     current_step = 1;
0579     direction = 1;
0580 
0581     if (intp->chip_id <= 0x20) {
0582         tuner_freq = intp->freq[d];
0583         intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
0584                 intp->rolloff) + intp->symbol_rate[d];
0585     } else
0586         tuner_freq = 0;
0587 
0588     while ((current_step <= nb_steps) && (lock == FALSE)) {
0589         if (direction > 0)
0590             tuner_freq += (current_step * currier_step);
0591         else
0592             tuner_freq -= (current_step * currier_step);
0593 
0594         if (intp->chip_id <= 0x20) {
0595             if (intp->tuner_type[d] == 3)
0596                 stv0900_set_tuner_auto(intp, tuner_freq,
0597                         intp->bw[d], demod);
0598             else
0599                 stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
0600 
0601             stv0900_write_reg(intp, DMDISTATE, 0x1c);
0602             stv0900_write_reg(intp, CFRINIT1, 0);
0603             stv0900_write_reg(intp, CFRINIT0, 0);
0604             stv0900_write_reg(intp, DMDISTATE, 0x1f);
0605             stv0900_write_reg(intp, DMDISTATE, 0x15);
0606         } else {
0607             stv0900_write_reg(intp, DMDISTATE, 0x1c);
0608             freq = (tuner_freq * 65536) / (intp->mclk / 1000);
0609             stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
0610             stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
0611             stv0900_write_reg(intp, DMDISTATE, 0x1f);
0612             stv0900_write_reg(intp, DMDISTATE, 0x05);
0613         }
0614 
0615         lock = stv0900_get_demod_lock(intp, d, timeout);
0616         direction *= -1;
0617         current_step++;
0618     }
0619 
0620     return  lock;
0621 }
0622 
0623 static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
0624                     s32 srate,
0625                     enum fe_stv0900_search_algo algo)
0626 {
0627     switch (algo) {
0628     case STV0900_BLIND_SEARCH:
0629         if (srate <= 1500000) {
0630             (*demod_timeout) = 1500;
0631             (*fec_timeout) = 400;
0632         } else if (srate <= 5000000) {
0633             (*demod_timeout) = 1000;
0634             (*fec_timeout) = 300;
0635         } else {
0636             (*demod_timeout) = 700;
0637             (*fec_timeout) = 100;
0638         }
0639 
0640         break;
0641     case STV0900_COLD_START:
0642     case STV0900_WARM_START:
0643     default:
0644         if (srate <= 1000000) {
0645             (*demod_timeout) = 3000;
0646             (*fec_timeout) = 1700;
0647         } else if (srate <= 2000000) {
0648             (*demod_timeout) = 2500;
0649             (*fec_timeout) = 1100;
0650         } else if (srate <= 5000000) {
0651             (*demod_timeout) = 1000;
0652             (*fec_timeout) = 550;
0653         } else if (srate <= 10000000) {
0654             (*demod_timeout) = 700;
0655             (*fec_timeout) = 250;
0656         } else if (srate <= 20000000) {
0657             (*demod_timeout) = 400;
0658             (*fec_timeout) = 130;
0659         } else {
0660             (*demod_timeout) = 300;
0661             (*fec_timeout) = 100;
0662         }
0663 
0664         break;
0665 
0666     }
0667 
0668     if (algo == STV0900_WARM_START)
0669         (*demod_timeout) /= 2;
0670 }
0671 
0672 static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
0673                     enum fe_stv0900_demod_num demod)
0674 {
0675 
0676     s32 vth_reg = VTH12;
0677 
0678     dprintk("%s\n", __func__);
0679 
0680     stv0900_write_reg(intp, vth_reg++, 0xd0);
0681     stv0900_write_reg(intp, vth_reg++, 0x7d);
0682     stv0900_write_reg(intp, vth_reg++, 0x53);
0683     stv0900_write_reg(intp, vth_reg++, 0x2f);
0684     stv0900_write_reg(intp, vth_reg++, 0x24);
0685     stv0900_write_reg(intp, vth_reg++, 0x1f);
0686 }
0687 
0688 static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
0689                    enum fe_stv0900_search_standard standard,
0690                    enum fe_stv0900_fec fec,
0691                    enum fe_stv0900_demod_num demod)
0692 {
0693     dprintk("%s: ViterbiStandard = ", __func__);
0694 
0695     switch (standard) {
0696     case STV0900_AUTO_SEARCH:
0697         dprintk("Auto\n");
0698         stv0900_write_reg(intp, FECM, 0x10);
0699         stv0900_write_reg(intp, PRVIT, 0x3f);
0700         break;
0701     case STV0900_SEARCH_DVBS1:
0702         dprintk("DVBS1\n");
0703         stv0900_write_reg(intp, FECM, 0x00);
0704         switch (fec) {
0705         case STV0900_FEC_UNKNOWN:
0706         default:
0707             stv0900_write_reg(intp, PRVIT, 0x2f);
0708             break;
0709         case STV0900_FEC_1_2:
0710             stv0900_write_reg(intp, PRVIT, 0x01);
0711             break;
0712         case STV0900_FEC_2_3:
0713             stv0900_write_reg(intp, PRVIT, 0x02);
0714             break;
0715         case STV0900_FEC_3_4:
0716             stv0900_write_reg(intp, PRVIT, 0x04);
0717             break;
0718         case STV0900_FEC_5_6:
0719             stv0900_write_reg(intp, PRVIT, 0x08);
0720             break;
0721         case STV0900_FEC_7_8:
0722             stv0900_write_reg(intp, PRVIT, 0x20);
0723             break;
0724         }
0725 
0726         break;
0727     case STV0900_SEARCH_DSS:
0728         dprintk("DSS\n");
0729         stv0900_write_reg(intp, FECM, 0x80);
0730         switch (fec) {
0731         case STV0900_FEC_UNKNOWN:
0732         default:
0733             stv0900_write_reg(intp, PRVIT, 0x13);
0734             break;
0735         case STV0900_FEC_1_2:
0736             stv0900_write_reg(intp, PRVIT, 0x01);
0737             break;
0738         case STV0900_FEC_2_3:
0739             stv0900_write_reg(intp, PRVIT, 0x02);
0740             break;
0741         case STV0900_FEC_6_7:
0742             stv0900_write_reg(intp, PRVIT, 0x10);
0743             break;
0744         }
0745         break;
0746     default:
0747         break;
0748     }
0749 }
0750 
0751 static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
0752                         enum fe_stv0900_demod_num demod)
0753 {
0754     enum fe_stv0900_fec prate;
0755     s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
0756 
0757     switch (rate_fld) {
0758     case 13:
0759         prate = STV0900_FEC_1_2;
0760         break;
0761     case 18:
0762         prate = STV0900_FEC_2_3;
0763         break;
0764     case 21:
0765         prate = STV0900_FEC_3_4;
0766         break;
0767     case 24:
0768         prate = STV0900_FEC_5_6;
0769         break;
0770     case 25:
0771         prate = STV0900_FEC_6_7;
0772         break;
0773     case 26:
0774         prate = STV0900_FEC_7_8;
0775         break;
0776     default:
0777         prate = STV0900_FEC_UNKNOWN;
0778         break;
0779     }
0780 
0781     return prate;
0782 }
0783 
0784 static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
0785                     enum fe_stv0900_demod_num demod,
0786                     u32 srate)
0787 {
0788     if (intp->chip_id >= 0x30) {
0789         if (srate >= 15000000) {
0790             stv0900_write_reg(intp, ACLC, 0x2b);
0791             stv0900_write_reg(intp, BCLC, 0x1a);
0792         } else if ((srate >= 7000000) && (15000000 > srate)) {
0793             stv0900_write_reg(intp, ACLC, 0x0c);
0794             stv0900_write_reg(intp, BCLC, 0x1b);
0795         } else if (srate < 7000000) {
0796             stv0900_write_reg(intp, ACLC, 0x2c);
0797             stv0900_write_reg(intp, BCLC, 0x1c);
0798         }
0799 
0800     } else { /*cut 2.0 and 1.x*/
0801         stv0900_write_reg(intp, ACLC, 0x1a);
0802         stv0900_write_reg(intp, BCLC, 0x09);
0803     }
0804 
0805 }
0806 
0807 static void stv0900_track_optimization(struct dvb_frontend *fe)
0808 {
0809     struct stv0900_state *state = fe->demodulator_priv;
0810     struct stv0900_internal *intp = state->internal;
0811     enum fe_stv0900_demod_num demod = state->demod;
0812 
0813     s32 srate,
0814         pilots,
0815         aclc,
0816         freq1,
0817         freq0,
0818         i = 0,
0819         timed,
0820         timef,
0821         blind_tun_sw = 0,
0822         modulation;
0823 
0824     enum fe_stv0900_modcode foundModcod;
0825 
0826     dprintk("%s\n", __func__);
0827 
0828     srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
0829     srate += stv0900_get_timing_offst(intp, srate, demod);
0830 
0831     switch (intp->result[demod].standard) {
0832     case STV0900_DVBS1_STANDARD:
0833     case STV0900_DSS_STANDARD:
0834         dprintk("%s: found DVB-S or DSS\n", __func__);
0835         if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
0836             stv0900_write_bits(intp, DVBS1_ENABLE, 1);
0837             stv0900_write_bits(intp, DVBS2_ENABLE, 0);
0838         }
0839 
0840         stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
0841         stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
0842 
0843         if (intp->chip_id < 0x30) {
0844             stv0900_write_reg(intp, ERRCTRL1, 0x75);
0845             break;
0846         }
0847 
0848         if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
0849             stv0900_write_reg(intp, GAUSSR0, 0x98);
0850             stv0900_write_reg(intp, CCIR0, 0x18);
0851         } else {
0852             stv0900_write_reg(intp, GAUSSR0, 0x18);
0853             stv0900_write_reg(intp, CCIR0, 0x18);
0854         }
0855 
0856         stv0900_write_reg(intp, ERRCTRL1, 0x75);
0857         break;
0858     case STV0900_DVBS2_STANDARD:
0859         dprintk("%s: found DVB-S2\n", __func__);
0860         stv0900_write_bits(intp, DVBS1_ENABLE, 0);
0861         stv0900_write_bits(intp, DVBS2_ENABLE, 1);
0862         stv0900_write_reg(intp, ACLC, 0);
0863         stv0900_write_reg(intp, BCLC, 0);
0864         if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
0865             foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
0866             pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
0867             aclc = stv0900_get_optim_carr_loop(srate,
0868                             foundModcod,
0869                             pilots,
0870                             intp->chip_id);
0871             if (foundModcod <= STV0900_QPSK_910)
0872                 stv0900_write_reg(intp, ACLC2S2Q, aclc);
0873             else if (foundModcod <= STV0900_8PSK_910) {
0874                 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
0875                 stv0900_write_reg(intp, ACLC2S28, aclc);
0876             }
0877 
0878             if ((intp->demod_mode == STV0900_SINGLE) &&
0879                     (foundModcod > STV0900_8PSK_910)) {
0880                 if (foundModcod <= STV0900_16APSK_910) {
0881                     stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
0882                     stv0900_write_reg(intp, ACLC2S216A,
0883                                     aclc);
0884                 } else if (foundModcod <= STV0900_32APSK_910) {
0885                     stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
0886                     stv0900_write_reg(intp, ACLC2S232A,
0887                                     aclc);
0888                 }
0889             }
0890 
0891         } else {
0892             modulation = intp->result[demod].modulation;
0893             aclc = stv0900_get_optim_short_carr_loop(srate,
0894                     modulation, intp->chip_id);
0895             if (modulation == STV0900_QPSK)
0896                 stv0900_write_reg(intp, ACLC2S2Q, aclc);
0897             else if (modulation == STV0900_8PSK) {
0898                 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
0899                 stv0900_write_reg(intp, ACLC2S28, aclc);
0900             } else if (modulation == STV0900_16APSK) {
0901                 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
0902                 stv0900_write_reg(intp, ACLC2S216A, aclc);
0903             } else if (modulation == STV0900_32APSK) {
0904                 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
0905                 stv0900_write_reg(intp, ACLC2S232A, aclc);
0906             }
0907 
0908         }
0909 
0910         if (intp->chip_id <= 0x11) {
0911             if (intp->demod_mode != STV0900_SINGLE)
0912                 stv0900_activate_s2_modcod(intp, demod);
0913 
0914         }
0915 
0916         stv0900_write_reg(intp, ERRCTRL1, 0x67);
0917         break;
0918     case STV0900_UNKNOWN_STANDARD:
0919     default:
0920         dprintk("%s: found unknown standard\n", __func__);
0921         stv0900_write_bits(intp, DVBS1_ENABLE, 1);
0922         stv0900_write_bits(intp, DVBS2_ENABLE, 1);
0923         break;
0924     }
0925 
0926     freq1 = stv0900_read_reg(intp, CFR2);
0927     freq0 = stv0900_read_reg(intp, CFR1);
0928     if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
0929         stv0900_write_reg(intp, SFRSTEP, 0x00);
0930         stv0900_write_bits(intp, SCAN_ENABLE, 0);
0931         stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
0932         stv0900_write_reg(intp, TMGCFG2, 0xc1);
0933         stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
0934         blind_tun_sw = 1;
0935         if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
0936             stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
0937 
0938     }
0939 
0940     if (intp->chip_id >= 0x20) {
0941         if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
0942                 (intp->srch_standard[demod] ==
0943                             STV0900_SEARCH_DSS) ||
0944                 (intp->srch_standard[demod] ==
0945                             STV0900_AUTO_SEARCH)) {
0946             stv0900_write_reg(intp, VAVSRVIT, 0x0a);
0947             stv0900_write_reg(intp, VITSCALE, 0x0);
0948         }
0949     }
0950 
0951     if (intp->chip_id < 0x20)
0952         stv0900_write_reg(intp, CARHDR, 0x08);
0953 
0954     if (intp->chip_id == 0x10)
0955         stv0900_write_reg(intp, CORRELEXP, 0x0a);
0956 
0957     stv0900_write_reg(intp, AGC2REF, 0x38);
0958 
0959     if ((intp->chip_id >= 0x20) ||
0960             (blind_tun_sw == 1) ||
0961             (intp->symbol_rate[demod] < 10000000)) {
0962         stv0900_write_reg(intp, CFRINIT1, freq1);
0963         stv0900_write_reg(intp, CFRINIT0, freq0);
0964         intp->bw[demod] = stv0900_carrier_width(srate,
0965                     intp->rolloff) + 10000000;
0966 
0967         if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
0968             if (intp->srch_algo[demod] != STV0900_WARM_START) {
0969                 if (intp->tuner_type[demod] == 3)
0970                     stv0900_set_tuner_auto(intp,
0971                             intp->freq[demod],
0972                             intp->bw[demod],
0973                             demod);
0974                 else
0975                     stv0900_set_bandwidth(fe,
0976                             intp->bw[demod]);
0977             }
0978         }
0979 
0980         if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
0981                 (intp->symbol_rate[demod] < 10000000))
0982             msleep(50);
0983         else
0984             msleep(5);
0985 
0986         stv0900_get_lock_timeout(&timed, &timef, srate,
0987                         STV0900_WARM_START);
0988 
0989         if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
0990             stv0900_write_reg(intp, DMDISTATE, 0x1f);
0991             stv0900_write_reg(intp, CFRINIT1, freq1);
0992             stv0900_write_reg(intp, CFRINIT0, freq0);
0993             stv0900_write_reg(intp, DMDISTATE, 0x18);
0994             i = 0;
0995             while ((stv0900_get_demod_lock(intp,
0996                             demod,
0997                             timed / 2) == FALSE) &&
0998                         (i <= 2)) {
0999                 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1000                 stv0900_write_reg(intp, CFRINIT1, freq1);
1001                 stv0900_write_reg(intp, CFRINIT0, freq0);
1002                 stv0900_write_reg(intp, DMDISTATE, 0x18);
1003                 i++;
1004             }
1005         }
1006 
1007     }
1008 
1009     if (intp->chip_id >= 0x20)
1010         stv0900_write_reg(intp, CARFREQ, 0x49);
1011 
1012     if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
1013             (intp->result[demod].standard == STV0900_DSS_STANDARD))
1014         stv0900_set_viterbi_tracq(intp, demod);
1015 
1016 }
1017 
1018 static int stv0900_get_fec_lock(struct stv0900_internal *intp,
1019                 enum fe_stv0900_demod_num demod, s32 time_out)
1020 {
1021     s32 timer = 0, lock = 0;
1022 
1023     enum fe_stv0900_search_state dmd_state;
1024 
1025     dprintk("%s\n", __func__);
1026 
1027     dmd_state = stv0900_get_bits(intp, HEADER_MODE);
1028 
1029     while ((timer < time_out) && (lock == 0)) {
1030         switch (dmd_state) {
1031         case STV0900_SEARCH:
1032         case STV0900_PLH_DETECTED:
1033         default:
1034             lock = 0;
1035             break;
1036         case STV0900_DVBS2_FOUND:
1037             lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
1038             break;
1039         case STV0900_DVBS_FOUND:
1040             lock = stv0900_get_bits(intp, LOCKEDVIT);
1041             break;
1042         }
1043 
1044         if (lock == 0) {
1045             msleep(10);
1046             timer += 10;
1047         }
1048     }
1049 
1050     if (lock)
1051         dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
1052     else
1053         dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
1054 
1055     return lock;
1056 }
1057 
1058 static int stv0900_wait_for_lock(struct stv0900_internal *intp,
1059                 enum fe_stv0900_demod_num demod,
1060                 s32 dmd_timeout, s32 fec_timeout)
1061 {
1062 
1063     s32 timer = 0, lock = 0;
1064 
1065     dprintk("%s\n", __func__);
1066 
1067     lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
1068 
1069     if (lock)
1070         lock = stv0900_get_fec_lock(intp, demod, fec_timeout);
1071 
1072     if (lock) {
1073         lock = 0;
1074 
1075         dprintk("%s: Timer = %d, time_out = %d\n",
1076                 __func__, timer, fec_timeout);
1077 
1078         while ((timer < fec_timeout) && (lock == 0)) {
1079             lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
1080             msleep(1);
1081             timer++;
1082         }
1083     }
1084 
1085     if (lock)
1086         dprintk("%s: DEMOD LOCK OK\n", __func__);
1087     else
1088         dprintk("%s: DEMOD LOCK FAIL\n", __func__);
1089 
1090     if (lock)
1091         return TRUE;
1092     else
1093         return FALSE;
1094 }
1095 
1096 enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
1097                         enum fe_stv0900_demod_num demod)
1098 {
1099     struct stv0900_state *state = fe->demodulator_priv;
1100     struct stv0900_internal *intp = state->internal;
1101     enum fe_stv0900_tracking_standard fnd_standard;
1102 
1103     int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
1104 
1105     switch (hdr_mode) {
1106     case 2:
1107         fnd_standard = STV0900_DVBS2_STANDARD;
1108         break;
1109     case 3:
1110         if (stv0900_get_bits(intp, DSS_DVB) == 1)
1111             fnd_standard = STV0900_DSS_STANDARD;
1112         else
1113             fnd_standard = STV0900_DVBS1_STANDARD;
1114 
1115         break;
1116     default:
1117         fnd_standard = STV0900_UNKNOWN_STANDARD;
1118     }
1119 
1120     dprintk("%s: standard %d\n", __func__, fnd_standard);
1121 
1122     return fnd_standard;
1123 }
1124 
1125 static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
1126                     enum fe_stv0900_demod_num demod)
1127 {
1128     s32 derot,
1129         rem1,
1130         rem2,
1131         intval1,
1132         intval2;
1133 
1134     derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
1135         (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
1136         (stv0900_get_bits(intp, CAR_FREQ0));
1137 
1138     derot = ge2comp(derot, 24);
1139     intval1 = mclk >> 12;
1140     intval2 = derot >> 12;
1141     rem1 = mclk % 0x1000;
1142     rem2 = derot % 0x1000;
1143     derot = (intval1 * intval2) +
1144         ((intval1 * rem2) >> 12) +
1145         ((intval2 * rem1) >> 12);
1146 
1147     return derot;
1148 }
1149 
1150 static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1151 {
1152     struct dvb_frontend_ops *frontend_ops = NULL;
1153     struct dvb_tuner_ops *tuner_ops = NULL;
1154     u32 freq = 0;
1155 
1156     frontend_ops = &fe->ops;
1157     tuner_ops = &frontend_ops->tuner_ops;
1158 
1159     if (tuner_ops->get_frequency) {
1160         if ((tuner_ops->get_frequency(fe, &freq)) < 0)
1161             dprintk("%s: Invalid parameter\n", __func__);
1162         else
1163             dprintk("%s: Frequency=%d\n", __func__, freq);
1164 
1165     }
1166 
1167     return freq;
1168 }
1169 
1170 static enum
1171 fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
1172 {
1173     struct stv0900_state *state = fe->demodulator_priv;
1174     struct stv0900_internal *intp = state->internal;
1175     enum fe_stv0900_demod_num demod = state->demod;
1176     enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
1177     struct stv0900_signal_info *result = &intp->result[demod];
1178     s32 offsetFreq,
1179         srate_offset;
1180     int i = 0,
1181         d = demod;
1182 
1183     u8 timing;
1184 
1185     msleep(5);
1186     if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
1187         timing = stv0900_read_reg(intp, TMGREG2);
1188         i = 0;
1189         stv0900_write_reg(intp, SFRSTEP, 0x5c);
1190 
1191         while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
1192             timing = stv0900_read_reg(intp, TMGREG2);
1193             msleep(5);
1194             i += 5;
1195         }
1196     }
1197 
1198     result->standard = stv0900_get_standard(fe, d);
1199     if (intp->tuner_type[demod] == 3)
1200         result->frequency = stv0900_get_freq_auto(intp, d);
1201     else
1202         result->frequency = stv0900_get_tuner_freq(fe);
1203 
1204     offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
1205     result->frequency += offsetFreq;
1206     result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
1207     srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
1208     result->symbol_rate += srate_offset;
1209     result->fec = stv0900_get_vit_fec(intp, d);
1210     result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
1211     result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
1212     result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
1213     result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
1214 
1215     dprintk("%s: modcode=0x%x \n", __func__, result->modcode);
1216 
1217     switch (result->standard) {
1218     case STV0900_DVBS2_STANDARD:
1219         result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
1220         if (result->modcode <= STV0900_QPSK_910)
1221             result->modulation = STV0900_QPSK;
1222         else if (result->modcode <= STV0900_8PSK_910)
1223             result->modulation = STV0900_8PSK;
1224         else if (result->modcode <= STV0900_16APSK_910)
1225             result->modulation = STV0900_16APSK;
1226         else if (result->modcode <= STV0900_32APSK_910)
1227             result->modulation = STV0900_32APSK;
1228         else
1229             result->modulation = STV0900_UNKNOWN;
1230         break;
1231     case STV0900_DVBS1_STANDARD:
1232     case STV0900_DSS_STANDARD:
1233         result->spectrum = stv0900_get_bits(intp, IQINV);
1234         result->modulation = STV0900_QPSK;
1235         break;
1236     default:
1237         break;
1238     }
1239 
1240     if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
1241                 (intp->symbol_rate[d] < 10000000)) {
1242         offsetFreq = result->frequency - intp->freq[d];
1243         if (intp->tuner_type[demod] == 3)
1244             intp->freq[d] = stv0900_get_freq_auto(intp, d);
1245         else
1246             intp->freq[d] = stv0900_get_tuner_freq(fe);
1247 
1248         if (abs(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1249             range = STV0900_RANGEOK;
1250         else if (abs(offsetFreq) <=
1251                 (stv0900_carrier_width(result->symbol_rate,
1252                         result->rolloff) / 2000))
1253             range = STV0900_RANGEOK;
1254 
1255     } else if (abs(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1256         range = STV0900_RANGEOK;
1257 
1258     dprintk("%s: range %d\n", __func__, range);
1259 
1260     return range;
1261 }
1262 
1263 static enum
1264 fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
1265 {
1266     struct stv0900_state *state = fe->demodulator_priv;
1267     struct stv0900_internal *intp = state->internal;
1268     enum fe_stv0900_demod_num demod = state->demod;
1269     enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
1270 
1271     s32 srate,
1272         demod_timeout,
1273         fec_timeout,
1274         freq1,
1275         freq0;
1276 
1277     intp->result[demod].locked = FALSE;
1278 
1279     if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
1280         srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1281         srate += stv0900_get_timing_offst(intp, srate, demod);
1282         if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
1283             stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
1284 
1285         stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1286                     srate, STV0900_WARM_START);
1287         freq1 = stv0900_read_reg(intp, CFR2);
1288         freq0 = stv0900_read_reg(intp, CFR1);
1289         stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1290         stv0900_write_bits(intp, SPECINV_CONTROL,
1291                     STV0900_IQ_FORCE_SWAPPED);
1292         stv0900_write_reg(intp, DMDISTATE, 0x1c);
1293         stv0900_write_reg(intp, CFRINIT1, freq1);
1294         stv0900_write_reg(intp, CFRINIT0, freq0);
1295         stv0900_write_reg(intp, DMDISTATE, 0x18);
1296         if (stv0900_wait_for_lock(intp, demod,
1297                 demod_timeout, fec_timeout) == TRUE) {
1298             intp->result[demod].locked = TRUE;
1299             signal_type = stv0900_get_signal_params(fe);
1300             stv0900_track_optimization(fe);
1301         } else {
1302             stv0900_write_bits(intp, SPECINV_CONTROL,
1303                     STV0900_IQ_FORCE_NORMAL);
1304             stv0900_write_reg(intp, DMDISTATE, 0x1c);
1305             stv0900_write_reg(intp, CFRINIT1, freq1);
1306             stv0900_write_reg(intp, CFRINIT0, freq0);
1307             stv0900_write_reg(intp, DMDISTATE, 0x18);
1308             if (stv0900_wait_for_lock(intp, demod,
1309                     demod_timeout, fec_timeout) == TRUE) {
1310                 intp->result[demod].locked = TRUE;
1311                 signal_type = stv0900_get_signal_params(fe);
1312                 stv0900_track_optimization(fe);
1313             }
1314 
1315         }
1316 
1317     } else
1318         intp->result[demod].locked = FALSE;
1319 
1320     return signal_type;
1321 }
1322 
1323 static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
1324                     enum fe_stv0900_demod_num demod)
1325 {
1326     u32 minagc2level = 0xffff,
1327         agc2level,
1328         init_freq, freq_step;
1329 
1330     s32 i, j, nb_steps, direction;
1331 
1332     dprintk("%s\n", __func__);
1333 
1334     stv0900_write_reg(intp, AGC2REF, 0x38);
1335     stv0900_write_bits(intp, SCAN_ENABLE, 0);
1336     stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1337 
1338     stv0900_write_bits(intp, AUTO_GUP, 1);
1339     stv0900_write_bits(intp, AUTO_GLOW, 1);
1340 
1341     stv0900_write_reg(intp, DMDT0M, 0x0);
1342 
1343     stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1344     nb_steps = -1 + (intp->srch_range[demod] / 1000000);
1345     nb_steps /= 2;
1346     nb_steps = (2 * nb_steps) + 1;
1347 
1348     if (nb_steps < 0)
1349         nb_steps = 1;
1350 
1351     direction = 1;
1352 
1353     freq_step = (1000000 << 8) / (intp->mclk >> 8);
1354 
1355     init_freq = 0;
1356 
1357     for (i = 0; i < nb_steps; i++) {
1358         if (direction > 0)
1359             init_freq = init_freq + (freq_step * i);
1360         else
1361             init_freq = init_freq - (freq_step * i);
1362 
1363         direction *= -1;
1364         stv0900_write_reg(intp, DMDISTATE, 0x5C);
1365         stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
1366         stv0900_write_reg(intp, CFRINIT0, init_freq  & 0xff);
1367         stv0900_write_reg(intp, DMDISTATE, 0x58);
1368         msleep(10);
1369         agc2level = 0;
1370 
1371         for (j = 0; j < 10; j++)
1372             agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
1373                     | stv0900_read_reg(intp, AGC2I0);
1374 
1375         agc2level /= 10;
1376 
1377         if (agc2level < minagc2level)
1378             minagc2level = agc2level;
1379 
1380     }
1381 
1382     return (u16)minagc2level;
1383 }
1384 
1385 static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
1386 {
1387     struct stv0900_state *state = fe->demodulator_priv;
1388     struct stv0900_internal *intp = state->internal;
1389     enum fe_stv0900_demod_num demod = state->demod;
1390     int timing_lck = FALSE;
1391     s32 i, timingcpt = 0,
1392         direction = 1,
1393         nb_steps,
1394         current_step = 0,
1395         tuner_freq;
1396     u32 agc2_th,
1397         coarse_srate = 0,
1398         agc2_integr = 0,
1399         currier_step = 1200;
1400 
1401     if (intp->chip_id >= 0x30)
1402         agc2_th = 0x2e00;
1403     else
1404         agc2_th = 0x1f00;
1405 
1406     stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
1407     stv0900_write_reg(intp, TMGCFG, 0x12);
1408     stv0900_write_reg(intp, TMGTHRISE, 0xf0);
1409     stv0900_write_reg(intp, TMGTHFALL, 0xe0);
1410     stv0900_write_bits(intp, SCAN_ENABLE, 1);
1411     stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
1412     stv0900_write_reg(intp, SFRUP1, 0x83);
1413     stv0900_write_reg(intp, SFRUP0, 0xc0);
1414     stv0900_write_reg(intp, SFRLOW1, 0x82);
1415     stv0900_write_reg(intp, SFRLOW0, 0xa0);
1416     stv0900_write_reg(intp, DMDT0M, 0x0);
1417     stv0900_write_reg(intp, AGC2REF, 0x50);
1418 
1419     if (intp->chip_id >= 0x30) {
1420         stv0900_write_reg(intp, CARFREQ, 0x99);
1421         stv0900_write_reg(intp, SFRSTEP, 0x98);
1422     } else if (intp->chip_id >= 0x20) {
1423         stv0900_write_reg(intp, CARFREQ, 0x6a);
1424         stv0900_write_reg(intp, SFRSTEP, 0x95);
1425     } else {
1426         stv0900_write_reg(intp, CARFREQ, 0xed);
1427         stv0900_write_reg(intp, SFRSTEP, 0x73);
1428     }
1429 
1430     if (intp->symbol_rate[demod] <= 2000000)
1431         currier_step = 1000;
1432     else if (intp->symbol_rate[demod] <= 5000000)
1433         currier_step = 2000;
1434     else if (intp->symbol_rate[demod] <= 12000000)
1435         currier_step = 3000;
1436     else
1437             currier_step = 5000;
1438 
1439     nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
1440     nb_steps /= 2;
1441     nb_steps = (2 * nb_steps) + 1;
1442 
1443     if (nb_steps < 0)
1444         nb_steps = 1;
1445     else if (nb_steps > 10) {
1446         nb_steps = 11;
1447         currier_step = (intp->srch_range[demod] / 1000) / 10;
1448     }
1449 
1450     current_step = 0;
1451     direction = 1;
1452 
1453     tuner_freq = intp->freq[demod];
1454 
1455     while ((timing_lck == FALSE) && (current_step < nb_steps)) {
1456         stv0900_write_reg(intp, DMDISTATE, 0x5f);
1457         stv0900_write_bits(intp, DEMOD_MODE, 0);
1458 
1459         msleep(50);
1460 
1461         for (i = 0; i < 10; i++) {
1462             if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
1463                 timingcpt++;
1464 
1465             agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
1466                     stv0900_read_reg(intp, AGC2I0);
1467         }
1468 
1469         agc2_integr /= 10;
1470         coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1471         current_step++;
1472         direction *= -1;
1473 
1474         dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started. tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
1475             tuner_freq, agc2_integr, coarse_srate, timingcpt);
1476 
1477         if ((timingcpt >= 5) &&
1478                 (agc2_integr < agc2_th) &&
1479                 (coarse_srate < 55000000) &&
1480                 (coarse_srate > 850000))
1481             timing_lck = TRUE;
1482         else if (current_step < nb_steps) {
1483             if (direction > 0)
1484                 tuner_freq += (current_step * currier_step);
1485             else
1486                 tuner_freq -= (current_step * currier_step);
1487 
1488             if (intp->tuner_type[demod] == 3)
1489                 stv0900_set_tuner_auto(intp, tuner_freq,
1490                         intp->bw[demod], demod);
1491             else
1492                 stv0900_set_tuner(fe, tuner_freq,
1493                         intp->bw[demod]);
1494         }
1495     }
1496 
1497     if (timing_lck == FALSE)
1498         coarse_srate = 0;
1499     else
1500         coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1501 
1502     return coarse_srate;
1503 }
1504 
1505 static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
1506 {
1507     struct stv0900_state *state = fe->demodulator_priv;
1508     struct stv0900_internal *intp = state->internal;
1509     enum fe_stv0900_demod_num demod = state->demod;
1510     u32 coarse_srate,
1511         coarse_freq,
1512         symb,
1513         symbmax,
1514         symbmin,
1515         symbcomp;
1516 
1517     coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1518 
1519     if (coarse_srate > 3000000) {
1520         symbmax = 13 * (coarse_srate / 10);
1521         symbmax = (symbmax / 1000) * 65536;
1522         symbmax /= (intp->mclk / 1000);
1523 
1524         symbmin = 10 * (coarse_srate / 13);
1525         symbmin = (symbmin / 1000)*65536;
1526         symbmin /= (intp->mclk / 1000);
1527 
1528         symb = (coarse_srate / 1000) * 65536;
1529         symb /= (intp->mclk / 1000);
1530     } else {
1531         symbmax = 13 * (coarse_srate / 10);
1532         symbmax = (symbmax / 100) * 65536;
1533         symbmax /= (intp->mclk / 100);
1534 
1535         symbmin = 10 * (coarse_srate / 14);
1536         symbmin = (symbmin / 100) * 65536;
1537         symbmin /= (intp->mclk / 100);
1538 
1539         symb = (coarse_srate / 100) * 65536;
1540         symb /= (intp->mclk / 100);
1541     }
1542 
1543     symbcomp = 13 * (coarse_srate / 10);
1544     coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
1545               | stv0900_read_reg(intp, CFR1);
1546 
1547     if (symbcomp < intp->symbol_rate[demod])
1548         coarse_srate = 0;
1549     else {
1550         stv0900_write_reg(intp, DMDISTATE, 0x1f);
1551         stv0900_write_reg(intp, TMGCFG2, 0xc1);
1552         stv0900_write_reg(intp, TMGTHRISE, 0x20);
1553         stv0900_write_reg(intp, TMGTHFALL, 0x00);
1554         stv0900_write_reg(intp, TMGCFG, 0xd2);
1555         stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1556         stv0900_write_reg(intp, AGC2REF, 0x38);
1557 
1558         if (intp->chip_id >= 0x30)
1559             stv0900_write_reg(intp, CARFREQ, 0x79);
1560         else if (intp->chip_id >= 0x20)
1561             stv0900_write_reg(intp, CARFREQ, 0x49);
1562         else
1563             stv0900_write_reg(intp, CARFREQ, 0xed);
1564 
1565         stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
1566         stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
1567 
1568         stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
1569         stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
1570 
1571         stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
1572         stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
1573 
1574         stv0900_write_reg(intp, DMDT0M, 0x20);
1575         stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
1576         stv0900_write_reg(intp, CFRINIT0, coarse_freq  & 0xff);
1577         stv0900_write_reg(intp, DMDISTATE, 0x15);
1578     }
1579 
1580     return coarse_srate;
1581 }
1582 
1583 static int stv0900_blind_search_algo(struct dvb_frontend *fe)
1584 {
1585     struct stv0900_state *state = fe->demodulator_priv;
1586     struct stv0900_internal *intp = state->internal;
1587     enum fe_stv0900_demod_num demod = state->demod;
1588     u8  k_ref_tmg,
1589         k_ref_tmg_max,
1590         k_ref_tmg_min;
1591     u32 coarse_srate,
1592         agc2_th;
1593     int lock = FALSE,
1594         coarse_fail = FALSE;
1595     s32 demod_timeout = 500,
1596         fec_timeout = 50,
1597         fail_cpt,
1598         i,
1599         agc2_overflow;
1600     u16 agc2_int;
1601     u8  dstatus2;
1602 
1603     dprintk("%s\n", __func__);
1604 
1605     if (intp->chip_id < 0x20) {
1606         k_ref_tmg_max = 233;
1607         k_ref_tmg_min = 143;
1608     } else {
1609         k_ref_tmg_max = 110;
1610         k_ref_tmg_min = 10;
1611     }
1612 
1613     if (intp->chip_id <= 0x20)
1614         agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
1615     else
1616         agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
1617 
1618     agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
1619 
1620     dprintk("%s agc2_int=%d agc2_th=%d \n", __func__, agc2_int, agc2_th);
1621     if (agc2_int > agc2_th)
1622         return FALSE;
1623 
1624     if (intp->chip_id == 0x10)
1625         stv0900_write_reg(intp, CORRELEXP, 0xaa);
1626 
1627     if (intp->chip_id < 0x20)
1628         stv0900_write_reg(intp, CARHDR, 0x55);
1629     else
1630         stv0900_write_reg(intp, CARHDR, 0x20);
1631 
1632     if (intp->chip_id <= 0x20)
1633         stv0900_write_reg(intp, CARCFG, 0xc4);
1634     else
1635         stv0900_write_reg(intp, CARCFG, 0x6);
1636 
1637     stv0900_write_reg(intp, RTCS2, 0x44);
1638 
1639     if (intp->chip_id >= 0x20) {
1640         stv0900_write_reg(intp, EQUALCFG, 0x41);
1641         stv0900_write_reg(intp, FFECFG, 0x41);
1642         stv0900_write_reg(intp, VITSCALE, 0x82);
1643         stv0900_write_reg(intp, VAVSRVIT, 0x0);
1644     }
1645 
1646     k_ref_tmg = k_ref_tmg_max;
1647 
1648     do {
1649         stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
1650         if (stv0900_search_srate_coarse(fe) != 0) {
1651             coarse_srate = stv0900_search_srate_fine(fe);
1652 
1653             if (coarse_srate != 0) {
1654                 stv0900_get_lock_timeout(&demod_timeout,
1655                             &fec_timeout,
1656                             coarse_srate,
1657                             STV0900_BLIND_SEARCH);
1658                 lock = stv0900_get_demod_lock(intp,
1659                             demod,
1660                             demod_timeout);
1661             } else
1662                 lock = FALSE;
1663         } else {
1664             fail_cpt = 0;
1665             agc2_overflow = 0;
1666 
1667             for (i = 0; i < 10; i++) {
1668                 agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
1669                     | stv0900_read_reg(intp, AGC2I0);
1670 
1671                 if (agc2_int >= 0xff00)
1672                     agc2_overflow++;
1673 
1674                 dstatus2 = stv0900_read_reg(intp, DSTATUS2);
1675 
1676                 if (((dstatus2 & 0x1) == 0x1) &&
1677                         ((dstatus2 >> 7) == 1))
1678                     fail_cpt++;
1679             }
1680 
1681             if ((fail_cpt > 7) || (agc2_overflow > 7))
1682                 coarse_fail = TRUE;
1683 
1684             lock = FALSE;
1685         }
1686         k_ref_tmg -= 30;
1687     } while ((k_ref_tmg >= k_ref_tmg_min) &&
1688                 (lock == FALSE) &&
1689                 (coarse_fail == FALSE));
1690 
1691     return lock;
1692 }
1693 
1694 static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
1695                     enum fe_stv0900_demod_num demod)
1696 {
1697     s32 vth_reg = VTH12;
1698 
1699     dprintk("%s\n", __func__);
1700 
1701     stv0900_write_reg(intp, vth_reg++, 0x96);
1702     stv0900_write_reg(intp, vth_reg++, 0x64);
1703     stv0900_write_reg(intp, vth_reg++, 0x36);
1704     stv0900_write_reg(intp, vth_reg++, 0x23);
1705     stv0900_write_reg(intp, vth_reg++, 0x1e);
1706     stv0900_write_reg(intp, vth_reg++, 0x19);
1707 }
1708 
1709 static void stv0900_set_search_standard(struct stv0900_internal *intp,
1710                     enum fe_stv0900_demod_num demod)
1711 {
1712 
1713     dprintk("%s\n", __func__);
1714 
1715     switch (intp->srch_standard[demod]) {
1716     case STV0900_SEARCH_DVBS1:
1717         dprintk("Search Standard = DVBS1\n");
1718         break;
1719     case STV0900_SEARCH_DSS:
1720         dprintk("Search Standard = DSS\n");
1721         break;
1722     case STV0900_SEARCH_DVBS2:
1723         dprintk("Search Standard = DVBS2\n");
1724         break;
1725     case STV0900_AUTO_SEARCH:
1726     default:
1727         dprintk("Search Standard = AUTO\n");
1728         break;
1729     }
1730 
1731     switch (intp->srch_standard[demod]) {
1732     case STV0900_SEARCH_DVBS1:
1733     case STV0900_SEARCH_DSS:
1734         stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1735         stv0900_write_bits(intp, DVBS2_ENABLE, 0);
1736         stv0900_write_bits(intp, STOP_CLKVIT, 0);
1737         stv0900_set_dvbs1_track_car_loop(intp,
1738                         demod,
1739                         intp->symbol_rate[demod]);
1740         stv0900_write_reg(intp, CAR2CFG, 0x22);
1741 
1742         stv0900_set_viterbi_acq(intp, demod);
1743         stv0900_set_viterbi_standard(intp,
1744                     intp->srch_standard[demod],
1745                     intp->fec[demod], demod);
1746 
1747         break;
1748     case STV0900_SEARCH_DVBS2:
1749         stv0900_write_bits(intp, DVBS1_ENABLE, 0);
1750         stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1751         stv0900_write_bits(intp, STOP_CLKVIT, 1);
1752         stv0900_write_reg(intp, ACLC, 0x1a);
1753         stv0900_write_reg(intp, BCLC, 0x09);
1754         if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1755             stv0900_write_reg(intp, CAR2CFG, 0x26);
1756         else
1757             stv0900_write_reg(intp, CAR2CFG, 0x66);
1758 
1759         if (intp->demod_mode != STV0900_SINGLE) {
1760             if (intp->chip_id <= 0x11)
1761                 stv0900_stop_all_s2_modcod(intp, demod);
1762             else
1763                 stv0900_activate_s2_modcod(intp, demod);
1764 
1765         } else
1766             stv0900_activate_s2_modcod_single(intp, demod);
1767 
1768         stv0900_set_viterbi_tracq(intp, demod);
1769 
1770         break;
1771     case STV0900_AUTO_SEARCH:
1772     default:
1773         stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1774         stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1775         stv0900_write_bits(intp, STOP_CLKVIT, 0);
1776         stv0900_write_reg(intp, ACLC, 0x1a);
1777         stv0900_write_reg(intp, BCLC, 0x09);
1778         stv0900_set_dvbs1_track_car_loop(intp,
1779                         demod,
1780                         intp->symbol_rate[demod]);
1781         if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1782             stv0900_write_reg(intp, CAR2CFG, 0x26);
1783         else
1784             stv0900_write_reg(intp, CAR2CFG, 0x66);
1785 
1786         if (intp->demod_mode != STV0900_SINGLE) {
1787             if (intp->chip_id <= 0x11)
1788                 stv0900_stop_all_s2_modcod(intp, demod);
1789             else
1790                 stv0900_activate_s2_modcod(intp, demod);
1791 
1792         } else
1793             stv0900_activate_s2_modcod_single(intp, demod);
1794 
1795         stv0900_set_viterbi_tracq(intp, demod);
1796         stv0900_set_viterbi_standard(intp,
1797                         intp->srch_standard[demod],
1798                         intp->fec[demod], demod);
1799 
1800         break;
1801     }
1802 }
1803 
1804 enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
1805 {
1806     struct stv0900_state *state = fe->demodulator_priv;
1807     struct stv0900_internal *intp = state->internal;
1808     enum fe_stv0900_demod_num demod = state->demod;
1809 
1810     s32 demod_timeout = 500, fec_timeout = 50;
1811     s32 aq_power, agc1_power, i;
1812 
1813     int lock = FALSE, low_sr = FALSE;
1814 
1815     enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
1816     enum fe_stv0900_search_algo algo;
1817     int no_signal = FALSE;
1818 
1819     dprintk("%s\n", __func__);
1820 
1821     algo = intp->srch_algo[demod];
1822     stv0900_write_bits(intp, RST_HWARE, 1);
1823     stv0900_write_reg(intp, DMDISTATE, 0x5c);
1824     if (intp->chip_id >= 0x20) {
1825         if (intp->symbol_rate[demod] > 5000000)
1826             stv0900_write_reg(intp, CORRELABS, 0x9e);
1827         else
1828             stv0900_write_reg(intp, CORRELABS, 0x82);
1829     } else
1830         stv0900_write_reg(intp, CORRELABS, 0x88);
1831 
1832     stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1833                 intp->symbol_rate[demod],
1834                 intp->srch_algo[demod]);
1835 
1836     if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
1837         intp->bw[demod] = 2 * 36000000;
1838 
1839         stv0900_write_reg(intp, TMGCFG2, 0xc0);
1840         stv0900_write_reg(intp, CORRELMANT, 0x70);
1841 
1842         stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1843     } else {
1844         stv0900_write_reg(intp, DMDT0M, 0x20);
1845         stv0900_write_reg(intp, TMGCFG, 0xd2);
1846 
1847         if (intp->symbol_rate[demod] < 2000000)
1848             stv0900_write_reg(intp, CORRELMANT, 0x63);
1849         else
1850             stv0900_write_reg(intp, CORRELMANT, 0x70);
1851 
1852         stv0900_write_reg(intp, AGC2REF, 0x38);
1853 
1854         intp->bw[demod] =
1855                 stv0900_carrier_width(intp->symbol_rate[demod],
1856                                 intp->rolloff);
1857         if (intp->chip_id >= 0x20) {
1858             stv0900_write_reg(intp, KREFTMG, 0x5a);
1859 
1860             if (intp->srch_algo[demod] == STV0900_COLD_START) {
1861                 intp->bw[demod] += 10000000;
1862                 intp->bw[demod] *= 15;
1863                 intp->bw[demod] /= 10;
1864             } else if (intp->srch_algo[demod] == STV0900_WARM_START)
1865                 intp->bw[demod] += 10000000;
1866 
1867         } else {
1868             stv0900_write_reg(intp, KREFTMG, 0xc1);
1869             intp->bw[demod] += 10000000;
1870             intp->bw[demod] *= 15;
1871             intp->bw[demod] /= 10;
1872         }
1873 
1874         stv0900_write_reg(intp, TMGCFG2, 0xc1);
1875 
1876         stv0900_set_symbol_rate(intp, intp->mclk,
1877                     intp->symbol_rate[demod], demod);
1878         stv0900_set_max_symbol_rate(intp, intp->mclk,
1879                     intp->symbol_rate[demod], demod);
1880         stv0900_set_min_symbol_rate(intp, intp->mclk,
1881                     intp->symbol_rate[demod], demod);
1882         if (intp->symbol_rate[demod] >= 10000000)
1883             low_sr = FALSE;
1884         else
1885             low_sr = TRUE;
1886 
1887     }
1888 
1889     if (intp->tuner_type[demod] == 3)
1890         stv0900_set_tuner_auto(intp, intp->freq[demod],
1891                 intp->bw[demod], demod);
1892     else
1893         stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
1894 
1895     agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
1896                 stv0900_get_bits(intp, AGCIQ_VALUE0));
1897 
1898     aq_power = 0;
1899 
1900     if (agc1_power == 0) {
1901         for (i = 0; i < 5; i++)
1902             aq_power += (stv0900_get_bits(intp, POWER_I) +
1903                     stv0900_get_bits(intp, POWER_Q)) / 2;
1904 
1905         aq_power /= 5;
1906     }
1907 
1908     if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
1909         intp->result[demod].locked = FALSE;
1910         signal_type = STV0900_NOAGC1;
1911         dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
1912     } else {
1913         stv0900_write_bits(intp, SPECINV_CONTROL,
1914                     intp->srch_iq_inv[demod]);
1915         if (intp->chip_id <= 0x20) /*cut 2.0*/
1916             stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
1917         else /*cut 3.0*/
1918             stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
1919 
1920         stv0900_set_search_standard(intp, demod);
1921 
1922         if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
1923             stv0900_start_search(intp, demod);
1924     }
1925 
1926     if (signal_type == STV0900_NOAGC1)
1927         return signal_type;
1928 
1929     if (intp->chip_id == 0x12) {
1930         stv0900_write_bits(intp, RST_HWARE, 0);
1931         msleep(3);
1932         stv0900_write_bits(intp, RST_HWARE, 1);
1933         stv0900_write_bits(intp, RST_HWARE, 0);
1934     }
1935 
1936     if (algo == STV0900_BLIND_SEARCH)
1937         lock = stv0900_blind_search_algo(fe);
1938     else if (algo == STV0900_COLD_START)
1939         lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
1940     else if (algo == STV0900_WARM_START)
1941         lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
1942 
1943     if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
1944         if (low_sr == FALSE) {
1945             if (stv0900_check_timing_lock(intp, demod) == TRUE)
1946                 lock = stv0900_sw_algo(intp, demod);
1947         }
1948     }
1949 
1950     if (lock == TRUE)
1951         signal_type = stv0900_get_signal_params(fe);
1952 
1953     if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
1954         stv0900_track_optimization(fe);
1955         if (intp->chip_id <= 0x11) {
1956             if ((stv0900_get_standard(fe, 0) ==
1957                         STV0900_DVBS1_STANDARD) &&
1958                (stv0900_get_standard(fe, 1) ==
1959                         STV0900_DVBS1_STANDARD)) {
1960                 msleep(20);
1961                 stv0900_write_bits(intp, RST_HWARE, 0);
1962             } else {
1963                 stv0900_write_bits(intp, RST_HWARE, 0);
1964                 msleep(3);
1965                 stv0900_write_bits(intp, RST_HWARE, 1);
1966                 stv0900_write_bits(intp, RST_HWARE, 0);
1967             }
1968 
1969         } else if (intp->chip_id >= 0x20) {
1970             stv0900_write_bits(intp, RST_HWARE, 0);
1971             msleep(3);
1972             stv0900_write_bits(intp, RST_HWARE, 1);
1973             stv0900_write_bits(intp, RST_HWARE, 0);
1974         }
1975 
1976         if (stv0900_wait_for_lock(intp, demod,
1977                     fec_timeout, fec_timeout) == TRUE) {
1978             lock = TRUE;
1979             intp->result[demod].locked = TRUE;
1980             if (intp->result[demod].standard ==
1981                         STV0900_DVBS2_STANDARD) {
1982                 stv0900_set_dvbs2_rolloff(intp, demod);
1983                 stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
1984                 stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
1985                 stv0900_write_reg(intp, ERRCTRL1, 0x67);
1986             } else {
1987                 stv0900_write_reg(intp, ERRCTRL1, 0x75);
1988             }
1989 
1990             stv0900_write_reg(intp, FBERCPT4, 0);
1991             stv0900_write_reg(intp, ERRCTRL2, 0xc1);
1992         } else {
1993             lock = FALSE;
1994             signal_type = STV0900_NODATA;
1995             no_signal = stv0900_check_signal_presence(intp, demod);
1996 
1997             intp->result[demod].locked = FALSE;
1998         }
1999     }
2000 
2001     if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
2002         return signal_type;
2003 
2004     if (intp->chip_id > 0x11) {
2005         intp->result[demod].locked = FALSE;
2006         return signal_type;
2007     }
2008 
2009     if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
2010        (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
2011         signal_type = stv0900_dvbs1_acq_workaround(fe);
2012 
2013     return signal_type;
2014 }
2015
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