Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * stv0900_core.c
0004  *
0005  * Driver for ST STV0900 satellite demodulator IC.
0006  *
0007  * Copyright (C) ST Microelectronics.
0008  * Copyright (C) 2009 NetUP Inc.
0009  * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
0010  */
0011 
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/string.h>
0015 #include <linux/slab.h>
0016 #include <linux/i2c.h>
0017 
0018 #include "stv0900.h"
0019 #include "stv0900_reg.h"
0020 #include "stv0900_priv.h"
0021 #include "stv0900_init.h"
0022 
0023 int stvdebug = 1;
0024 module_param_named(debug, stvdebug, int, 0644);
0025 
0026 /* internal params node */
0027 struct stv0900_inode {
0028     /* pointer for internal params, one for each pair of demods */
0029     struct stv0900_internal     *internal;
0030     struct stv0900_inode        *next_inode;
0031 };
0032 
0033 /* first internal params */
0034 static struct stv0900_inode *stv0900_first_inode;
0035 
0036 /* find chip by i2c adapter and i2c address */
0037 static struct stv0900_inode *find_inode(struct i2c_adapter *i2c_adap,
0038                             u8 i2c_addr)
0039 {
0040     struct stv0900_inode *temp_chip = stv0900_first_inode;
0041 
0042     if (temp_chip != NULL) {
0043         /*
0044          Search of the last stv0900 chip or
0045          find it by i2c adapter and i2c address */
0046         while ((temp_chip != NULL) &&
0047             ((temp_chip->internal->i2c_adap != i2c_adap) ||
0048             (temp_chip->internal->i2c_addr != i2c_addr)))
0049 
0050             temp_chip = temp_chip->next_inode;
0051 
0052     }
0053 
0054     return temp_chip;
0055 }
0056 
0057 /* deallocating chip */
0058 static void remove_inode(struct stv0900_internal *internal)
0059 {
0060     struct stv0900_inode *prev_node = stv0900_first_inode;
0061     struct stv0900_inode *del_node = find_inode(internal->i2c_adap,
0062                         internal->i2c_addr);
0063 
0064     if (del_node != NULL) {
0065         if (del_node == stv0900_first_inode) {
0066             stv0900_first_inode = del_node->next_inode;
0067         } else {
0068             while (prev_node->next_inode != del_node)
0069                 prev_node = prev_node->next_inode;
0070 
0071             if (del_node->next_inode == NULL)
0072                 prev_node->next_inode = NULL;
0073             else
0074                 prev_node->next_inode =
0075                     prev_node->next_inode->next_inode;
0076         }
0077 
0078         kfree(del_node);
0079     }
0080 }
0081 
0082 /* allocating new chip */
0083 static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
0084 {
0085     struct stv0900_inode *new_node = stv0900_first_inode;
0086 
0087     if (new_node == NULL) {
0088         new_node = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
0089         stv0900_first_inode = new_node;
0090     } else {
0091         while (new_node->next_inode != NULL)
0092             new_node = new_node->next_inode;
0093 
0094         new_node->next_inode = kmalloc(sizeof(struct stv0900_inode),
0095                                 GFP_KERNEL);
0096         if (new_node->next_inode != NULL)
0097             new_node = new_node->next_inode;
0098         else
0099             new_node = NULL;
0100     }
0101 
0102     if (new_node != NULL) {
0103         new_node->internal = internal;
0104         new_node->next_inode = NULL;
0105     }
0106 
0107     return new_node;
0108 }
0109 
0110 s32 ge2comp(s32 a, s32 width)
0111 {
0112     if (width == 32)
0113         return a;
0114     else
0115         return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
0116 }
0117 
0118 void stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr,
0119                                 u8 reg_data)
0120 {
0121     u8 data[3];
0122     int ret;
0123     struct i2c_msg i2cmsg = {
0124         .addr  = intp->i2c_addr,
0125         .flags = 0,
0126         .len   = 3,
0127         .buf   = data,
0128     };
0129 
0130     data[0] = MSB(reg_addr);
0131     data[1] = LSB(reg_addr);
0132     data[2] = reg_data;
0133 
0134     ret = i2c_transfer(intp->i2c_adap, &i2cmsg, 1);
0135     if (ret != 1)
0136         dprintk("%s: i2c error %d\n", __func__, ret);
0137 }
0138 
0139 u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg)
0140 {
0141     int ret;
0142     u8 b0[] = { MSB(reg), LSB(reg) };
0143     u8 buf = 0;
0144     struct i2c_msg msg[] = {
0145         {
0146             .addr   = intp->i2c_addr,
0147             .flags  = 0,
0148             .buf = b0,
0149             .len = 2,
0150         }, {
0151             .addr   = intp->i2c_addr,
0152             .flags  = I2C_M_RD,
0153             .buf = &buf,
0154             .len = 1,
0155         },
0156     };
0157 
0158     ret = i2c_transfer(intp->i2c_adap, msg, 2);
0159     if (ret != 2)
0160         dprintk("%s: i2c error %d, reg[0x%02x]\n",
0161                 __func__, ret, reg);
0162 
0163     return buf;
0164 }
0165 
0166 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
0167 {
0168     u8 position = 0, i = 0;
0169 
0170     (*mask) = label & 0xff;
0171 
0172     while ((position == 0) && (i < 8)) {
0173         position = ((*mask) >> i) & 0x01;
0174         i++;
0175     }
0176 
0177     (*pos) = (i - 1);
0178 }
0179 
0180 void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val)
0181 {
0182     u8 reg, mask, pos;
0183 
0184     reg = stv0900_read_reg(intp, (label >> 16) & 0xffff);
0185     extract_mask_pos(label, &mask, &pos);
0186 
0187     val = mask & (val << pos);
0188 
0189     reg = (reg & (~mask)) | val;
0190     stv0900_write_reg(intp, (label >> 16) & 0xffff, reg);
0191 
0192 }
0193 
0194 u8 stv0900_get_bits(struct stv0900_internal *intp, u32 label)
0195 {
0196     u8 val;
0197     u8 mask, pos;
0198 
0199     extract_mask_pos(label, &mask, &pos);
0200 
0201     val = stv0900_read_reg(intp, label >> 16);
0202     val = (val & mask) >> pos;
0203 
0204     return val;
0205 }
0206 
0207 static enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *intp)
0208 {
0209     s32 i;
0210 
0211     if (intp == NULL)
0212         return STV0900_INVALID_HANDLE;
0213 
0214     intp->chip_id = stv0900_read_reg(intp, R0900_MID);
0215 
0216     if (intp->errs != STV0900_NO_ERROR)
0217         return intp->errs;
0218 
0219     /*Startup sequence*/
0220     stv0900_write_reg(intp, R0900_P1_DMDISTATE, 0x5c);
0221     stv0900_write_reg(intp, R0900_P2_DMDISTATE, 0x5c);
0222     msleep(3);
0223     stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x6c);
0224     stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x6f);
0225     stv0900_write_reg(intp, R0900_P1_I2CRPT, 0x20);
0226     stv0900_write_reg(intp, R0900_P2_I2CRPT, 0x20);
0227     stv0900_write_reg(intp, R0900_NCOARSE, 0x13);
0228     msleep(3);
0229     stv0900_write_reg(intp, R0900_I2CCFG, 0x08);
0230 
0231     switch (intp->clkmode) {
0232     case 0:
0233     case 2:
0234         stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20
0235                 | intp->clkmode);
0236         break;
0237     default:
0238         /* preserve SELOSCI bit */
0239         i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
0240         stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | i);
0241         break;
0242     }
0243 
0244     msleep(3);
0245     for (i = 0; i < 181; i++)
0246         stv0900_write_reg(intp, STV0900_InitVal[i][0],
0247                 STV0900_InitVal[i][1]);
0248 
0249     if (stv0900_read_reg(intp, R0900_MID) >= 0x20) {
0250         stv0900_write_reg(intp, R0900_TSGENERAL, 0x0c);
0251         for (i = 0; i < 32; i++)
0252             stv0900_write_reg(intp, STV0900_Cut20_AddOnVal[i][0],
0253                     STV0900_Cut20_AddOnVal[i][1]);
0254     }
0255 
0256     stv0900_write_reg(intp, R0900_P1_FSPYCFG, 0x6c);
0257     stv0900_write_reg(intp, R0900_P2_FSPYCFG, 0x6c);
0258 
0259     stv0900_write_reg(intp, R0900_P1_PDELCTRL2, 0x01);
0260     stv0900_write_reg(intp, R0900_P2_PDELCTRL2, 0x21);
0261 
0262     stv0900_write_reg(intp, R0900_P1_PDELCTRL3, 0x20);
0263     stv0900_write_reg(intp, R0900_P2_PDELCTRL3, 0x20);
0264 
0265     stv0900_write_reg(intp, R0900_TSTRES0, 0x80);
0266     stv0900_write_reg(intp, R0900_TSTRES0, 0x00);
0267 
0268     return STV0900_NO_ERROR;
0269 }
0270 
0271 static u32 stv0900_get_mclk_freq(struct stv0900_internal *intp, u32 ext_clk)
0272 {
0273     u32 mclk, div, ad_div;
0274 
0275     div = stv0900_get_bits(intp, F0900_M_DIV);
0276     ad_div = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
0277 
0278     mclk = (div + 1) * ext_clk / ad_div;
0279 
0280     dprintk("%s: Calculated Mclk = %d\n", __func__, mclk);
0281 
0282     return mclk;
0283 }
0284 
0285 static enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk)
0286 {
0287     u32 m_div, clk_sel;
0288 
0289     if (intp == NULL)
0290         return STV0900_INVALID_HANDLE;
0291 
0292     if (intp->errs)
0293         return STV0900_I2C_ERROR;
0294 
0295     dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
0296             intp->quartz);
0297 
0298     clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
0299     m_div = ((clk_sel * mclk) / intp->quartz) - 1;
0300     stv0900_write_bits(intp, F0900_M_DIV, m_div);
0301     intp->mclk = stv0900_get_mclk_freq(intp,
0302                     intp->quartz);
0303 
0304     /*Set the DiseqC frequency to 22KHz */
0305     /*
0306         Formula:
0307         DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
0308         DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
0309     */
0310     m_div = intp->mclk / 704000;
0311     stv0900_write_reg(intp, R0900_P1_F22TX, m_div);
0312     stv0900_write_reg(intp, R0900_P1_F22RX, m_div);
0313 
0314     stv0900_write_reg(intp, R0900_P2_F22TX, m_div);
0315     stv0900_write_reg(intp, R0900_P2_F22RX, m_div);
0316 
0317     if ((intp->errs))
0318         return STV0900_I2C_ERROR;
0319 
0320     return STV0900_NO_ERROR;
0321 }
0322 
0323 static u32 stv0900_get_err_count(struct stv0900_internal *intp, int cntr,
0324                     enum fe_stv0900_demod_num demod)
0325 {
0326     u32 lsb, msb, hsb, err_val;
0327 
0328     switch (cntr) {
0329     case 0:
0330     default:
0331         hsb = stv0900_get_bits(intp, ERR_CNT12);
0332         msb = stv0900_get_bits(intp, ERR_CNT11);
0333         lsb = stv0900_get_bits(intp, ERR_CNT10);
0334         break;
0335     case 1:
0336         hsb = stv0900_get_bits(intp, ERR_CNT22);
0337         msb = stv0900_get_bits(intp, ERR_CNT21);
0338         lsb = stv0900_get_bits(intp, ERR_CNT20);
0339         break;
0340     }
0341 
0342     err_val = (hsb << 16) + (msb << 8) + (lsb);
0343 
0344     return err_val;
0345 }
0346 
0347 static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
0348 {
0349     struct stv0900_state *state = fe->demodulator_priv;
0350     struct stv0900_internal *intp = state->internal;
0351     enum fe_stv0900_demod_num demod = state->demod;
0352 
0353     stv0900_write_bits(intp, I2CT_ON, enable);
0354 
0355     return 0;
0356 }
0357 
0358 static void stv0900_set_ts_parallel_serial(struct stv0900_internal *intp,
0359                     enum fe_stv0900_clock_type path1_ts,
0360                     enum fe_stv0900_clock_type path2_ts)
0361 {
0362 
0363     dprintk("%s\n", __func__);
0364 
0365     if (intp->chip_id >= 0x20) {
0366         switch (path1_ts) {
0367         case STV0900_PARALLEL_PUNCT_CLOCK:
0368         case STV0900_DVBCI_CLOCK:
0369             switch (path2_ts) {
0370             case STV0900_SERIAL_PUNCT_CLOCK:
0371             case STV0900_SERIAL_CONT_CLOCK:
0372             default:
0373                 stv0900_write_reg(intp, R0900_TSGENERAL,
0374                             0x00);
0375                 break;
0376             case STV0900_PARALLEL_PUNCT_CLOCK:
0377             case STV0900_DVBCI_CLOCK:
0378                 stv0900_write_reg(intp, R0900_TSGENERAL,
0379                             0x06);
0380                 stv0900_write_bits(intp,
0381                         F0900_P1_TSFIFO_MANSPEED, 3);
0382                 stv0900_write_bits(intp,
0383                         F0900_P2_TSFIFO_MANSPEED, 0);
0384                 stv0900_write_reg(intp,
0385                         R0900_P1_TSSPEED, 0x14);
0386                 stv0900_write_reg(intp,
0387                         R0900_P2_TSSPEED, 0x28);
0388                 break;
0389             }
0390             break;
0391         case STV0900_SERIAL_PUNCT_CLOCK:
0392         case STV0900_SERIAL_CONT_CLOCK:
0393         default:
0394             switch (path2_ts) {
0395             case STV0900_SERIAL_PUNCT_CLOCK:
0396             case STV0900_SERIAL_CONT_CLOCK:
0397             default:
0398                 stv0900_write_reg(intp,
0399                         R0900_TSGENERAL, 0x0C);
0400                 break;
0401             case STV0900_PARALLEL_PUNCT_CLOCK:
0402             case STV0900_DVBCI_CLOCK:
0403                 stv0900_write_reg(intp,
0404                         R0900_TSGENERAL, 0x0A);
0405                 dprintk("%s: 0x0a\n", __func__);
0406                 break;
0407             }
0408             break;
0409         }
0410     } else {
0411         switch (path1_ts) {
0412         case STV0900_PARALLEL_PUNCT_CLOCK:
0413         case STV0900_DVBCI_CLOCK:
0414             switch (path2_ts) {
0415             case STV0900_SERIAL_PUNCT_CLOCK:
0416             case STV0900_SERIAL_CONT_CLOCK:
0417             default:
0418                 stv0900_write_reg(intp, R0900_TSGENERAL1X,
0419                             0x10);
0420                 break;
0421             case STV0900_PARALLEL_PUNCT_CLOCK:
0422             case STV0900_DVBCI_CLOCK:
0423                 stv0900_write_reg(intp, R0900_TSGENERAL1X,
0424                             0x16);
0425                 stv0900_write_bits(intp,
0426                         F0900_P1_TSFIFO_MANSPEED, 3);
0427                 stv0900_write_bits(intp,
0428                         F0900_P2_TSFIFO_MANSPEED, 0);
0429                 stv0900_write_reg(intp, R0900_P1_TSSPEED,
0430                             0x14);
0431                 stv0900_write_reg(intp, R0900_P2_TSSPEED,
0432                             0x28);
0433                 break;
0434             }
0435 
0436             break;
0437         case STV0900_SERIAL_PUNCT_CLOCK:
0438         case STV0900_SERIAL_CONT_CLOCK:
0439         default:
0440             switch (path2_ts) {
0441             case STV0900_SERIAL_PUNCT_CLOCK:
0442             case STV0900_SERIAL_CONT_CLOCK:
0443             default:
0444                 stv0900_write_reg(intp, R0900_TSGENERAL1X,
0445                             0x14);
0446                 break;
0447             case STV0900_PARALLEL_PUNCT_CLOCK:
0448             case STV0900_DVBCI_CLOCK:
0449                 stv0900_write_reg(intp, R0900_TSGENERAL1X,
0450                             0x12);
0451                 dprintk("%s: 0x12\n", __func__);
0452                 break;
0453             }
0454 
0455             break;
0456         }
0457     }
0458 
0459     switch (path1_ts) {
0460     case STV0900_PARALLEL_PUNCT_CLOCK:
0461         stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
0462         stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
0463         break;
0464     case STV0900_DVBCI_CLOCK:
0465         stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
0466         stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
0467         break;
0468     case STV0900_SERIAL_PUNCT_CLOCK:
0469         stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
0470         stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
0471         break;
0472     case STV0900_SERIAL_CONT_CLOCK:
0473         stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
0474         stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
0475         break;
0476     default:
0477         break;
0478     }
0479 
0480     switch (path2_ts) {
0481     case STV0900_PARALLEL_PUNCT_CLOCK:
0482         stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
0483         stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
0484         break;
0485     case STV0900_DVBCI_CLOCK:
0486         stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
0487         stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
0488         break;
0489     case STV0900_SERIAL_PUNCT_CLOCK:
0490         stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
0491         stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
0492         break;
0493     case STV0900_SERIAL_CONT_CLOCK:
0494         stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
0495         stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
0496         break;
0497     default:
0498         break;
0499     }
0500 
0501     stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
0502     stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
0503     stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
0504     stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
0505 }
0506 
0507 void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
0508                             u32 bandwidth)
0509 {
0510     struct dvb_frontend_ops *frontend_ops = NULL;
0511     struct dvb_tuner_ops *tuner_ops = NULL;
0512 
0513     frontend_ops = &fe->ops;
0514     tuner_ops = &frontend_ops->tuner_ops;
0515 
0516     if (tuner_ops->set_frequency) {
0517         if ((tuner_ops->set_frequency(fe, frequency)) < 0)
0518             dprintk("%s: Invalid parameter\n", __func__);
0519         else
0520             dprintk("%s: Frequency=%d\n", __func__, frequency);
0521 
0522     }
0523 
0524     if (tuner_ops->set_bandwidth) {
0525         if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
0526             dprintk("%s: Invalid parameter\n", __func__);
0527         else
0528             dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
0529 
0530     }
0531 }
0532 
0533 void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
0534 {
0535     struct dvb_frontend_ops *frontend_ops = NULL;
0536     struct dvb_tuner_ops *tuner_ops = NULL;
0537 
0538     frontend_ops = &fe->ops;
0539     tuner_ops = &frontend_ops->tuner_ops;
0540 
0541     if (tuner_ops->set_bandwidth) {
0542         if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
0543             dprintk("%s: Invalid parameter\n", __func__);
0544         else
0545             dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
0546 
0547     }
0548 }
0549 
0550 u32 stv0900_get_freq_auto(struct stv0900_internal *intp, int demod)
0551 {
0552     u32 freq, round;
0553     /*  Formulat :
0554     Tuner_Frequency(MHz)    = Regs / 64
0555     Tuner_granularity(MHz)  = Regs / 2048
0556     real_Tuner_Frequency    = Tuner_Frequency(MHz) - Tuner_granularity(MHz)
0557     */
0558     freq = (stv0900_get_bits(intp, TUN_RFFREQ2) << 10) +
0559         (stv0900_get_bits(intp, TUN_RFFREQ1) << 2) +
0560         stv0900_get_bits(intp, TUN_RFFREQ0);
0561 
0562     freq = (freq * 1000) / 64;
0563 
0564     round = (stv0900_get_bits(intp, TUN_RFRESTE1) >> 2) +
0565         stv0900_get_bits(intp, TUN_RFRESTE0);
0566 
0567     round = (round * 1000) / 2048;
0568 
0569     return freq + round;
0570 }
0571 
0572 void stv0900_set_tuner_auto(struct stv0900_internal *intp, u32 Frequency,
0573                         u32 Bandwidth, int demod)
0574 {
0575     u32 tunerFrequency;
0576     /* Formulat:
0577     Tuner_frequency_reg= Frequency(MHz)*64
0578     */
0579     tunerFrequency = (Frequency * 64) / 1000;
0580 
0581     stv0900_write_bits(intp, TUN_RFFREQ2, (tunerFrequency >> 10));
0582     stv0900_write_bits(intp, TUN_RFFREQ1, (tunerFrequency >> 2) & 0xff);
0583     stv0900_write_bits(intp, TUN_RFFREQ0, (tunerFrequency & 0x03));
0584     /* Low Pass Filter = BW /2 (MHz)*/
0585     stv0900_write_bits(intp, TUN_BW, Bandwidth / 2000000);
0586     /* Tuner Write trig */
0587     stv0900_write_reg(intp, TNRLD, 1);
0588 }
0589 
0590 static s32 stv0900_get_rf_level(struct stv0900_internal *intp,
0591                 const struct stv0900_table *lookup,
0592                 enum fe_stv0900_demod_num demod)
0593 {
0594     s32 agc_gain = 0,
0595         imin,
0596         imax,
0597         i,
0598         rf_lvl = 0;
0599 
0600     dprintk("%s\n", __func__);
0601 
0602     if ((lookup == NULL) || (lookup->size <= 0))
0603         return 0;
0604 
0605     agc_gain = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
0606                 stv0900_get_bits(intp, AGCIQ_VALUE0));
0607 
0608     imin = 0;
0609     imax = lookup->size - 1;
0610     if (INRANGE(lookup->table[imin].regval, agc_gain,
0611                     lookup->table[imax].regval)) {
0612         while ((imax - imin) > 1) {
0613             i = (imax + imin) >> 1;
0614 
0615             if (INRANGE(lookup->table[imin].regval,
0616                     agc_gain,
0617                     lookup->table[i].regval))
0618                 imax = i;
0619             else
0620                 imin = i;
0621         }
0622 
0623         rf_lvl = (s32)agc_gain - lookup->table[imin].regval;
0624         rf_lvl *= (lookup->table[imax].realval -
0625                 lookup->table[imin].realval);
0626         rf_lvl /= (lookup->table[imax].regval -
0627                 lookup->table[imin].regval);
0628         rf_lvl += lookup->table[imin].realval;
0629     } else if (agc_gain > lookup->table[0].regval)
0630         rf_lvl = 5;
0631     else if (agc_gain < lookup->table[lookup->size-1].regval)
0632         rf_lvl = -100;
0633 
0634     dprintk("%s: RFLevel = %d\n", __func__, rf_lvl);
0635 
0636     return rf_lvl;
0637 }
0638 
0639 static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
0640 {
0641     struct stv0900_state *state = fe->demodulator_priv;
0642     struct stv0900_internal *internal = state->internal;
0643     s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf,
0644                                 state->demod);
0645 
0646     rflevel = (rflevel + 100) * (65535 / 70);
0647     if (rflevel < 0)
0648         rflevel = 0;
0649 
0650     if (rflevel > 65535)
0651         rflevel = 65535;
0652 
0653     *strength = rflevel;
0654 
0655     return 0;
0656 }
0657 
0658 static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
0659                     const struct stv0900_table *lookup)
0660 {
0661     struct stv0900_state *state = fe->demodulator_priv;
0662     struct stv0900_internal *intp = state->internal;
0663     enum fe_stv0900_demod_num demod = state->demod;
0664 
0665     s32 c_n = -100,
0666         regval,
0667         imin,
0668         imax,
0669         i,
0670         noise_field1,
0671         noise_field0;
0672 
0673     dprintk("%s\n", __func__);
0674 
0675     if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
0676         noise_field1 = NOSPLHT_NORMED1;
0677         noise_field0 = NOSPLHT_NORMED0;
0678     } else {
0679         noise_field1 = NOSDATAT_NORMED1;
0680         noise_field0 = NOSDATAT_NORMED0;
0681     }
0682 
0683     if (stv0900_get_bits(intp, LOCK_DEFINITIF)) {
0684         if ((lookup != NULL) && lookup->size) {
0685             regval = 0;
0686             msleep(5);
0687             for (i = 0; i < 16; i++) {
0688                 regval += MAKEWORD(stv0900_get_bits(intp,
0689                                 noise_field1),
0690                         stv0900_get_bits(intp,
0691                                 noise_field0));
0692                 msleep(1);
0693             }
0694 
0695             regval /= 16;
0696             imin = 0;
0697             imax = lookup->size - 1;
0698             if (INRANGE(lookup->table[imin].regval,
0699                     regval,
0700                     lookup->table[imax].regval)) {
0701                 while ((imax - imin) > 1) {
0702                     i = (imax + imin) >> 1;
0703                     if (INRANGE(lookup->table[imin].regval,
0704                             regval,
0705                             lookup->table[i].regval))
0706                         imax = i;
0707                     else
0708                         imin = i;
0709                 }
0710 
0711                 c_n = ((regval - lookup->table[imin].regval)
0712                         * (lookup->table[imax].realval
0713                         - lookup->table[imin].realval)
0714                         / (lookup->table[imax].regval
0715                         - lookup->table[imin].regval))
0716                         + lookup->table[imin].realval;
0717             } else if (regval < lookup->table[imin].regval)
0718                 c_n = 1000;
0719         }
0720     }
0721 
0722     return c_n;
0723 }
0724 
0725 static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
0726 {
0727     struct stv0900_state *state = fe->demodulator_priv;
0728     struct stv0900_internal *intp = state->internal;
0729     enum fe_stv0900_demod_num demod = state->demod;
0730     u8 err_val1, err_val0;
0731     u32 header_err_val = 0;
0732 
0733     *ucblocks = 0x0;
0734     if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
0735         /* DVB-S2 delineator errors count */
0736 
0737         /* retrieving number for errnous headers */
0738         err_val1 = stv0900_read_reg(intp, BBFCRCKO1);
0739         err_val0 = stv0900_read_reg(intp, BBFCRCKO0);
0740         header_err_val = (err_val1 << 8) | err_val0;
0741 
0742         /* retrieving number for errnous packets */
0743         err_val1 = stv0900_read_reg(intp, UPCRCKO1);
0744         err_val0 = stv0900_read_reg(intp, UPCRCKO0);
0745         *ucblocks = (err_val1 << 8) | err_val0;
0746         *ucblocks += header_err_val;
0747     }
0748 
0749     return 0;
0750 }
0751 
0752 static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
0753 {
0754     s32 snrlcl = stv0900_carr_get_quality(fe,
0755             (const struct stv0900_table *)&stv0900_s2_cn);
0756     snrlcl = (snrlcl + 30) * 384;
0757     if (snrlcl < 0)
0758         snrlcl = 0;
0759 
0760     if (snrlcl > 65535)
0761         snrlcl = 65535;
0762 
0763     *snr = snrlcl;
0764 
0765     return 0;
0766 }
0767 
0768 static u32 stv0900_get_ber(struct stv0900_internal *intp,
0769                 enum fe_stv0900_demod_num demod)
0770 {
0771     u32 ber = 10000000, i;
0772     s32 demod_state;
0773 
0774     demod_state = stv0900_get_bits(intp, HEADER_MODE);
0775 
0776     switch (demod_state) {
0777     case STV0900_SEARCH:
0778     case STV0900_PLH_DETECTED:
0779     default:
0780         ber = 10000000;
0781         break;
0782     case STV0900_DVBS_FOUND:
0783         ber = 0;
0784         for (i = 0; i < 5; i++) {
0785             msleep(5);
0786             ber += stv0900_get_err_count(intp, 0, demod);
0787         }
0788 
0789         ber /= 5;
0790         if (stv0900_get_bits(intp, PRFVIT)) {
0791             ber *= 9766;
0792             ber = ber >> 13;
0793         }
0794 
0795         break;
0796     case STV0900_DVBS2_FOUND:
0797         ber = 0;
0798         for (i = 0; i < 5; i++) {
0799             msleep(5);
0800             ber += stv0900_get_err_count(intp, 0, demod);
0801         }
0802 
0803         ber /= 5;
0804         if (stv0900_get_bits(intp, PKTDELIN_LOCK)) {
0805             ber *= 9766;
0806             ber = ber >> 13;
0807         }
0808 
0809         break;
0810     }
0811 
0812     return ber;
0813 }
0814 
0815 static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
0816 {
0817     struct stv0900_state *state = fe->demodulator_priv;
0818     struct stv0900_internal *internal = state->internal;
0819 
0820     *ber = stv0900_get_ber(internal, state->demod);
0821 
0822     return 0;
0823 }
0824 
0825 int stv0900_get_demod_lock(struct stv0900_internal *intp,
0826             enum fe_stv0900_demod_num demod, s32 time_out)
0827 {
0828     s32 timer = 0,
0829         lock = 0;
0830 
0831     enum fe_stv0900_search_state    dmd_state;
0832 
0833     while ((timer < time_out) && (lock == 0)) {
0834         dmd_state = stv0900_get_bits(intp, HEADER_MODE);
0835         dprintk("Demod State = %d\n", dmd_state);
0836         switch (dmd_state) {
0837         case STV0900_SEARCH:
0838         case STV0900_PLH_DETECTED:
0839         default:
0840             lock = 0;
0841             break;
0842         case STV0900_DVBS2_FOUND:
0843         case STV0900_DVBS_FOUND:
0844             lock = stv0900_get_bits(intp, LOCK_DEFINITIF);
0845             break;
0846         }
0847 
0848         if (lock == 0)
0849             msleep(10);
0850 
0851         timer += 10;
0852     }
0853 
0854     if (lock)
0855         dprintk("DEMOD LOCK OK\n");
0856     else
0857         dprintk("DEMOD LOCK FAIL\n");
0858 
0859     return lock;
0860 }
0861 
0862 void stv0900_stop_all_s2_modcod(struct stv0900_internal *intp,
0863                 enum fe_stv0900_demod_num demod)
0864 {
0865     s32 regflist,
0866     i;
0867 
0868     dprintk("%s\n", __func__);
0869 
0870     regflist = MODCODLST0;
0871 
0872     for (i = 0; i < 16; i++)
0873         stv0900_write_reg(intp, regflist + i, 0xff);
0874 }
0875 
0876 void stv0900_activate_s2_modcod(struct stv0900_internal *intp,
0877                 enum fe_stv0900_demod_num demod)
0878 {
0879     u32 matype,
0880         mod_code,
0881         fmod,
0882         reg_index,
0883         field_index;
0884 
0885     dprintk("%s\n", __func__);
0886 
0887     if (intp->chip_id <= 0x11) {
0888         msleep(5);
0889 
0890         mod_code = stv0900_read_reg(intp, PLHMODCOD);
0891         matype = mod_code & 0x3;
0892         mod_code = (mod_code & 0x7f) >> 2;
0893 
0894         reg_index = MODCODLSTF - mod_code / 2;
0895         field_index = mod_code % 2;
0896 
0897         switch (matype) {
0898         case 0:
0899         default:
0900             fmod = 14;
0901             break;
0902         case 1:
0903             fmod = 13;
0904             break;
0905         case 2:
0906             fmod = 11;
0907             break;
0908         case 3:
0909             fmod = 7;
0910             break;
0911         }
0912 
0913         if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
0914                         && (matype <= 1)) {
0915             if (field_index == 0)
0916                 stv0900_write_reg(intp, reg_index,
0917                             0xf0 | fmod);
0918             else
0919                 stv0900_write_reg(intp, reg_index,
0920                             (fmod << 4) | 0xf);
0921         }
0922 
0923     } else if (intp->chip_id >= 0x12) {
0924         for (reg_index = 0; reg_index < 7; reg_index++)
0925             stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff);
0926 
0927         stv0900_write_reg(intp, MODCODLSTE, 0xff);
0928         stv0900_write_reg(intp, MODCODLSTF, 0xcf);
0929         for (reg_index = 0; reg_index < 8; reg_index++)
0930             stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc);
0931 
0932 
0933     }
0934 }
0935 
0936 void stv0900_activate_s2_modcod_single(struct stv0900_internal *intp,
0937                     enum fe_stv0900_demod_num demod)
0938 {
0939     u32 reg_index;
0940 
0941     dprintk("%s\n", __func__);
0942 
0943     stv0900_write_reg(intp, MODCODLST0, 0xff);
0944     stv0900_write_reg(intp, MODCODLST1, 0xf0);
0945     stv0900_write_reg(intp, MODCODLSTF, 0x0f);
0946     for (reg_index = 0; reg_index < 13; reg_index++)
0947         stv0900_write_reg(intp, MODCODLST2 + reg_index, 0);
0948 
0949 }
0950 
0951 static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
0952 {
0953     return DVBFE_ALGO_CUSTOM;
0954 }
0955 
0956 void stv0900_start_search(struct stv0900_internal *intp,
0957                 enum fe_stv0900_demod_num demod)
0958 {
0959     u32 freq;
0960     s16 freq_s16 ;
0961 
0962     stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
0963     if (intp->chip_id == 0x10)
0964         stv0900_write_reg(intp, CORRELEXP, 0xaa);
0965 
0966     if (intp->chip_id < 0x20)
0967         stv0900_write_reg(intp, CARHDR, 0x55);
0968 
0969     if (intp->chip_id <= 0x20) {
0970         if (intp->symbol_rate[0] <= 5000000) {
0971             stv0900_write_reg(intp, CARCFG, 0x44);
0972             stv0900_write_reg(intp, CFRUP1, 0x0f);
0973             stv0900_write_reg(intp, CFRUP0, 0xff);
0974             stv0900_write_reg(intp, CFRLOW1, 0xf0);
0975             stv0900_write_reg(intp, CFRLOW0, 0x00);
0976             stv0900_write_reg(intp, RTCS2, 0x68);
0977         } else {
0978             stv0900_write_reg(intp, CARCFG, 0xc4);
0979             stv0900_write_reg(intp, RTCS2, 0x44);
0980         }
0981 
0982     } else { /*cut 3.0 above*/
0983         if (intp->symbol_rate[demod] <= 5000000)
0984             stv0900_write_reg(intp, RTCS2, 0x68);
0985         else
0986             stv0900_write_reg(intp, RTCS2, 0x44);
0987 
0988         stv0900_write_reg(intp, CARCFG, 0x46);
0989         if (intp->srch_algo[demod] == STV0900_WARM_START) {
0990             freq = 1000 << 16;
0991             freq /= (intp->mclk / 1000);
0992             freq_s16 = (s16)freq;
0993         } else {
0994             freq = (intp->srch_range[demod] / 2000);
0995             if (intp->symbol_rate[demod] <= 5000000)
0996                 freq += 80;
0997             else
0998                 freq += 600;
0999 
1000             freq = freq << 16;
1001             freq /= (intp->mclk / 1000);
1002             freq_s16 = (s16)freq;
1003         }
1004 
1005         stv0900_write_bits(intp, CFR_UP1, MSB(freq_s16));
1006         stv0900_write_bits(intp, CFR_UP0, LSB(freq_s16));
1007         freq_s16 *= (-1);
1008         stv0900_write_bits(intp, CFR_LOW1, MSB(freq_s16));
1009         stv0900_write_bits(intp, CFR_LOW0, LSB(freq_s16));
1010     }
1011 
1012     stv0900_write_reg(intp, CFRINIT1, 0);
1013     stv0900_write_reg(intp, CFRINIT0, 0);
1014 
1015     if (intp->chip_id >= 0x20) {
1016         stv0900_write_reg(intp, EQUALCFG, 0x41);
1017         stv0900_write_reg(intp, FFECFG, 0x41);
1018 
1019         if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
1020             (intp->srch_standard[demod] == STV0900_SEARCH_DSS) ||
1021             (intp->srch_standard[demod] == STV0900_AUTO_SEARCH)) {
1022             stv0900_write_reg(intp, VITSCALE,
1023                                 0x82);
1024             stv0900_write_reg(intp, VAVSRVIT, 0x0);
1025         }
1026     }
1027 
1028     stv0900_write_reg(intp, SFRSTEP, 0x00);
1029     stv0900_write_reg(intp, TMGTHRISE, 0xe0);
1030     stv0900_write_reg(intp, TMGTHFALL, 0xc0);
1031     stv0900_write_bits(intp, SCAN_ENABLE, 0);
1032     stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1033     stv0900_write_bits(intp, S1S2_SEQUENTIAL, 0);
1034     stv0900_write_reg(intp, RTC, 0x88);
1035     if (intp->chip_id >= 0x20) {
1036         if (intp->symbol_rate[demod] < 2000000) {
1037             if (intp->chip_id <= 0x20)
1038                 stv0900_write_reg(intp, CARFREQ, 0x39);
1039             else  /*cut 3.0*/
1040                 stv0900_write_reg(intp, CARFREQ, 0x89);
1041 
1042             stv0900_write_reg(intp, CARHDR, 0x40);
1043         } else if (intp->symbol_rate[demod] < 10000000) {
1044             stv0900_write_reg(intp, CARFREQ, 0x4c);
1045             stv0900_write_reg(intp, CARHDR, 0x20);
1046         } else {
1047             stv0900_write_reg(intp, CARFREQ, 0x4b);
1048             stv0900_write_reg(intp, CARHDR, 0x20);
1049         }
1050 
1051     } else {
1052         if (intp->symbol_rate[demod] < 10000000)
1053             stv0900_write_reg(intp, CARFREQ, 0xef);
1054         else
1055             stv0900_write_reg(intp, CARFREQ, 0xed);
1056     }
1057 
1058     switch (intp->srch_algo[demod]) {
1059     case STV0900_WARM_START:
1060         stv0900_write_reg(intp, DMDISTATE, 0x1f);
1061         stv0900_write_reg(intp, DMDISTATE, 0x18);
1062         break;
1063     case STV0900_COLD_START:
1064         stv0900_write_reg(intp, DMDISTATE, 0x1f);
1065         stv0900_write_reg(intp, DMDISTATE, 0x15);
1066         break;
1067     default:
1068         break;
1069     }
1070 }
1071 
1072 u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
1073                             s32 pilot, u8 chip_id)
1074 {
1075     u8 aclc_value = 0x29;
1076     s32 i, cllas2_size;
1077     const struct stv0900_car_loop_optim *cls2, *cllqs2, *cllas2;
1078 
1079     dprintk("%s\n", __func__);
1080 
1081     if (chip_id <= 0x12) {
1082         cls2 = FE_STV0900_S2CarLoop;
1083         cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
1084         cllas2 = FE_STV0900_S2APSKCarLoopCut30;
1085         cllas2_size = ARRAY_SIZE(FE_STV0900_S2APSKCarLoopCut30);
1086     } else if (chip_id == 0x20) {
1087         cls2 = FE_STV0900_S2CarLoopCut20;
1088         cllqs2 = FE_STV0900_S2LowQPCarLoopCut20;
1089         cllas2 = FE_STV0900_S2APSKCarLoopCut20;
1090         cllas2_size = ARRAY_SIZE(FE_STV0900_S2APSKCarLoopCut20);
1091     } else {
1092         cls2 = FE_STV0900_S2CarLoopCut30;
1093         cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
1094         cllas2 = FE_STV0900_S2APSKCarLoopCut30;
1095         cllas2_size = ARRAY_SIZE(FE_STV0900_S2APSKCarLoopCut30);
1096     }
1097 
1098     if (modcode < STV0900_QPSK_12) {
1099         i = 0;
1100         while ((i < 3) && (modcode != cllqs2[i].modcode))
1101             i++;
1102 
1103         if (i >= 3)
1104             i = 2;
1105     } else {
1106         i = 0;
1107         while ((i < 14) && (modcode != cls2[i].modcode))
1108             i++;
1109 
1110         if (i >= 14) {
1111             i = 0;
1112             while ((i < 11) && (modcode != cllas2[i].modcode))
1113                 i++;
1114 
1115             if (i >= 11)
1116                 i = 10;
1117         }
1118     }
1119 
1120     if (modcode <= STV0900_QPSK_25) {
1121         if (pilot) {
1122             if (srate <= 3000000)
1123                 aclc_value = cllqs2[i].car_loop_pilots_on_2;
1124             else if (srate <= 7000000)
1125                 aclc_value = cllqs2[i].car_loop_pilots_on_5;
1126             else if (srate <= 15000000)
1127                 aclc_value = cllqs2[i].car_loop_pilots_on_10;
1128             else if (srate <= 25000000)
1129                 aclc_value = cllqs2[i].car_loop_pilots_on_20;
1130             else
1131                 aclc_value = cllqs2[i].car_loop_pilots_on_30;
1132         } else {
1133             if (srate <= 3000000)
1134                 aclc_value = cllqs2[i].car_loop_pilots_off_2;
1135             else if (srate <= 7000000)
1136                 aclc_value = cllqs2[i].car_loop_pilots_off_5;
1137             else if (srate <= 15000000)
1138                 aclc_value = cllqs2[i].car_loop_pilots_off_10;
1139             else if (srate <= 25000000)
1140                 aclc_value = cllqs2[i].car_loop_pilots_off_20;
1141             else
1142                 aclc_value = cllqs2[i].car_loop_pilots_off_30;
1143         }
1144 
1145     } else if (modcode <= STV0900_8PSK_910) {
1146         if (pilot) {
1147             if (srate <= 3000000)
1148                 aclc_value = cls2[i].car_loop_pilots_on_2;
1149             else if (srate <= 7000000)
1150                 aclc_value = cls2[i].car_loop_pilots_on_5;
1151             else if (srate <= 15000000)
1152                 aclc_value = cls2[i].car_loop_pilots_on_10;
1153             else if (srate <= 25000000)
1154                 aclc_value = cls2[i].car_loop_pilots_on_20;
1155             else
1156                 aclc_value = cls2[i].car_loop_pilots_on_30;
1157         } else {
1158             if (srate <= 3000000)
1159                 aclc_value = cls2[i].car_loop_pilots_off_2;
1160             else if (srate <= 7000000)
1161                 aclc_value = cls2[i].car_loop_pilots_off_5;
1162             else if (srate <= 15000000)
1163                 aclc_value = cls2[i].car_loop_pilots_off_10;
1164             else if (srate <= 25000000)
1165                 aclc_value = cls2[i].car_loop_pilots_off_20;
1166             else
1167                 aclc_value = cls2[i].car_loop_pilots_off_30;
1168         }
1169 
1170     } else if (i < cllas2_size) {
1171         if (srate <= 3000000)
1172             aclc_value = cllas2[i].car_loop_pilots_on_2;
1173         else if (srate <= 7000000)
1174             aclc_value = cllas2[i].car_loop_pilots_on_5;
1175         else if (srate <= 15000000)
1176             aclc_value = cllas2[i].car_loop_pilots_on_10;
1177         else if (srate <= 25000000)
1178             aclc_value = cllas2[i].car_loop_pilots_on_20;
1179         else
1180             aclc_value = cllas2[i].car_loop_pilots_on_30;
1181     }
1182 
1183     return aclc_value;
1184 }
1185 
1186 u8 stv0900_get_optim_short_carr_loop(s32 srate,
1187                 enum fe_stv0900_modulation modulation,
1188                 u8 chip_id)
1189 {
1190     const struct stv0900_short_frames_car_loop_optim *s2scl;
1191     const struct stv0900_short_frames_car_loop_optim_vs_mod *s2sclc30;
1192     s32 mod_index = 0;
1193     u8 aclc_value = 0x0b;
1194 
1195     dprintk("%s\n", __func__);
1196 
1197     s2scl = FE_STV0900_S2ShortCarLoop;
1198     s2sclc30 = FE_STV0900_S2ShortCarLoopCut30;
1199 
1200     switch (modulation) {
1201     case STV0900_QPSK:
1202     default:
1203         mod_index = 0;
1204         break;
1205     case STV0900_8PSK:
1206         mod_index = 1;
1207         break;
1208     case STV0900_16APSK:
1209         mod_index = 2;
1210         break;
1211     case STV0900_32APSK:
1212         mod_index = 3;
1213         break;
1214     }
1215 
1216     if (chip_id >= 0x30) {
1217         if (srate <= 3000000)
1218             aclc_value = s2sclc30[mod_index].car_loop_2;
1219         else if (srate <= 7000000)
1220             aclc_value = s2sclc30[mod_index].car_loop_5;
1221         else if (srate <= 15000000)
1222             aclc_value = s2sclc30[mod_index].car_loop_10;
1223         else if (srate <= 25000000)
1224             aclc_value = s2sclc30[mod_index].car_loop_20;
1225         else
1226             aclc_value = s2sclc30[mod_index].car_loop_30;
1227 
1228     } else if (chip_id >= 0x20) {
1229         if (srate <= 3000000)
1230             aclc_value = s2scl[mod_index].car_loop_cut20_2;
1231         else if (srate <= 7000000)
1232             aclc_value = s2scl[mod_index].car_loop_cut20_5;
1233         else if (srate <= 15000000)
1234             aclc_value = s2scl[mod_index].car_loop_cut20_10;
1235         else if (srate <= 25000000)
1236             aclc_value = s2scl[mod_index].car_loop_cut20_20;
1237         else
1238             aclc_value = s2scl[mod_index].car_loop_cut20_30;
1239 
1240     } else {
1241         if (srate <= 3000000)
1242             aclc_value = s2scl[mod_index].car_loop_cut12_2;
1243         else if (srate <= 7000000)
1244             aclc_value = s2scl[mod_index].car_loop_cut12_5;
1245         else if (srate <= 15000000)
1246             aclc_value = s2scl[mod_index].car_loop_cut12_10;
1247         else if (srate <= 25000000)
1248             aclc_value = s2scl[mod_index].car_loop_cut12_20;
1249         else
1250             aclc_value = s2scl[mod_index].car_loop_cut12_30;
1251 
1252     }
1253 
1254     return aclc_value;
1255 }
1256 
1257 static
1258 enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *intp,
1259                     enum fe_stv0900_demod_mode LDPC_Mode,
1260                     enum fe_stv0900_demod_num demod)
1261 {
1262     s32 reg_ind;
1263 
1264     dprintk("%s\n", __func__);
1265 
1266     switch (LDPC_Mode) {
1267     case STV0900_DUAL:
1268     default:
1269         if ((intp->demod_mode != STV0900_DUAL)
1270             || (stv0900_get_bits(intp, F0900_DDEMOD) != 1)) {
1271             stv0900_write_reg(intp, R0900_GENCFG, 0x1d);
1272 
1273             intp->demod_mode = STV0900_DUAL;
1274 
1275             stv0900_write_bits(intp, F0900_FRESFEC, 1);
1276             stv0900_write_bits(intp, F0900_FRESFEC, 0);
1277 
1278             for (reg_ind = 0; reg_ind < 7; reg_ind++)
1279                 stv0900_write_reg(intp,
1280                         R0900_P1_MODCODLST0 + reg_ind,
1281                         0xff);
1282             for (reg_ind = 0; reg_ind < 8; reg_ind++)
1283                 stv0900_write_reg(intp,
1284                         R0900_P1_MODCODLST7 + reg_ind,
1285                         0xcc);
1286 
1287             stv0900_write_reg(intp, R0900_P1_MODCODLSTE, 0xff);
1288             stv0900_write_reg(intp, R0900_P1_MODCODLSTF, 0xcf);
1289 
1290             for (reg_ind = 0; reg_ind < 7; reg_ind++)
1291                 stv0900_write_reg(intp,
1292                         R0900_P2_MODCODLST0 + reg_ind,
1293                         0xff);
1294             for (reg_ind = 0; reg_ind < 8; reg_ind++)
1295                 stv0900_write_reg(intp,
1296                         R0900_P2_MODCODLST7 + reg_ind,
1297                         0xcc);
1298 
1299             stv0900_write_reg(intp, R0900_P2_MODCODLSTE, 0xff);
1300             stv0900_write_reg(intp, R0900_P2_MODCODLSTF, 0xcf);
1301         }
1302 
1303         break;
1304     case STV0900_SINGLE:
1305         if (demod == STV0900_DEMOD_2) {
1306             stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_1);
1307             stv0900_activate_s2_modcod_single(intp,
1308                             STV0900_DEMOD_2);
1309             stv0900_write_reg(intp, R0900_GENCFG, 0x06);
1310         } else {
1311             stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_2);
1312             stv0900_activate_s2_modcod_single(intp,
1313                             STV0900_DEMOD_1);
1314             stv0900_write_reg(intp, R0900_GENCFG, 0x04);
1315         }
1316 
1317         intp->demod_mode = STV0900_SINGLE;
1318 
1319         stv0900_write_bits(intp, F0900_FRESFEC, 1);
1320         stv0900_write_bits(intp, F0900_FRESFEC, 0);
1321         stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 1);
1322         stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 0);
1323         stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 1);
1324         stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 0);
1325         break;
1326     }
1327 
1328     return STV0900_NO_ERROR;
1329 }
1330 
1331 static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
1332                     struct stv0900_init_params *p_init)
1333 {
1334     struct stv0900_state *state = fe->demodulator_priv;
1335     enum fe_stv0900_error error = STV0900_NO_ERROR;
1336     enum fe_stv0900_error demodError = STV0900_NO_ERROR;
1337     struct stv0900_internal *intp = NULL;
1338     int selosci, i;
1339 
1340     struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
1341                         state->config->demod_address);
1342 
1343     dprintk("%s\n", __func__);
1344 
1345     if ((temp_int != NULL) && (p_init->demod_mode == STV0900_DUAL)) {
1346         state->internal = temp_int->internal;
1347         (state->internal->dmds_used)++;
1348         dprintk("%s: Find Internal Structure!\n", __func__);
1349         return STV0900_NO_ERROR;
1350     } else {
1351         state->internal = kmalloc(sizeof(struct stv0900_internal),
1352                                 GFP_KERNEL);
1353         if (state->internal == NULL)
1354             return STV0900_INVALID_HANDLE;
1355         temp_int = append_internal(state->internal);
1356         if (temp_int == NULL) {
1357             kfree(state->internal);
1358             state->internal = NULL;
1359             return STV0900_INVALID_HANDLE;
1360         }
1361         state->internal->dmds_used = 1;
1362         state->internal->i2c_adap = state->i2c_adap;
1363         state->internal->i2c_addr = state->config->demod_address;
1364         state->internal->clkmode = state->config->clkmode;
1365         state->internal->errs = STV0900_NO_ERROR;
1366         dprintk("%s: Create New Internal Structure!\n", __func__);
1367     }
1368 
1369     if (state->internal == NULL) {
1370         error = STV0900_INVALID_HANDLE;
1371         return error;
1372     }
1373 
1374     demodError = stv0900_initialize(state->internal);
1375     if (demodError == STV0900_NO_ERROR) {
1376             error = STV0900_NO_ERROR;
1377     } else {
1378         if (demodError == STV0900_INVALID_HANDLE)
1379             error = STV0900_INVALID_HANDLE;
1380         else
1381             error = STV0900_I2C_ERROR;
1382 
1383         return error;
1384     }
1385 
1386     intp = state->internal;
1387 
1388     intp->demod_mode = p_init->demod_mode;
1389     stv0900_st_dvbs2_single(intp, intp->demod_mode, STV0900_DEMOD_1);
1390     intp->chip_id = stv0900_read_reg(intp, R0900_MID);
1391     intp->rolloff = p_init->rolloff;
1392     intp->quartz = p_init->dmd_ref_clk;
1393 
1394     stv0900_write_bits(intp, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
1395     stv0900_write_bits(intp, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
1396 
1397     intp->ts_config = p_init->ts_config;
1398     if (intp->ts_config == NULL)
1399         stv0900_set_ts_parallel_serial(intp,
1400                 p_init->path1_ts_clock,
1401                 p_init->path2_ts_clock);
1402     else {
1403         for (i = 0; intp->ts_config[i].addr != 0xffff; i++)
1404             stv0900_write_reg(intp,
1405                     intp->ts_config[i].addr,
1406                     intp->ts_config[i].val);
1407 
1408         stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
1409         stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
1410         stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
1411         stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
1412     }
1413 
1414     intp->tuner_type[0] = p_init->tuner1_type;
1415     intp->tuner_type[1] = p_init->tuner2_type;
1416     /* tuner init */
1417     switch (p_init->tuner1_type) {
1418     case 3: /*FE_AUTO_STB6100:*/
1419         stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x3c);
1420         stv0900_write_reg(intp, R0900_P1_TNRCFG2, 0x86);
1421         stv0900_write_reg(intp, R0900_P1_TNRCFG3, 0x18);
1422         stv0900_write_reg(intp, R0900_P1_TNRXTAL, 27); /* 27MHz */
1423         stv0900_write_reg(intp, R0900_P1_TNRSTEPS, 0x05);
1424         stv0900_write_reg(intp, R0900_P1_TNRGAIN, 0x17);
1425         stv0900_write_reg(intp, R0900_P1_TNRADJ, 0x1f);
1426         stv0900_write_reg(intp, R0900_P1_TNRCTL2, 0x0);
1427         stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 3);
1428         break;
1429     /* case FE_SW_TUNER: */
1430     default:
1431         stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 6);
1432         break;
1433     }
1434 
1435     stv0900_write_bits(intp, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
1436     switch (p_init->tuner1_adc) {
1437     case 1:
1438         stv0900_write_reg(intp, R0900_TSTTNR1, 0x26);
1439         break;
1440     default:
1441         break;
1442     }
1443 
1444     stv0900_write_reg(intp, R0900_P1_TNRLD, 1); /* hw tuner */
1445 
1446     /* tuner init */
1447     switch (p_init->tuner2_type) {
1448     case 3: /*FE_AUTO_STB6100:*/
1449         stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x3c);
1450         stv0900_write_reg(intp, R0900_P2_TNRCFG2, 0x86);
1451         stv0900_write_reg(intp, R0900_P2_TNRCFG3, 0x18);
1452         stv0900_write_reg(intp, R0900_P2_TNRXTAL, 27); /* 27MHz */
1453         stv0900_write_reg(intp, R0900_P2_TNRSTEPS, 0x05);
1454         stv0900_write_reg(intp, R0900_P2_TNRGAIN, 0x17);
1455         stv0900_write_reg(intp, R0900_P2_TNRADJ, 0x1f);
1456         stv0900_write_reg(intp, R0900_P2_TNRCTL2, 0x0);
1457         stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 3);
1458         break;
1459     /* case FE_SW_TUNER: */
1460     default:
1461         stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 6);
1462         break;
1463     }
1464 
1465     stv0900_write_bits(intp, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
1466     switch (p_init->tuner2_adc) {
1467     case 1:
1468         stv0900_write_reg(intp, R0900_TSTTNR3, 0x26);
1469         break;
1470     default:
1471         break;
1472     }
1473 
1474     stv0900_write_reg(intp, R0900_P2_TNRLD, 1); /* hw tuner */
1475 
1476     stv0900_write_bits(intp, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inv);
1477     stv0900_write_bits(intp, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inv);
1478     stv0900_set_mclk(intp, 135000000);
1479     msleep(3);
1480 
1481     switch (intp->clkmode) {
1482     case 0:
1483     case 2:
1484         stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | intp->clkmode);
1485         break;
1486     default:
1487         selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
1488         stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | selosci);
1489         break;
1490     }
1491     msleep(3);
1492 
1493     intp->mclk = stv0900_get_mclk_freq(intp, intp->quartz);
1494     if (intp->errs)
1495         error = STV0900_I2C_ERROR;
1496 
1497     return error;
1498 }
1499 
1500 static int stv0900_status(struct stv0900_internal *intp,
1501                     enum fe_stv0900_demod_num demod)
1502 {
1503     enum fe_stv0900_search_state demod_state;
1504     int locked = FALSE;
1505     u8 tsbitrate0_val, tsbitrate1_val;
1506     s32 bitrate;
1507 
1508     demod_state = stv0900_get_bits(intp, HEADER_MODE);
1509     switch (demod_state) {
1510     case STV0900_SEARCH:
1511     case STV0900_PLH_DETECTED:
1512     default:
1513         locked = FALSE;
1514         break;
1515     case STV0900_DVBS2_FOUND:
1516         locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
1517                 stv0900_get_bits(intp, PKTDELIN_LOCK) &&
1518                 stv0900_get_bits(intp, TSFIFO_LINEOK);
1519         break;
1520     case STV0900_DVBS_FOUND:
1521         locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
1522                 stv0900_get_bits(intp, LOCKEDVIT) &&
1523                 stv0900_get_bits(intp, TSFIFO_LINEOK);
1524         break;
1525     }
1526 
1527     dprintk("%s: locked = %d\n", __func__, locked);
1528 
1529     if (stvdebug) {
1530         /* Print TS bitrate */
1531         tsbitrate0_val = stv0900_read_reg(intp, TSBITRATE0);
1532         tsbitrate1_val = stv0900_read_reg(intp, TSBITRATE1);
1533         /* Formula Bit rate = Mclk * px_tsfifo_bitrate / 16384 */
1534         bitrate = (stv0900_get_mclk_freq(intp, intp->quartz)/1000000)
1535             * (tsbitrate1_val << 8 | tsbitrate0_val);
1536         bitrate /= 16384;
1537         dprintk("TS bitrate = %d Mbit/sec\n", bitrate);
1538     }
1539 
1540     return locked;
1541 }
1542 
1543 static int stv0900_set_mis(struct stv0900_internal *intp,
1544                 enum fe_stv0900_demod_num demod, int mis)
1545 {
1546     dprintk("%s\n", __func__);
1547 
1548     if (mis < 0 || mis > 255) {
1549         dprintk("Disable MIS filtering\n");
1550         stv0900_write_bits(intp, FILTER_EN, 0);
1551     } else {
1552         dprintk("Enable MIS filtering - %d\n", mis);
1553         stv0900_write_bits(intp, FILTER_EN, 1);
1554         stv0900_write_reg(intp, ISIENTRY, mis);
1555         stv0900_write_reg(intp, ISIBITENA, 0xff);
1556     }
1557 
1558     return STV0900_NO_ERROR;
1559 }
1560 
1561 
1562 static enum dvbfe_search stv0900_search(struct dvb_frontend *fe)
1563 {
1564     struct stv0900_state *state = fe->demodulator_priv;
1565     struct stv0900_internal *intp = state->internal;
1566     enum fe_stv0900_demod_num demod = state->demod;
1567     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1568 
1569     struct stv0900_search_params p_search;
1570     struct stv0900_signal_info p_result = intp->result[demod];
1571 
1572     enum fe_stv0900_error error = STV0900_NO_ERROR;
1573 
1574     dprintk("%s: ", __func__);
1575 
1576     if (!(INRANGE(100000, c->symbol_rate, 70000000)))
1577         return DVBFE_ALGO_SEARCH_FAILED;
1578 
1579     if (state->config->set_ts_params)
1580         state->config->set_ts_params(fe, 0);
1581 
1582     stv0900_set_mis(intp, demod, c->stream_id);
1583 
1584     p_result.locked = FALSE;
1585     p_search.path = demod;
1586     p_search.frequency = c->frequency;
1587     p_search.symbol_rate = c->symbol_rate;
1588     p_search.search_range = 10000000;
1589     p_search.fec = STV0900_FEC_UNKNOWN;
1590     p_search.standard = STV0900_AUTO_SEARCH;
1591     p_search.iq_inversion = STV0900_IQ_AUTO;
1592     p_search.search_algo = STV0900_BLIND_SEARCH;
1593     /* Speeds up DVB-S searching */
1594     if (c->delivery_system == SYS_DVBS)
1595         p_search.standard = STV0900_SEARCH_DVBS1;
1596 
1597     intp->srch_standard[demod] = p_search.standard;
1598     intp->symbol_rate[demod] = p_search.symbol_rate;
1599     intp->srch_range[demod] = p_search.search_range;
1600     intp->freq[demod] = p_search.frequency;
1601     intp->srch_algo[demod] = p_search.search_algo;
1602     intp->srch_iq_inv[demod] = p_search.iq_inversion;
1603     intp->fec[demod] = p_search.fec;
1604     if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
1605                 (intp->errs == STV0900_NO_ERROR)) {
1606         p_result.locked = intp->result[demod].locked;
1607         p_result.standard = intp->result[demod].standard;
1608         p_result.frequency = intp->result[demod].frequency;
1609         p_result.symbol_rate = intp->result[demod].symbol_rate;
1610         p_result.fec = intp->result[demod].fec;
1611         p_result.modcode = intp->result[demod].modcode;
1612         p_result.pilot = intp->result[demod].pilot;
1613         p_result.frame_len = intp->result[demod].frame_len;
1614         p_result.spectrum = intp->result[demod].spectrum;
1615         p_result.rolloff = intp->result[demod].rolloff;
1616         p_result.modulation = intp->result[demod].modulation;
1617     } else {
1618         p_result.locked = FALSE;
1619         switch (intp->err[demod]) {
1620         case STV0900_I2C_ERROR:
1621             error = STV0900_I2C_ERROR;
1622             break;
1623         case STV0900_NO_ERROR:
1624         default:
1625             error = STV0900_SEARCH_FAILED;
1626             break;
1627         }
1628     }
1629 
1630     if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
1631         dprintk("Search Success\n");
1632         return DVBFE_ALGO_SEARCH_SUCCESS;
1633     } else {
1634         dprintk("Search Fail\n");
1635         return DVBFE_ALGO_SEARCH_FAILED;
1636     }
1637 
1638 }
1639 
1640 static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
1641 {
1642     struct stv0900_state *state = fe->demodulator_priv;
1643 
1644     dprintk("%s: ", __func__);
1645 
1646     if ((stv0900_status(state->internal, state->demod)) == TRUE) {
1647         dprintk("DEMOD LOCK OK\n");
1648         *status = FE_HAS_CARRIER
1649             | FE_HAS_VITERBI
1650             | FE_HAS_SYNC
1651             | FE_HAS_LOCK;
1652         if (state->config->set_lock_led)
1653             state->config->set_lock_led(fe, 1);
1654     } else {
1655         *status = 0;
1656         if (state->config->set_lock_led)
1657             state->config->set_lock_led(fe, 0);
1658         dprintk("DEMOD LOCK FAIL\n");
1659     }
1660 
1661     return 0;
1662 }
1663 
1664 static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
1665 {
1666 
1667     struct stv0900_state *state = fe->demodulator_priv;
1668     struct stv0900_internal *intp = state->internal;
1669     enum fe_stv0900_demod_num demod = state->demod;
1670 
1671     if (stop_ts == TRUE)
1672         stv0900_write_bits(intp, RST_HWARE, 1);
1673     else
1674         stv0900_write_bits(intp, RST_HWARE, 0);
1675 
1676     return 0;
1677 }
1678 
1679 static int stv0900_diseqc_init(struct dvb_frontend *fe)
1680 {
1681     struct stv0900_state *state = fe->demodulator_priv;
1682     struct stv0900_internal *intp = state->internal;
1683     enum fe_stv0900_demod_num demod = state->demod;
1684 
1685     stv0900_write_bits(intp, DISTX_MODE, state->config->diseqc_mode);
1686     stv0900_write_bits(intp, DISEQC_RESET, 1);
1687     stv0900_write_bits(intp, DISEQC_RESET, 0);
1688 
1689     return 0;
1690 }
1691 
1692 static int stv0900_init(struct dvb_frontend *fe)
1693 {
1694     dprintk("%s\n", __func__);
1695 
1696     stv0900_stop_ts(fe, 1);
1697     stv0900_diseqc_init(fe);
1698 
1699     return 0;
1700 }
1701 
1702 static int stv0900_diseqc_send(struct stv0900_internal *intp , u8 *data,
1703                 u32 NbData, enum fe_stv0900_demod_num demod)
1704 {
1705     s32 i = 0;
1706 
1707     stv0900_write_bits(intp, DIS_PRECHARGE, 1);
1708     while (i < NbData) {
1709         while (stv0900_get_bits(intp, FIFO_FULL))
1710             ;/* checkpatch complains */
1711         stv0900_write_reg(intp, DISTXDATA, data[i]);
1712         i++;
1713     }
1714 
1715     stv0900_write_bits(intp, DIS_PRECHARGE, 0);
1716     i = 0;
1717     while ((stv0900_get_bits(intp, TX_IDLE) != 1) && (i < 10)) {
1718         msleep(10);
1719         i++;
1720     }
1721 
1722     return 0;
1723 }
1724 
1725 static int stv0900_send_master_cmd(struct dvb_frontend *fe,
1726                     struct dvb_diseqc_master_cmd *cmd)
1727 {
1728     struct stv0900_state *state = fe->demodulator_priv;
1729 
1730     return stv0900_diseqc_send(state->internal,
1731                 cmd->msg,
1732                 cmd->msg_len,
1733                 state->demod);
1734 }
1735 
1736 static int stv0900_send_burst(struct dvb_frontend *fe,
1737                   enum fe_sec_mini_cmd burst)
1738 {
1739     struct stv0900_state *state = fe->demodulator_priv;
1740     struct stv0900_internal *intp = state->internal;
1741     enum fe_stv0900_demod_num demod = state->demod;
1742     u8 data;
1743 
1744 
1745     switch (burst) {
1746     case SEC_MINI_A:
1747         stv0900_write_bits(intp, DISTX_MODE, 3);/* Unmodulated */
1748         data = 0x00;
1749         stv0900_diseqc_send(intp, &data, 1, state->demod);
1750         break;
1751     case SEC_MINI_B:
1752         stv0900_write_bits(intp, DISTX_MODE, 2);/* Modulated */
1753         data = 0xff;
1754         stv0900_diseqc_send(intp, &data, 1, state->demod);
1755         break;
1756     }
1757 
1758     return 0;
1759 }
1760 
1761 static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
1762                 struct dvb_diseqc_slave_reply *reply)
1763 {
1764     struct stv0900_state *state = fe->demodulator_priv;
1765     struct stv0900_internal *intp = state->internal;
1766     enum fe_stv0900_demod_num demod = state->demod;
1767     s32 i = 0;
1768 
1769     reply->msg_len = 0;
1770 
1771     while ((stv0900_get_bits(intp, RX_END) != 1) && (i < 10)) {
1772         msleep(10);
1773         i++;
1774     }
1775 
1776     if (stv0900_get_bits(intp, RX_END)) {
1777         reply->msg_len = stv0900_get_bits(intp, FIFO_BYTENBR);
1778 
1779         for (i = 0; i < reply->msg_len; i++)
1780             reply->msg[i] = stv0900_read_reg(intp, DISRXDATA);
1781     }
1782 
1783     return 0;
1784 }
1785 
1786 static int stv0900_set_tone(struct dvb_frontend *fe,
1787                 enum fe_sec_tone_mode toneoff)
1788 {
1789     struct stv0900_state *state = fe->demodulator_priv;
1790     struct stv0900_internal *intp = state->internal;
1791     enum fe_stv0900_demod_num demod = state->demod;
1792 
1793     dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off"));
1794 
1795     switch (toneoff) {
1796     case SEC_TONE_ON:
1797         /*Set the DiseqC mode to 22Khz _continues_ tone*/
1798         stv0900_write_bits(intp, DISTX_MODE, 0);
1799         stv0900_write_bits(intp, DISEQC_RESET, 1);
1800         /*release DiseqC reset to enable the 22KHz tone*/
1801         stv0900_write_bits(intp, DISEQC_RESET, 0);
1802         break;
1803     case SEC_TONE_OFF:
1804         /*return diseqc mode to config->diseqc_mode.
1805         Usually it's without _continues_ tone */
1806         stv0900_write_bits(intp, DISTX_MODE,
1807                 state->config->diseqc_mode);
1808         /*maintain the DiseqC reset to disable the 22KHz tone*/
1809         stv0900_write_bits(intp, DISEQC_RESET, 1);
1810         stv0900_write_bits(intp, DISEQC_RESET, 0);
1811         break;
1812     default:
1813         return -EINVAL;
1814     }
1815 
1816     return 0;
1817 }
1818 
1819 static void stv0900_release(struct dvb_frontend *fe)
1820 {
1821     struct stv0900_state *state = fe->demodulator_priv;
1822 
1823     dprintk("%s\n", __func__);
1824 
1825     if (state->config->set_lock_led)
1826         state->config->set_lock_led(fe, 0);
1827 
1828     if ((--(state->internal->dmds_used)) <= 0) {
1829 
1830         dprintk("%s: Actually removing\n", __func__);
1831 
1832         remove_inode(state->internal);
1833         kfree(state->internal);
1834     }
1835 
1836     kfree(state);
1837 }
1838 
1839 static int stv0900_sleep(struct dvb_frontend *fe)
1840 {
1841     struct stv0900_state *state = fe->demodulator_priv;
1842 
1843     dprintk("%s\n", __func__);
1844 
1845     if (state->config->set_lock_led)
1846         state->config->set_lock_led(fe, 0);
1847 
1848     return 0;
1849 }
1850 
1851 static int stv0900_get_frontend(struct dvb_frontend *fe,
1852                 struct dtv_frontend_properties *p)
1853 {
1854     struct stv0900_state *state = fe->demodulator_priv;
1855     struct stv0900_internal *intp = state->internal;
1856     enum fe_stv0900_demod_num demod = state->demod;
1857     struct stv0900_signal_info p_result = intp->result[demod];
1858 
1859     p->frequency = p_result.locked ? p_result.frequency : 0;
1860     p->symbol_rate = p_result.locked ? p_result.symbol_rate : 0;
1861     return 0;
1862 }
1863 
1864 static const struct dvb_frontend_ops stv0900_ops = {
1865     .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
1866     .info = {
1867         .name           = "STV0900 frontend",
1868         .frequency_min_hz   =  950 * MHz,
1869         .frequency_max_hz   = 2150 * MHz,
1870         .frequency_stepsize_hz  =  125 * kHz,
1871         .symbol_rate_min    = 1000000,
1872         .symbol_rate_max    = 45000000,
1873         .symbol_rate_tolerance  = 500,
1874         .caps           = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1875                       FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
1876                       FE_CAN_FEC_7_8 | FE_CAN_QPSK    |
1877                       FE_CAN_2G_MODULATION |
1878                       FE_CAN_FEC_AUTO
1879     },
1880     .release            = stv0900_release,
1881     .init               = stv0900_init,
1882     .get_frontend                   = stv0900_get_frontend,
1883     .sleep              = stv0900_sleep,
1884     .get_frontend_algo      = stv0900_frontend_algo,
1885     .i2c_gate_ctrl          = stv0900_i2c_gate_ctrl,
1886     .diseqc_send_master_cmd     = stv0900_send_master_cmd,
1887     .diseqc_send_burst      = stv0900_send_burst,
1888     .diseqc_recv_slave_reply    = stv0900_recv_slave_reply,
1889     .set_tone           = stv0900_set_tone,
1890     .search             = stv0900_search,
1891     .read_status            = stv0900_read_status,
1892     .read_ber           = stv0900_read_ber,
1893     .read_signal_strength       = stv0900_read_signal_strength,
1894     .read_snr           = stv0900_read_snr,
1895     .read_ucblocks                  = stv0900_read_ucblocks,
1896 };
1897 
1898 struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
1899                     struct i2c_adapter *i2c,
1900                     int demod)
1901 {
1902     struct stv0900_state *state = NULL;
1903     struct stv0900_init_params init_params;
1904     enum fe_stv0900_error err_stv0900;
1905 
1906     state = kzalloc(sizeof(struct stv0900_state), GFP_KERNEL);
1907     if (state == NULL)
1908         goto error;
1909 
1910     state->demod        = demod;
1911     state->config       = config;
1912     state->i2c_adap     = i2c;
1913 
1914     memcpy(&state->frontend.ops, &stv0900_ops,
1915             sizeof(struct dvb_frontend_ops));
1916     state->frontend.demodulator_priv = state;
1917 
1918     switch (demod) {
1919     case 0:
1920     case 1:
1921         init_params.dmd_ref_clk     = config->xtal;
1922         init_params.demod_mode      = config->demod_mode;
1923         init_params.rolloff     = STV0900_35;
1924         init_params.path1_ts_clock  = config->path1_mode;
1925         init_params.tun1_maddress   = config->tun1_maddress;
1926         init_params.tun1_iq_inv     = STV0900_IQ_NORMAL;
1927         init_params.tuner1_adc      = config->tun1_adc;
1928         init_params.tuner1_type     = config->tun1_type;
1929         init_params.path2_ts_clock  = config->path2_mode;
1930         init_params.ts_config       = config->ts_config_regs;
1931         init_params.tun2_maddress   = config->tun2_maddress;
1932         init_params.tuner2_adc      = config->tun2_adc;
1933         init_params.tuner2_type     = config->tun2_type;
1934         init_params.tun2_iq_inv     = STV0900_IQ_SWAPPED;
1935 
1936         err_stv0900 = stv0900_init_internal(&state->frontend,
1937                             &init_params);
1938 
1939         if (err_stv0900)
1940             goto error;
1941 
1942         if (state->internal->chip_id >= 0x30)
1943             state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM;
1944 
1945         break;
1946     default:
1947         goto error;
1948         break;
1949     }
1950 
1951     dprintk("%s: Attaching STV0900 demodulator(%d) \n", __func__, demod);
1952     return &state->frontend;
1953 
1954 error:
1955     dprintk("%s: Failed to attach STV0900 demodulator(%d) \n",
1956         __func__, demod);
1957     kfree(state);
1958     return NULL;
1959 }
1960 EXPORT_SYMBOL(stv0900_attach);
1961 
1962 MODULE_PARM_DESC(debug, "Set debug");
1963 
1964 MODULE_AUTHOR("Igor M. Liplianin");
1965 MODULE_DESCRIPTION("ST STV0900 frontend");
1966 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!