media/dvb-frontends/stv0367.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * stv0367.c
0004  *
0005  * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
0006  *
0007  * Copyright (C) ST Microelectronics.
0008  * Copyright (C) 2010,2011 NetUP Inc.
0009  * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
0010  */
0011
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/string.h>
0015 #include <linux/slab.h>
0016 #include <linux/i2c.h>
0017
0018 #include <media/dvb_math.h>
0019
0020 #include "stv0367.h"
0021 #include "stv0367_defs.h"
0022 #include "stv0367_regs.h"
0023 #include "stv0367_priv.h"
0024
0025 /* Max transfer size done by I2C transfer functions */
0026 #define MAX_XFER_SIZE  64
0027
0028 static int stvdebug;
0029 module_param_named(debug, stvdebug, int, 0644);
0030
0031 static int i2cdebug;
0032 module_param_named(i2c_debug, i2cdebug, int, 0644);
0033
0034 #define dprintk(args...) \
0035     do { \
0036         if (stvdebug) \
0037             printk(KERN_DEBUG args); \
0038     } while (0)
0039     /* DVB-C */
0040
0041 enum active_demod_state { demod_none, demod_ter, demod_cab };
0042
0043 struct stv0367cab_state {
0044     enum stv0367_cab_signal_type    state;
0045     u32 mclk;
0046     u32 adc_clk;
0047     s32 search_range;
0048     s32 derot_offset;
0049     /* results */
0050     int locked;         /* channel found        */
0051     u32 freq_khz;           /* found frequency (in kHz) */
0052     u32 symbol_rate;        /* found symbol rate (in Bds)   */
0053     enum fe_spectral_inversion spect_inv; /* Spectrum Inversion */
0054     u32 qamfec_status_reg;          /* status reg to poll for FEC Lock */
0055 };
0056
0057 struct stv0367ter_state {
0058     /* DVB-T */
0059     enum stv0367_ter_signal_type state;
0060     enum stv0367_ter_if_iq_mode if_iq_mode;
0061     enum stv0367_ter_mode mode;/* mode 2K or 8K */
0062     enum fe_guard_interval guard;
0063     enum stv0367_ter_hierarchy hierarchy;
0064     u32 frequency;
0065     enum fe_spectral_inversion sense; /*  current search spectrum */
0066     u8  force; /* force mode/guard */
0067     u8  bw; /* channel width 6, 7 or 8 in MHz */
0068     u8  pBW; /* channel width used during previous lock */
0069     u32 pBER;
0070     u32 pPER;
0071     u32 ucblocks;
0072     s8  echo_pos; /* echo position */
0073     u8  first_lock;
0074     u8  unlock_counter;
0075     u32 agc_val;
0076 };
0077
0078 struct stv0367_state {
0079     struct dvb_frontend fe;
0080     struct i2c_adapter *i2c;
0081     /* config settings */
0082     const struct stv0367_config *config;
0083     u8 chip_id;
0084     /* DVB-C */
0085     struct stv0367cab_state *cab_state;
0086     /* DVB-T */
0087     struct stv0367ter_state *ter_state;
0088     /* flags for operation control */
0089     u8 use_i2c_gatectrl;
0090     u8 deftabs;
0091     u8 reinit_on_setfrontend;
0092     u8 auto_if_khz;
0093     enum active_demod_state activedemod;
0094 };
0095
0096 #define RF_LOOKUP_TABLE_SIZE  31
0097 #define RF_LOOKUP_TABLE2_SIZE 16
0098 /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
0099 static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
0100     {/*AGC1*/
0101         48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
0102         64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
0103         76, 77, 78, 80, 83, 85, 88,
0104     }, {/*RF(dbm)*/
0105         22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
0106         34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
0107         49, 50, 52, 53, 54, 55, 56,
0108     }
0109 };
0110 /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
0111 static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
0112     {/*AGC2*/
0113         28, 29, 31, 32, 34, 35, 36, 37,
0114         38, 39, 40, 41, 42, 43, 44, 45,
0115     }, {/*RF(dbm)*/
0116         57, 58, 59, 60, 61, 62, 63, 64,
0117         65, 66, 67, 68, 69, 70, 71, 72,
0118     }
0119 };
0120
0121 static
0122 int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
0123 {
0124     u8 buf[MAX_XFER_SIZE];
0125     struct i2c_msg msg = {
0126         .addr = state->config->demod_address,
0127         .flags = 0,
0128         .buf = buf,
0129         .len = len + 2
0130     };
0131     int ret;
0132
0133     if (2 + len > sizeof(buf)) {
0134         printk(KERN_WARNING
0135                "%s: i2c wr reg=%04x: len=%d is too big!\n",
0136                KBUILD_MODNAME, reg, len);
0137         return -EINVAL;
0138     }
0139
0140
0141     buf[0] = MSB(reg);
0142     buf[1] = LSB(reg);
0143     memcpy(buf + 2, data, len);
0144
0145     if (i2cdebug)
0146         printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
0147             state->config->demod_address, reg, buf[2]);
0148
0149     ret = i2c_transfer(state->i2c, &msg, 1);
0150     if (ret != 1)
0151         printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n",
0152             __func__, state->config->demod_address, reg, buf[2]);
0153
0154     return (ret != 1) ? -EREMOTEIO : 0;
0155 }
0156
0157 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
0158 {
0159     u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
0160
0161     return stv0367_writeregs(state, reg, &tmp, 1);
0162 }
0163
0164 static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
0165 {
0166     u8 b0[] = { 0, 0 };
0167     u8 b1[] = { 0 };
0168     struct i2c_msg msg[] = {
0169         {
0170             .addr = state->config->demod_address,
0171             .flags = 0,
0172             .buf = b0,
0173             .len = 2
0174         }, {
0175             .addr = state->config->demod_address,
0176             .flags = I2C_M_RD,
0177             .buf = b1,
0178             .len = 1
0179         }
0180     };
0181     int ret;
0182
0183     b0[0] = MSB(reg);
0184     b0[1] = LSB(reg);
0185
0186     ret = i2c_transfer(state->i2c, msg, 2);
0187     if (ret != 2)
0188         printk(KERN_ERR "%s: i2c read error ([%02x] %02x: %02x)\n",
0189             __func__, state->config->demod_address, reg, b1[0]);
0190
0191     if (i2cdebug)
0192         printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
0193             state->config->demod_address, reg, b1[0]);
0194
0195     return b1[0];
0196 }
0197
0198 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
0199 {
0200     u8 position = 0, i = 0;
0201
0202     (*mask) = label & 0xff;
0203
0204     while ((position == 0) && (i < 8)) {
0205         position = ((*mask) >> i) & 0x01;
0206         i++;
0207     }
0208
0209     (*pos) = (i - 1);
0210 }
0211
0212 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
0213 {
0214     u8 reg, mask, pos;
0215
0216     reg = stv0367_readreg(state, (label >> 16) & 0xffff);
0217     extract_mask_pos(label, &mask, &pos);
0218
0219     val = mask & (val << pos);
0220
0221     reg = (reg & (~mask)) | val;
0222     stv0367_writereg(state, (label >> 16) & 0xffff, reg);
0223
0224 }
0225
0226 static void stv0367_setbits(u8 *reg, u32 label, u8 val)
0227 {
0228     u8 mask, pos;
0229
0230     extract_mask_pos(label, &mask, &pos);
0231
0232     val = mask & (val << pos);
0233
0234     (*reg) = ((*reg) & (~mask)) | val;
0235 }
0236
0237 static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
0238 {
0239     u8 val = 0xff;
0240     u8 mask, pos;
0241
0242     extract_mask_pos(label, &mask, &pos);
0243
0244     val = stv0367_readreg(state, label >> 16);
0245     val = (val & mask) >> pos;
0246
0247     return val;
0248 }
0249
0250 #if 0 /* Currently, unused */
0251 static u8 stv0367_getbits(u8 reg, u32 label)
0252 {
0253     u8 mask, pos;
0254
0255     extract_mask_pos(label, &mask, &pos);
0256
0257     return (reg & mask) >> pos;
0258 }
0259 #endif
0260
0261 static void stv0367_write_table(struct stv0367_state *state,
0262                 const struct st_register *deftab)
0263 {
0264     int i = 0;
0265
0266     while (1) {
0267         if (!deftab[i].addr)
0268             break;
0269         stv0367_writereg(state, deftab[i].addr, deftab[i].value);
0270         i++;
0271     }
0272 }
0273
0274 static void stv0367_pll_setup(struct stv0367_state *state,
0275                 u32 icspeed, u32 xtal)
0276 {
0277     /* note on regs: R367TER_* and R367CAB_* defines each point to
0278      * 0xf0d8, so just use R367TER_ for both cases
0279      */
0280
0281     switch (icspeed) {
0282     case STV0367_ICSPEED_58000:
0283         switch (xtal) {
0284         default:
0285         case 27000000:
0286             dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n");
0287             /* PLLMDIV: 27, PLLNDIV: 232 */
0288             stv0367_writereg(state, R367TER_PLLMDIV, 0x1b);
0289             stv0367_writereg(state, R367TER_PLLNDIV, 0xe8);
0290             break;
0291         }
0292         break;
0293     default:
0294     case STV0367_ICSPEED_53125:
0295         switch (xtal) {
0296             /* set internal freq to 53.125MHz */
0297         case 16000000:
0298             stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
0299             stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
0300             break;
0301         case 25000000:
0302             stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
0303             stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
0304             break;
0305         default:
0306         case 27000000:
0307             dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
0308             stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
0309             stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
0310             break;
0311         case 30000000:
0312             stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
0313             stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
0314             break;
0315         }
0316     }
0317
0318     stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
0319 }
0320
0321 static int stv0367_get_if_khz(struct stv0367_state *state, u32 *ifkhz)
0322 {
0323     if (state->auto_if_khz && state->fe.ops.tuner_ops.get_if_frequency) {
0324         state->fe.ops.tuner_ops.get_if_frequency(&state->fe, ifkhz);
0325         *ifkhz = *ifkhz / 1000; /* hz -> khz */
0326     } else
0327         *ifkhz = state->config->if_khz;
0328
0329     return 0;
0330 }
0331
0332 static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
0333 {
0334     struct stv0367_state *state = fe->demodulator_priv;
0335     u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
0336
0337     dprintk("%s:\n", __func__);
0338
0339     if (enable) {
0340         stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
0341         stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
0342     } else {
0343         stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
0344         stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
0345     }
0346
0347     stv0367_writereg(state, R367TER_I2CRPT, tmp);
0348
0349     return 0;
0350 }
0351
0352 static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
0353 {
0354     struct dvb_frontend_ops *frontend_ops = &fe->ops;
0355     struct dvb_tuner_ops    *tuner_ops = &frontend_ops->tuner_ops;
0356     u32 freq = 0;
0357     int err = 0;
0358
0359     dprintk("%s:\n", __func__);
0360
0361     if (tuner_ops->get_frequency) {
0362         err = tuner_ops->get_frequency(fe, &freq);
0363         if (err < 0) {
0364             printk(KERN_ERR "%s: Invalid parameter\n", __func__);
0365             return err;
0366         }
0367
0368         dprintk("%s: frequency=%d\n", __func__, freq);
0369
0370     } else
0371         return -1;
0372
0373     return freq;
0374 }
0375
0376 static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
0377     {
0378         {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
0379         {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
0380         {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
0381         {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
0382         {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
0383         {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
0384     }, {
0385         {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
0386         {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
0387         {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
0388         {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
0389         {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
0390         {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
0391     }, {
0392         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
0393         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
0394         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
0395         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
0396         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
0397         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
0398     }
0399 };
0400
0401 static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
0402     {
0403         {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
0404         {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
0405         {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
0406         {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
0407         {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
0408         {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
0409     }, {
0410         {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
0411         {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
0412         {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
0413         {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
0414         {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
0415         {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
0416     }, {
0417         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
0418         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
0419         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
0420         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
0421         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
0422         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
0423     }
0424 };
0425
0426 static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
0427     {
0428         {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
0429         {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
0430         {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
0431         {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
0432         {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
0433         {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
0434     }, {
0435         {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
0436         {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
0437         {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
0438         {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
0439         {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
0440         {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
0441
0442     }, {
0443         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
0444         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
0445         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
0446         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
0447         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
0448         {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
0449     }
0450 };
0451
0452 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
0453 {
0454     u32 mclk_Hz = 0; /* master clock frequency (Hz) */
0455     u32 m, n, p;
0456
0457     dprintk("%s:\n", __func__);
0458
0459     if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
0460         n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
0461         if (n == 0)
0462             n = n + 1;
0463
0464         m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
0465         if (m == 0)
0466             m = m + 1;
0467
0468         p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
0469         if (p > 5)
0470             p = 5;
0471
0472         mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
0473
0474         dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
0475                 n, m, p, mclk_Hz, ExtClk_Hz);
0476     } else
0477         mclk_Hz = ExtClk_Hz;
0478
0479     dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
0480
0481     return mclk_Hz;
0482 }
0483
0484 static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
0485                 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
0486 {
0487     int i, j, k, freq;
0488
0489     dprintk("%s:\n", __func__);
0490
0491     freq = stv0367ter_get_mclk(state, DemodXtal);
0492
0493     if (freq == 53125000)
0494         k = 1; /* equivalent to Xtal 25M on 362*/
0495     else if (freq == 54000000)
0496         k = 0; /* equivalent to Xtal 27M on 362*/
0497     else if (freq == 52500000)
0498         k = 2; /* equivalent to Xtal 30M on 362*/
0499     else
0500         return 0;
0501
0502     for (i = 1; i <= 6; i++) {
0503         stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
0504
0505         for (j = 1; j <= 5; j++) {
0506             stv0367_writereg(state,
0507                 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
0508                 MSB(CellsCoeffs[k][i-1][j-1]));
0509             stv0367_writereg(state,
0510                 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
0511                 LSB(CellsCoeffs[k][i-1][j-1]));
0512         }
0513     }
0514
0515     return 1;
0516
0517 }
0518
0519 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
0520 {
0521     dprintk("%s:\n", __func__);
0522
0523     stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
0524
0525     /* Lock detect 1 */
0526     stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
0527     stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
0528     stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
0529
0530     /* Lock detect 2 */
0531     stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
0532     stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
0533     stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
0534
0535     /* Lock detect 3 */
0536     stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
0537     stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
0538     stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
0539
0540     /* Lock detect 4 */
0541     stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
0542     stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
0543     stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
0544
0545 }
0546
0547 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
0548                             u32 DemodXtalValue)
0549 {
0550     dprintk("%s:\n", __func__);
0551
0552     stv0367_writebits(state, F367TER_NRST_IIR, 0);
0553
0554     switch (Bandwidth) {
0555     case 6:
0556         if (!stv0367ter_filt_coeff_init(state,
0557                 CellsCoeffs_6MHz_367cofdm,
0558                 DemodXtalValue))
0559             return 0;
0560         break;
0561     case 7:
0562         if (!stv0367ter_filt_coeff_init(state,
0563                 CellsCoeffs_7MHz_367cofdm,
0564                 DemodXtalValue))
0565             return 0;
0566         break;
0567     case 8:
0568         if (!stv0367ter_filt_coeff_init(state,
0569                 CellsCoeffs_8MHz_367cofdm,
0570                 DemodXtalValue))
0571             return 0;
0572         break;
0573     default:
0574         return 0;
0575     }
0576
0577     stv0367_writebits(state, F367TER_NRST_IIR, 1);
0578
0579     return 1;
0580 }
0581
0582 static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
0583 {
0584
0585     u8 com_n;
0586
0587     dprintk("%s:\n", __func__);
0588
0589     com_n = stv0367_readbits(state, F367TER_COM_N);
0590
0591     stv0367_writebits(state, F367TER_COM_N, 0x07);
0592
0593     stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
0594     stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
0595
0596     stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
0597     stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
0598
0599     stv0367_writebits(state, F367TER_COM_N, com_n);
0600
0601 }
0602
0603 static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
0604 {
0605     int local_tempo = 0;
0606     switch (mode) {
0607     case 0:
0608         local_tempo = tempo1;
0609         break;
0610     case 1:
0611         local_tempo = tempo2;
0612         break ;
0613
0614     case 2:
0615         local_tempo = tempo3;
0616         break;
0617
0618     default:
0619         break;
0620     }
0621     /*  msleep(local_tempo);  */
0622     return local_tempo;
0623 }
0624
0625 static enum
0626 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
0627 {
0628     int wd = 100;
0629     unsigned short int SYR_var;
0630     s32 SYRStatus;
0631
0632     dprintk("%s:\n", __func__);
0633
0634     SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
0635
0636     while ((!SYR_var) && (wd > 0)) {
0637         usleep_range(2000, 3000);
0638         wd -= 2;
0639         SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
0640     }
0641
0642     if (!SYR_var)
0643         SYRStatus = FE_TER_NOSYMBOL;
0644     else
0645         SYRStatus =  FE_TER_SYMBOLOK;
0646
0647     dprintk("stv0367ter_check_syr SYRStatus %s\n",
0648                 SYR_var == 0 ? "No Symbol" : "OK");
0649
0650     return SYRStatus;
0651 }
0652
0653 static enum
0654 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
0655                                 s32 FFTmode)
0656 {
0657
0658     s32  CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
0659     int wd = 0;
0660
0661     dprintk("%s:\n", __func__);
0662
0663     switch (FFTmode) {
0664     case 0: /*2k mode*/
0665         CPAMPMin = 20;
0666         wd = 10;
0667         break;
0668     case 1: /*8k mode*/
0669         CPAMPMin = 80;
0670         wd = 55;
0671         break;
0672     case 2: /*4k mode*/
0673         CPAMPMin = 40;
0674         wd = 30;
0675         break;
0676     default:
0677         CPAMPMin = 0xffff;  /*drives to NOCPAMP */
0678         break;
0679     }
0680
0681     dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
0682
0683     CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
0684     while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
0685         usleep_range(1000, 2000);
0686         wd -= 1;
0687         CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
0688         /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
0689     }
0690     dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
0691     if (CPAMPvalue < CPAMPMin) {
0692         CPAMPStatus = FE_TER_NOCPAMP;
0693         dprintk("%s: CPAMP failed\n", __func__);
0694     } else {
0695         dprintk("%s: CPAMP OK !\n", __func__);
0696         CPAMPStatus = FE_TER_CPAMPOK;
0697     }
0698
0699     return CPAMPStatus;
0700 }
0701
0702 static enum stv0367_ter_signal_type
0703 stv0367ter_lock_algo(struct stv0367_state *state)
0704 {
0705     enum stv0367_ter_signal_type ret_flag;
0706     short int wd, tempo;
0707     u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
0708     u8 tmp, tmp2;
0709
0710     dprintk("%s:\n", __func__);
0711
0712     if (state == NULL)
0713         return FE_TER_SWNOK;
0714
0715     try = 0;
0716     do {
0717         ret_flag = FE_TER_LOCKOK;
0718
0719         stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
0720
0721         if (state->config->if_iq_mode != 0)
0722             stv0367_writebits(state, F367TER_COM_N, 0x07);
0723
0724         stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
0725         stv0367_writebits(state, F367TER_MODE, 0);
0726         stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
0727         usleep_range(5000, 10000);
0728
0729         stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
0730
0731
0732         if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
0733             return FE_TER_NOSYMBOL;
0734         else { /*
0735             if chip locked on wrong mode first try,
0736             it must lock correctly second try */
0737             mode = stv0367_readbits(state, F367TER_SYR_MODE);
0738             if (stv0367ter_check_cpamp(state, mode) ==
0739                             FE_TER_NOCPAMP) {
0740                 if (try == 0)
0741                     ret_flag = FE_TER_NOCPAMP;
0742
0743             }
0744         }
0745
0746         try++;
0747     } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
0748
0749     tmp  = stv0367_readreg(state, R367TER_SYR_STAT);
0750     tmp2 = stv0367_readreg(state, R367TER_STATUS);
0751     dprintk("state=%p\n", state);
0752     dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
0753                             mode, tmp, tmp2);
0754
0755     tmp  = stv0367_readreg(state, R367TER_PRVIT);
0756     tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
0757     dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
0758
0759     tmp  = stv0367_readreg(state, R367TER_GAIN_SRC1);
0760     dprintk("GAIN_SRC1=0x%x\n", tmp);
0761
0762     if ((mode != 0) && (mode != 1) && (mode != 2))
0763         return FE_TER_SWNOK;
0764
0765     /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
0766
0767     /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
0768     and set channel predictor in automatic */
0769 #if 0
0770     switch (guard) {
0771
0772     case 0:
0773     case 1:
0774         stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
0775         stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
0776         break;
0777     case 2:
0778     case 3:
0779         stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
0780         stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
0781         break;
0782
0783     default:
0784         return FE_TER_SWNOK;
0785     }
0786 #endif
0787
0788     /*reset fec an reedsolo FOR 367 only*/
0789     stv0367_writebits(state, F367TER_RST_SFEC, 1);
0790     stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
0791     usleep_range(1000, 2000);
0792     stv0367_writebits(state, F367TER_RST_SFEC, 0);
0793     stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
0794
0795     u_var1 = stv0367_readbits(state, F367TER_LK);
0796     u_var2 = stv0367_readbits(state, F367TER_PRF);
0797     u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
0798     /*  u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
0799
0800     wd = stv0367ter_duration(mode, 125, 500, 250);
0801     tempo = stv0367ter_duration(mode, 4, 16, 8);
0802
0803     /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4))  && (wd>=0)) */
0804     while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
0805         usleep_range(1000 * tempo, 1000 * (tempo + 1));
0806         wd -= tempo;
0807         u_var1 = stv0367_readbits(state, F367TER_LK);
0808         u_var2 = stv0367_readbits(state, F367TER_PRF);
0809         u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
0810         /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
0811     }
0812
0813     if (!u_var1)
0814         return FE_TER_NOLOCK;
0815
0816
0817     if (!u_var2)
0818         return FE_TER_NOPRFOUND;
0819
0820     if (!u_var3)
0821         return FE_TER_NOTPS;
0822
0823     guard = stv0367_readbits(state, F367TER_SYR_GUARD);
0824     stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
0825     switch (guard) {
0826     case 0:
0827     case 1:
0828         stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
0829         /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
0830         stv0367_writebits(state, F367TER_SYR_FILTER, 0);
0831         break;
0832     case 2:
0833     case 3:
0834         stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
0835         /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
0836         stv0367_writebits(state, F367TER_SYR_FILTER, 1);
0837         break;
0838
0839     default:
0840         return FE_TER_SWNOK;
0841     }
0842
0843     /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
0844     if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
0845             (mode == 1) &&
0846             (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
0847         stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
0848         stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
0849         stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
0850     } else
0851         stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
0852
0853     wd = stv0367ter_duration(mode, 125, 500, 250);
0854     u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
0855
0856     while ((!u_var4) && (wd >= 0)) {
0857         usleep_range(1000 * tempo, 1000 * (tempo + 1));
0858         wd -= tempo;
0859         u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
0860     }
0861
0862     if (!u_var4)
0863         return FE_TER_NOLOCK;
0864
0865     /* for 367 leave COM_N at 0x7 for IQ_mode*/
0866     /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
0867         tempo=0;
0868         while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
0869         (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
0870             ChipWaitOrAbort(state,1);
0871             tempo+=1;
0872         }
0873
0874         stv0367_writebits(state,F367TER_COM_N,0x17);
0875     } */
0876
0877     stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
0878
0879     dprintk("FE_TER_LOCKOK !!!\n");
0880
0881     return  FE_TER_LOCKOK;
0882
0883 }
0884
0885 static void stv0367ter_set_ts_mode(struct stv0367_state *state,
0886                     enum stv0367_ts_mode PathTS)
0887 {
0888
0889     dprintk("%s:\n", __func__);
0890
0891     if (state == NULL)
0892         return;
0893
0894     stv0367_writebits(state, F367TER_TS_DIS, 0);
0895     switch (PathTS) {
0896     default:
0897         /*for removing warning :default we can assume in parallel mode*/
0898     case STV0367_PARALLEL_PUNCT_CLOCK:
0899         stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
0900         stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
0901         break;
0902     case STV0367_SERIAL_PUNCT_CLOCK:
0903         stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
0904         stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
0905         break;
0906     }
0907 }
0908
0909 static void stv0367ter_set_clk_pol(struct stv0367_state *state,
0910                     enum stv0367_clk_pol clock)
0911 {
0912
0913     dprintk("%s:\n", __func__);
0914
0915     if (state == NULL)
0916         return;
0917
0918     switch (clock) {
0919     case STV0367_RISINGEDGE_CLOCK:
0920         stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
0921         break;
0922     case STV0367_FALLINGEDGE_CLOCK:
0923         stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
0924         break;
0925         /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
0926     default:
0927         stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
0928         break;
0929     }
0930 }
0931
0932 #if 0
0933 static void stv0367ter_core_sw(struct stv0367_state *state)
0934 {
0935
0936     dprintk("%s:\n", __func__);
0937
0938     stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
0939     stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
0940     msleep(350);
0941 }
0942 #endif
0943 static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
0944 {
0945     struct stv0367_state *state = fe->demodulator_priv;
0946
0947     dprintk("%s:\n", __func__);
0948
0949     if (standby_on) {
0950         stv0367_writebits(state, F367TER_STDBY, 1);
0951         stv0367_writebits(state, F367TER_STDBY_FEC, 1);
0952         stv0367_writebits(state, F367TER_STDBY_CORE, 1);
0953     } else {
0954         stv0367_writebits(state, F367TER_STDBY, 0);
0955         stv0367_writebits(state, F367TER_STDBY_FEC, 0);
0956         stv0367_writebits(state, F367TER_STDBY_CORE, 0);
0957     }
0958
0959     return 0;
0960 }
0961
0962 static int stv0367ter_sleep(struct dvb_frontend *fe)
0963 {
0964     return stv0367ter_standby(fe, 1);
0965 }
0966
0967 static int stv0367ter_init(struct dvb_frontend *fe)
0968 {
0969     struct stv0367_state *state = fe->demodulator_priv;
0970     struct stv0367ter_state *ter_state = state->ter_state;
0971
0972     dprintk("%s:\n", __func__);
0973
0974     ter_state->pBER = 0;
0975
0976     stv0367_write_table(state,
0977         stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
0978
0979     stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
0980
0981     stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
0982     stv0367_writereg(state, R367TER_ANACTRL, 0x00);
0983
0984     /*Set TS1 and TS2 to serial or parallel mode */
0985     stv0367ter_set_ts_mode(state, state->config->ts_mode);
0986     stv0367ter_set_clk_pol(state, state->config->clk_pol);
0987
0988     state->chip_id = stv0367_readreg(state, R367TER_ID);
0989     ter_state->first_lock = 0;
0990     ter_state->unlock_counter = 2;
0991
0992     return 0;
0993 }
0994
0995 static int stv0367ter_algo(struct dvb_frontend *fe)
0996 {
0997     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0998     struct stv0367_state *state = fe->demodulator_priv;
0999     struct stv0367ter_state *ter_state = state->ter_state;
1000     int offset = 0, tempo = 0;
1001     u8 u_var;
1002     u8 /*constell,*/ counter;
1003     s8 step;
1004     s32 timing_offset = 0;
1005     u32 trl_nomrate = 0, InternalFreq = 0, temp = 0, ifkhz = 0;
1006
1007     dprintk("%s:\n", __func__);
1008
1009     stv0367_get_if_khz(state, &ifkhz);
1010
1011     ter_state->frequency = p->frequency;
1012     ter_state->force = FE_TER_FORCENONE
1013             + stv0367_readbits(state, F367TER_FORCE) * 2;
1014     ter_state->if_iq_mode = state->config->if_iq_mode;
1015     switch (state->config->if_iq_mode) {
1016     case FE_TER_NORMAL_IF_TUNER:  /* Normal IF mode */
1017         dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1018         stv0367_writebits(state, F367TER_TUNER_BB, 0);
1019         stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1020         stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1021         break;
1022     case FE_TER_LONGPATH_IF_TUNER:  /* Long IF mode */
1023         dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1024         stv0367_writebits(state, F367TER_TUNER_BB, 0);
1025         stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1026         stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1027         break;
1028     case FE_TER_IQ_TUNER:  /* IQ mode */
1029         dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1030         stv0367_writebits(state, F367TER_TUNER_BB, 1);
1031         stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1032         break;
1033     default:
1034         printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1035         return -EINVAL;
1036     }
1037
1038     usleep_range(5000, 7000);
1039
1040     switch (p->inversion) {
1041     case INVERSION_AUTO:
1042     default:
1043         dprintk("%s: inversion AUTO\n", __func__);
1044         if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1045             stv0367_writebits(state, F367TER_IQ_INVERT,
1046                         ter_state->sense);
1047         else
1048             stv0367_writebits(state, F367TER_INV_SPECTR,
1049                         ter_state->sense);
1050
1051         break;
1052     case INVERSION_ON:
1053     case INVERSION_OFF:
1054         if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1055             stv0367_writebits(state, F367TER_IQ_INVERT,
1056                         p->inversion);
1057         else
1058             stv0367_writebits(state, F367TER_INV_SPECTR,
1059                         p->inversion);
1060
1061         break;
1062     }
1063
1064     if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1065                 (ter_state->pBW != ter_state->bw)) {
1066         stv0367ter_agc_iir_lock_detect_set(state);
1067
1068         /*set fine agc target to 180 for LPIF or IQ mode*/
1069         /* set Q_AGCTarget */
1070         stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1071         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1072         /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1073
1074         /* set Q_AGCTarget */
1075         stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1076         stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1077         /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1078
1079         if (!stv0367_iir_filt_init(state, ter_state->bw,
1080                         state->config->xtal))
1081             return -EINVAL;
1082         /*set IIR filter once for 6,7 or 8MHz BW*/
1083         ter_state->pBW = ter_state->bw;
1084
1085         stv0367ter_agc_iir_rst(state);
1086     }
1087
1088     if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1089         stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1090     else
1091         stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1092
1093     InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1094     temp = (int)
1095         ((((ter_state->bw * 64 * (1 << 15) * 100)
1096                         / (InternalFreq)) * 10) / 7);
1097
1098     stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1099     temp = temp / 2;
1100     stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1101     stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1102
1103     temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1104             stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1105             stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1106     temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1107     stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1108     stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1109     temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1110             stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1111
1112     temp = (int)
1113         ((InternalFreq - ifkhz) * (1 << 16) / (InternalFreq));
1114
1115     dprintk("DEROT temp=0x%x\n", temp);
1116     stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1117     stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1118
1119     ter_state->echo_pos = 0;
1120     ter_state->ucblocks = 0; /* liplianin */
1121     ter_state->pBER = 0; /* liplianin */
1122     stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1123
1124     if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1125         return 0;
1126
1127     ter_state->state = FE_TER_LOCKOK;
1128
1129     ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1130     ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1131
1132     ter_state->first_lock = 1; /* we know sense now :) */
1133
1134     ter_state->agc_val =
1135             (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1136             (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1137             stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1138             (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1139
1140     /* Carrier offset calculation */
1141     stv0367_writebits(state, F367TER_FREEZE, 1);
1142     offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1143     offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1144     offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1145     stv0367_writebits(state, F367TER_FREEZE, 0);
1146     if (offset > 8388607)
1147         offset -= 16777216;
1148
1149     offset = offset * 2 / 16384;
1150
1151     if (ter_state->mode == FE_TER_MODE_2K)
1152         offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1153     else if (ter_state->mode == FE_TER_MODE_4K)
1154         offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1155     else  if (ter_state->mode == FE_TER_MODE_8K)
1156         offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1157
1158     if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1159         if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1160                 (stv0367_readbits(state,
1161                     F367TER_STATUS_INV_SPECRUM) == 1)))
1162             offset = offset * -1;
1163     }
1164
1165     if (ter_state->bw == 6)
1166         offset = (offset * 6) / 8;
1167     else if (ter_state->bw == 7)
1168         offset = (offset * 7) / 8;
1169
1170     ter_state->frequency += offset;
1171
1172     tempo = 10;  /* exit even if timing_offset stays null */
1173     while ((timing_offset == 0) && (tempo > 0)) {
1174         usleep_range(10000, 20000); /*was 20ms  */
1175         /* fine tuning of timing offset if required */
1176         timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1177                 + 256 * stv0367_readbits(state,
1178                             F367TER_TRL_TOFFSET_HI);
1179         if (timing_offset >= 32768)
1180             timing_offset -= 65536;
1181         trl_nomrate = (512 * stv0367_readbits(state,
1182                             F367TER_TRL_NOMRATE_HI)
1183             + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1184             + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1185
1186         timing_offset = ((signed)(1000000 / trl_nomrate) *
1187                             timing_offset) / 2048;
1188         tempo--;
1189     }
1190
1191     if (timing_offset <= 0) {
1192         timing_offset = (timing_offset - 11) / 22;
1193         step = -1;
1194     } else {
1195         timing_offset = (timing_offset + 11) / 22;
1196         step = 1;
1197     }
1198
1199     for (counter = 0; counter < abs(timing_offset); counter++) {
1200         trl_nomrate += step;
1201         stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1202                         trl_nomrate % 2);
1203         stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1204                         trl_nomrate / 2);
1205         usleep_range(1000, 2000);
1206     }
1207
1208     usleep_range(5000, 6000);
1209     /* unlocks could happen in case of trl centring big step,
1210     then a core off/on restarts demod */
1211     u_var = stv0367_readbits(state, F367TER_LK);
1212
1213     if (!u_var) {
1214         stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1215         msleep(20);
1216         stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1217     }
1218
1219     return 0;
1220 }
1221
1222 static int stv0367ter_set_frontend(struct dvb_frontend *fe)
1223 {
1224     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1225     struct stv0367_state *state = fe->demodulator_priv;
1226     struct stv0367ter_state *ter_state = state->ter_state;
1227
1228     /*u8 trials[2]; */
1229     s8 num_trials, index;
1230     u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1231
1232     if (state->reinit_on_setfrontend)
1233         stv0367ter_init(fe);
1234
1235     if (fe->ops.tuner_ops.set_params) {
1236         if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
1237             fe->ops.i2c_gate_ctrl(fe, 1);
1238         fe->ops.tuner_ops.set_params(fe);
1239         if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
1240             fe->ops.i2c_gate_ctrl(fe, 0);
1241     }
1242
1243     switch (p->transmission_mode) {
1244     default:
1245     case TRANSMISSION_MODE_AUTO:
1246     case TRANSMISSION_MODE_2K:
1247         ter_state->mode = FE_TER_MODE_2K;
1248         break;
1249 /*  case TRANSMISSION_MODE_4K:
1250         pLook.mode = FE_TER_MODE_4K;
1251         break;*/
1252     case TRANSMISSION_MODE_8K:
1253         ter_state->mode = FE_TER_MODE_8K;
1254         break;
1255     }
1256
1257     switch (p->guard_interval) {
1258     default:
1259     case GUARD_INTERVAL_1_32:
1260     case GUARD_INTERVAL_1_16:
1261     case GUARD_INTERVAL_1_8:
1262     case GUARD_INTERVAL_1_4:
1263         ter_state->guard = p->guard_interval;
1264         break;
1265     case GUARD_INTERVAL_AUTO:
1266         ter_state->guard = GUARD_INTERVAL_1_32;
1267         break;
1268     }
1269
1270     switch (p->bandwidth_hz) {
1271     case 6000000:
1272         ter_state->bw = FE_TER_CHAN_BW_6M;
1273         break;
1274     case 7000000:
1275         ter_state->bw = FE_TER_CHAN_BW_7M;
1276         break;
1277     case 8000000:
1278     default:
1279         ter_state->bw = FE_TER_CHAN_BW_8M;
1280     }
1281
1282     ter_state->hierarchy = FE_TER_HIER_NONE;
1283
1284     switch (p->inversion) {
1285     case INVERSION_OFF:
1286     case INVERSION_ON:
1287         num_trials = 1;
1288         break;
1289     default:
1290         num_trials = 2;
1291         if (ter_state->first_lock)
1292             num_trials = 1;
1293         break;
1294     }
1295
1296     ter_state->state = FE_TER_NOLOCK;
1297     index = 0;
1298
1299     while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1300         if (!ter_state->first_lock) {
1301             if (p->inversion == INVERSION_AUTO)
1302                 ter_state->sense = SenseTrials[index];
1303
1304         }
1305         stv0367ter_algo(fe);
1306
1307         if ((ter_state->state == FE_TER_LOCKOK) &&
1308                 (p->inversion == INVERSION_AUTO) &&
1309                                 (index == 1)) {
1310             /* invert spectrum sense */
1311             SenseTrials[index] = SenseTrials[0];
1312             SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1313         }
1314
1315         index++;
1316     }
1317
1318     return 0;
1319 }
1320
1321 static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1322 {
1323     struct stv0367_state *state = fe->demodulator_priv;
1324     struct stv0367ter_state *ter_state = state->ter_state;
1325     u32 errs = 0;
1326
1327     /*wait for counting completion*/
1328     if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1329         errs =
1330             ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1331             * (1 << 16))
1332             + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1333             * (1 << 8))
1334             + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1335         ter_state->ucblocks = errs;
1336     }
1337
1338     (*ucblocks) = ter_state->ucblocks;
1339
1340     return 0;
1341 }
1342
1343 static int stv0367ter_get_frontend(struct dvb_frontend *fe,
1344                    struct dtv_frontend_properties *p)
1345 {
1346     struct stv0367_state *state = fe->demodulator_priv;
1347     struct stv0367ter_state *ter_state = state->ter_state;
1348     enum stv0367_ter_mode mode;
1349     int constell = 0,/* snr = 0,*/ Data = 0;
1350
1351     p->frequency = stv0367_get_tuner_freq(fe);
1352     if ((int)p->frequency < 0)
1353         p->frequency = -p->frequency;
1354
1355     constell = stv0367_readbits(state, F367TER_TPS_CONST);
1356     if (constell == 0)
1357         p->modulation = QPSK;
1358     else if (constell == 1)
1359         p->modulation = QAM_16;
1360     else
1361         p->modulation = QAM_64;
1362
1363     p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1364
1365     /* Get the Hierarchical mode */
1366     Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1367
1368     switch (Data) {
1369     case 0:
1370         p->hierarchy = HIERARCHY_NONE;
1371         break;
1372     case 1:
1373         p->hierarchy = HIERARCHY_1;
1374         break;
1375     case 2:
1376         p->hierarchy = HIERARCHY_2;
1377         break;
1378     case 3:
1379         p->hierarchy = HIERARCHY_4;
1380         break;
1381     default:
1382         p->hierarchy = HIERARCHY_AUTO;
1383         break; /* error */
1384     }
1385
1386     /* Get the FEC Rate */
1387     if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1388         Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1389     else
1390         Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1391
1392     switch (Data) {
1393     case 0:
1394         p->code_rate_HP = FEC_1_2;
1395         break;
1396     case 1:
1397         p->code_rate_HP = FEC_2_3;
1398         break;
1399     case 2:
1400         p->code_rate_HP = FEC_3_4;
1401         break;
1402     case 3:
1403         p->code_rate_HP = FEC_5_6;
1404         break;
1405     case 4:
1406         p->code_rate_HP = FEC_7_8;
1407         break;
1408     default:
1409         p->code_rate_HP = FEC_AUTO;
1410         break; /* error */
1411     }
1412
1413     mode = stv0367_readbits(state, F367TER_SYR_MODE);
1414
1415     switch (mode) {
1416     case FE_TER_MODE_2K:
1417         p->transmission_mode = TRANSMISSION_MODE_2K;
1418         break;
1419 /*  case FE_TER_MODE_4K:
1420         p->transmission_mode = TRANSMISSION_MODE_4K;
1421         break;*/
1422     case FE_TER_MODE_8K:
1423         p->transmission_mode = TRANSMISSION_MODE_8K;
1424         break;
1425     default:
1426         p->transmission_mode = TRANSMISSION_MODE_AUTO;
1427     }
1428
1429     p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
1430
1431     return 0;
1432 }
1433
1434 static u32 stv0367ter_snr_readreg(struct dvb_frontend *fe)
1435 {
1436     struct stv0367_state *state = fe->demodulator_priv;
1437     u32 snru32 = 0;
1438     int cpt = 0;
1439     u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
1440
1441     while (cpt < 10) {
1442         usleep_range(2000, 3000);
1443         if (cut == 0x50) /*cut 1.0 cut 1.1*/
1444             snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
1445         else /*cu2.0*/
1446             snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
1447
1448         cpt++;
1449     }
1450     snru32 /= 10;/*average on 10 values*/
1451
1452     return snru32;
1453 }
1454
1455 static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
1456 {
1457     u32 snrval = stv0367ter_snr_readreg(fe);
1458
1459     *snr = snrval / 1000;
1460
1461     return 0;
1462 }
1463
1464 #if 0
1465 static int stv0367ter_status(struct dvb_frontend *fe)
1466 {
1467
1468     struct stv0367_state *state = fe->demodulator_priv;
1469     struct stv0367ter_state *ter_state = state->ter_state;
1470     int locked = FALSE;
1471
1472     locked = (stv0367_readbits(state, F367TER_LK));
1473     if (!locked)
1474         ter_state->unlock_counter += 1;
1475     else
1476         ter_state->unlock_counter = 0;
1477
1478     if (ter_state->unlock_counter > 2) {
1479         if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
1480                 (!stv0367_readbits(state, F367TER_LK))) {
1481             stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1482             usleep_range(2000, 3000);
1483             stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1484             msleep(350);
1485             locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
1486                     (stv0367_readbits(state, F367TER_LK));
1487         }
1488
1489     }
1490
1491     return locked;
1492 }
1493 #endif
1494 static int stv0367ter_read_status(struct dvb_frontend *fe,
1495                   enum fe_status *status)
1496 {
1497     struct stv0367_state *state = fe->demodulator_priv;
1498
1499     dprintk("%s:\n", __func__);
1500
1501     *status = 0;
1502
1503     if (stv0367_readbits(state, F367TER_LK)) {
1504         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
1505               | FE_HAS_SYNC | FE_HAS_LOCK;
1506         dprintk("%s: stv0367 has locked\n", __func__);
1507     }
1508
1509     return 0;
1510 }
1511
1512 static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
1513 {
1514     struct stv0367_state *state = fe->demodulator_priv;
1515     struct stv0367ter_state *ter_state = state->ter_state;
1516     u32 Errors = 0, tber = 0, temporary = 0;
1517     int abc = 0, def = 0;
1518
1519
1520     /*wait for counting completion*/
1521     if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
1522         Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
1523             * (1 << 16))
1524             + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
1525             * (1 << 8))
1526             + ((u32)stv0367_readbits(state,
1527                         F367TER_SFEC_ERR_CNT_LO));
1528     /*measurement not completed, load previous value*/
1529     else {
1530         tber = ter_state->pBER;
1531         return 0;
1532     }
1533
1534     abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
1535     def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
1536
1537     if (Errors == 0) {
1538         tber = 0;
1539     } else if (abc == 0x7) {
1540         if (Errors <= 4) {
1541             temporary = (Errors * 1000000000) / (8 * (1 << 14));
1542         } else if (Errors <= 42) {
1543             temporary = (Errors * 100000000) / (8 * (1 << 14));
1544             temporary = temporary * 10;
1545         } else if (Errors <= 429) {
1546             temporary = (Errors * 10000000) / (8 * (1 << 14));
1547             temporary = temporary * 100;
1548         } else if (Errors <= 4294) {
1549             temporary = (Errors * 1000000) / (8 * (1 << 14));
1550             temporary = temporary * 1000;
1551         } else if (Errors <= 42949) {
1552             temporary = (Errors * 100000) / (8 * (1 << 14));
1553             temporary = temporary * 10000;
1554         } else if (Errors <= 429496) {
1555             temporary = (Errors * 10000) / (8 * (1 << 14));
1556             temporary = temporary * 100000;
1557         } else { /*if (Errors<4294967) 2^22 max error*/
1558             temporary = (Errors * 1000) / (8 * (1 << 14));
1559             temporary = temporary * 100000; /* still to *10 */
1560         }
1561
1562         /* Byte error*/
1563         if (def == 2)
1564             /*tber=Errors/(8*(1 <<14));*/
1565             tber = temporary;
1566         else if (def == 3)
1567             /*tber=Errors/(8*(1 <<16));*/
1568             tber = temporary / 4;
1569         else if (def == 4)
1570             /*tber=Errors/(8*(1 <<18));*/
1571             tber = temporary / 16;
1572         else if (def == 5)
1573             /*tber=Errors/(8*(1 <<20));*/
1574             tber = temporary / 64;
1575         else if (def == 6)
1576             /*tber=Errors/(8*(1 <<22));*/
1577             tber = temporary / 256;
1578         else
1579             /* should not pass here*/
1580             tber = 0;
1581
1582         if ((Errors < 4294967) && (Errors > 429496))
1583             tber *= 10;
1584
1585     }
1586
1587     /* save actual value */
1588     ter_state->pBER = tber;
1589
1590     (*ber) = tber;
1591
1592     return 0;
1593 }
1594 #if 0
1595 static u32 stv0367ter_get_per(struct stv0367_state *state)
1596 {
1597     struct stv0367ter_state *ter_state = state->ter_state;
1598     u32 Errors = 0, Per = 0, temporary = 0;
1599     int abc = 0, def = 0, cpt = 0;
1600
1601     while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
1602             (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
1603         usleep_range(1000, 2000);
1604         Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1605             * (1 << 16))
1606             + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1607             * (1 << 8))
1608             + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1609         cpt++;
1610     }
1611     abc = stv0367_readbits(state, F367TER_ERR_SRC1);
1612     def = stv0367_readbits(state, F367TER_NUM_EVT1);
1613
1614     if (Errors == 0)
1615         Per = 0;
1616     else if (abc == 0x9) {
1617         if (Errors <= 4) {
1618             temporary = (Errors * 1000000000) / (8 * (1 << 8));
1619         } else if (Errors <= 42) {
1620             temporary = (Errors * 100000000) / (8 * (1 << 8));
1621             temporary = temporary * 10;
1622         } else if (Errors <= 429) {
1623             temporary = (Errors * 10000000) / (8 * (1 << 8));
1624             temporary = temporary * 100;
1625         } else if (Errors <= 4294) {
1626             temporary = (Errors * 1000000) / (8 * (1 << 8));
1627             temporary = temporary * 1000;
1628         } else if (Errors <= 42949) {
1629             temporary = (Errors * 100000) / (8 * (1 << 8));
1630             temporary = temporary * 10000;
1631         } else { /*if(Errors<=429496)  2^16 errors max*/
1632             temporary = (Errors * 10000) / (8 * (1 << 8));
1633             temporary = temporary * 100000;
1634         }
1635
1636         /* pkt error*/
1637         if (def == 2)
1638             /*Per=Errors/(1 << 8);*/
1639             Per = temporary;
1640         else if (def == 3)
1641             /*Per=Errors/(1 << 10);*/
1642             Per = temporary / 4;
1643         else if (def == 4)
1644             /*Per=Errors/(1 << 12);*/
1645             Per = temporary / 16;
1646         else if (def == 5)
1647             /*Per=Errors/(1 << 14);*/
1648             Per = temporary / 64;
1649         else if (def == 6)
1650             /*Per=Errors/(1 << 16);*/
1651             Per = temporary / 256;
1652         else
1653             Per = 0;
1654
1655     }
1656     /* save actual value */
1657     ter_state->pPER = Per;
1658
1659     return Per;
1660 }
1661 #endif
1662 static int stv0367_get_tune_settings(struct dvb_frontend *fe,
1663                     struct dvb_frontend_tune_settings
1664                     *fe_tune_settings)
1665 {
1666     fe_tune_settings->min_delay_ms = 1000;
1667     fe_tune_settings->step_size = 0;
1668     fe_tune_settings->max_drift = 0;
1669
1670     return 0;
1671 }
1672
1673 static void stv0367_release(struct dvb_frontend *fe)
1674 {
1675     struct stv0367_state *state = fe->demodulator_priv;
1676
1677     kfree(state->ter_state);
1678     kfree(state->cab_state);
1679     kfree(state);
1680 }
1681
1682 static const struct dvb_frontend_ops stv0367ter_ops = {
1683     .delsys = { SYS_DVBT },
1684     .info = {
1685         .name           = "ST STV0367 DVB-T",
1686         .frequency_min_hz   =  47 * MHz,
1687         .frequency_max_hz   = 862 * MHz,
1688         .frequency_stepsize_hz  = 15625,
1689         .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1690             FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
1691             FE_CAN_FEC_AUTO |
1692             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1693             FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
1694             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
1695             FE_CAN_INVERSION_AUTO |
1696             FE_CAN_MUTE_TS
1697     },
1698     .release = stv0367_release,
1699     .init = stv0367ter_init,
1700     .sleep = stv0367ter_sleep,
1701     .i2c_gate_ctrl = stv0367ter_gate_ctrl,
1702     .set_frontend = stv0367ter_set_frontend,
1703     .get_frontend = stv0367ter_get_frontend,
1704     .get_tune_settings = stv0367_get_tune_settings,
1705     .read_status = stv0367ter_read_status,
1706     .read_ber = stv0367ter_read_ber,/* too slow */
1707 /*  .read_signal_strength = stv0367_read_signal_strength,*/
1708     .read_snr = stv0367ter_read_snr,
1709     .read_ucblocks = stv0367ter_read_ucblocks,
1710 };
1711
1712 struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
1713                    struct i2c_adapter *i2c)
1714 {
1715     struct stv0367_state *state = NULL;
1716     struct stv0367ter_state *ter_state = NULL;
1717
1718     /* allocate memory for the internal state */
1719     state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
1720     if (state == NULL)
1721         goto error;
1722     ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
1723     if (ter_state == NULL)
1724         goto error;
1725
1726     /* setup the state */
1727     state->i2c = i2c;
1728     state->config = config;
1729     state->ter_state = ter_state;
1730     state->fe.ops = stv0367ter_ops;
1731     state->fe.demodulator_priv = state;
1732     state->chip_id = stv0367_readreg(state, 0xf000);
1733
1734     /* demod operation options */
1735     state->use_i2c_gatectrl = 1;
1736     state->deftabs = STV0367_DEFTAB_GENERIC;
1737     state->reinit_on_setfrontend = 1;
1738     state->auto_if_khz = 0;
1739
1740     dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
1741
1742     /* check if the demod is there */
1743     if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
1744         goto error;
1745
1746     return &state->fe;
1747
1748 error:
1749     kfree(ter_state);
1750     kfree(state);
1751     return NULL;
1752 }
1753 EXPORT_SYMBOL(stv0367ter_attach);
1754
1755 static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
1756 {
1757     struct stv0367_state *state = fe->demodulator_priv;
1758
1759     dprintk("%s:\n", __func__);
1760
1761     stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
1762
1763     return 0;
1764 }
1765
1766 static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
1767 {
1768     struct stv0367_state *state = fe->demodulator_priv;
1769     u32 mclk_Hz = 0;/* master clock frequency (Hz) */
1770     u32 M, N, P;
1771
1772
1773     if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
1774         N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
1775         if (N == 0)
1776             N = N + 1;
1777
1778         M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
1779         if (M == 0)
1780             M = M + 1;
1781
1782         P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
1783
1784         if (P > 5)
1785             P = 5;
1786
1787         mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
1788         dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
1789                                 mclk_Hz);
1790     } else
1791         mclk_Hz = ExtClk_Hz;
1792
1793     dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
1794
1795     return mclk_Hz;
1796 }
1797
1798 static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
1799 {
1800     return stv0367cab_get_mclk(fe, ExtClk_Hz);
1801 }
1802
1803 static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
1804                          u32 SymbolRate,
1805                          enum stv0367cab_mod QAMSize)
1806 {
1807     /* Set QAM size */
1808     stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
1809
1810     /* Set Registers settings specific to the QAM size */
1811     switch (QAMSize) {
1812     case FE_CAB_MOD_QAM4:
1813         stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1814         break;
1815     case FE_CAB_MOD_QAM16:
1816         stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
1817         stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1818         stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1819         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1820         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1821         stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1822         stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1823         stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
1824         break;
1825     case FE_CAB_MOD_QAM32:
1826         stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1827         stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
1828         stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1829         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1830         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
1831         stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
1832         stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1833         stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1834         break;
1835     case FE_CAB_MOD_QAM64:
1836         stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
1837         stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1838         if (SymbolRate > 4500000) {
1839             stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1840             stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1841             stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
1842         } else if (SymbolRate > 2500000) {
1843             stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1844             stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1845             stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1846         } else {
1847             stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1848             stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1849             stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1850         }
1851         stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1852         stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1853         stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
1854         break;
1855     case FE_CAB_MOD_QAM128:
1856         stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1857         stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
1858         stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1859         stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
1860         if (SymbolRate > 4500000)
1861             stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1862         else if (SymbolRate > 2500000)
1863             stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1864         else
1865             stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
1866
1867         stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
1868         stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1869         stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1870         break;
1871     case FE_CAB_MOD_QAM256:
1872         stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
1873         stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1874         stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1875         if (SymbolRate > 4500000)
1876             stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1877         else if (SymbolRate > 2500000)
1878             stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1879         else
1880             stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1881
1882         stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1883         stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
1884         stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1885         stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1886         break;
1887     case FE_CAB_MOD_QAM512:
1888         stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1889         break;
1890     case FE_CAB_MOD_QAM1024:
1891         stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1892         break;
1893     default:
1894         break;
1895     }
1896
1897     return QAMSize;
1898 }
1899
1900 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
1901                     u32 adc_hz, s32 derot_hz)
1902 {
1903     u32 sampled_if = 0;
1904     u32 adc_khz;
1905
1906     adc_khz = adc_hz / 1000;
1907
1908     dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
1909
1910     if (adc_khz != 0) {
1911         if (derot_hz < 1000000)
1912             derot_hz = adc_hz / 4; /* ZIF operation */
1913         if (derot_hz > adc_hz)
1914             derot_hz = derot_hz - adc_hz;
1915         sampled_if = (u32)derot_hz / 1000;
1916         sampled_if *= 32768;
1917         sampled_if /= adc_khz;
1918         sampled_if *= 256;
1919     }
1920
1921     if (sampled_if > 8388607)
1922         sampled_if = 8388607;
1923
1924     dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
1925
1926     stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
1927     stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
1928     stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
1929
1930     return derot_hz;
1931 }
1932
1933 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
1934 {
1935     u32 sampled_if;
1936
1937     sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
1938             (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
1939             (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
1940
1941     sampled_if /= 256;
1942     sampled_if *= (adc_hz / 1000);
1943     sampled_if += 1;
1944     sampled_if /= 32768;
1945
1946     return sampled_if;
1947 }
1948
1949 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
1950             u32 mclk_hz, u32 SymbolRate,
1951             enum stv0367cab_mod QAMSize)
1952 {
1953     u32 QamSizeCorr = 0;
1954     u32 u32_tmp = 0, u32_tmp1 = 0;
1955     u32 adp_khz;
1956
1957     dprintk("%s:\n", __func__);
1958
1959     /* Set Correction factor of SRC gain */
1960     switch (QAMSize) {
1961     case FE_CAB_MOD_QAM4:
1962         QamSizeCorr = 1110;
1963         break;
1964     case FE_CAB_MOD_QAM16:
1965         QamSizeCorr = 1032;
1966         break;
1967     case FE_CAB_MOD_QAM32:
1968         QamSizeCorr =  954;
1969         break;
1970     case FE_CAB_MOD_QAM64:
1971         QamSizeCorr =  983;
1972         break;
1973     case FE_CAB_MOD_QAM128:
1974         QamSizeCorr =  957;
1975         break;
1976     case FE_CAB_MOD_QAM256:
1977         QamSizeCorr =  948;
1978         break;
1979     case FE_CAB_MOD_QAM512:
1980         QamSizeCorr =    0;
1981         break;
1982     case FE_CAB_MOD_QAM1024:
1983         QamSizeCorr =  944;
1984         break;
1985     default:
1986         break;
1987     }
1988
1989     /* Transfer ratio calculation */
1990     if (adc_hz != 0) {
1991         u32_tmp = 256 * SymbolRate;
1992         u32_tmp = u32_tmp / adc_hz;
1993     }
1994     stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
1995
1996     /* Symbol rate and SRC gain calculation */
1997     adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
1998     if (adp_khz != 0) {
1999         u32_tmp = SymbolRate;
2000         u32_tmp1 = SymbolRate;
2001
2002         if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2003             /* Symbol rate calculation */
2004             u32_tmp *= 2048; /* 2048 = 2^11 */
2005             u32_tmp = u32_tmp / adp_khz;
2006             u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2007             u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2008             u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2009
2010             /* SRC Gain Calculation */
2011             u32_tmp1 *= 2048; /* *2*2^10 */
2012             u32_tmp1 /= 439; /* *2/878 */
2013             u32_tmp1 *= 256; /* *2^8 */
2014             u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2015             u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2016             u32_tmp1 = u32_tmp1 / 10000000;
2017
2018         } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2019             /* Symbol rate calculation */
2020             u32_tmp *= 1024 ; /* 1024 = 2**10 */
2021             u32_tmp = u32_tmp / adp_khz;
2022             u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2023             u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2024             u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2025
2026             /* SRC Gain Calculation */
2027             u32_tmp1 *= 1024; /* *2*2^9 */
2028             u32_tmp1 /= 439; /* *2/878 */
2029             u32_tmp1 *= 256; /* *2^8 */
2030             u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2031             u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2032             u32_tmp1 = u32_tmp1 / 5000000;
2033         } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2034             /* Symbol rate calculation */
2035             u32_tmp *= 512 ; /* 512 = 2**9 */
2036             u32_tmp = u32_tmp / adp_khz;
2037             u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2038             u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2039             u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2040
2041             /* SRC Gain Calculation */
2042             u32_tmp1 *= 512; /* *2*2^8 */
2043             u32_tmp1 /= 439; /* *2/878 */
2044             u32_tmp1 *= 256; /* *2^8 */
2045             u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2046             u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2047             u32_tmp1 = u32_tmp1 / 2500000;
2048         } else {
2049             /* Symbol rate calculation */
2050             u32_tmp *= 256 ; /* 256 = 2**8 */
2051             u32_tmp = u32_tmp / adp_khz;
2052             u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2053             u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2054             u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2055
2056             /* SRC Gain Calculation */
2057             u32_tmp1 *= 256; /* 2*2^7 */
2058             u32_tmp1 /= 439; /* *2/878 */
2059             u32_tmp1 *= 256; /* *2^8 */
2060             u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2061             u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2062             u32_tmp1 = u32_tmp1 / 1250000;
2063         }
2064     }
2065 #if 0
2066     /* Filters' coefficients are calculated and written
2067     into registers only if the filters are enabled */
2068     if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2069         stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2070                                 SymbolRate);
2071         /* AllPass filter must be enabled
2072         when the adjacents filter is used */
2073         stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2074         stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2075     } else
2076         /* AllPass filter must be disabled
2077         when the adjacents filter is not used */
2078 #endif
2079     stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2080
2081     stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2082     stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2083     stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2084     stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2085
2086     stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2087     stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2088
2089     return SymbolRate ;
2090 }
2091
2092 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2093 {
2094     u32 regsym;
2095     u32 adp_khz;
2096
2097     regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2098         (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2099         (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2100         (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2101
2102     adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2103
2104     if (regsym < 134217728) {       /* 134217728L = 2**27*/
2105         regsym = regsym * 32;       /* 32 = 2**5 */
2106         regsym = regsym / 32768;    /* 32768L = 2**15 */
2107         regsym = adp_khz * regsym;  /* AdpClk in kHz */
2108         regsym = regsym / 128;      /* 128 = 2**7 */
2109         regsym *= 125 ;         /* 125 = 1000/2**3 */
2110         regsym /= 2048 ;        /* 2048 = 2**11 */
2111     } else if (regsym < 268435456) {    /* 268435456L = 2**28 */
2112         regsym = regsym * 16;       /* 16 = 2**4 */
2113         regsym = regsym / 32768;    /* 32768L = 2**15 */
2114         regsym = adp_khz * regsym;  /* AdpClk in kHz */
2115         regsym = regsym / 128;      /* 128 = 2**7 */
2116         regsym *= 125 ;         /* 125 = 1000/2**3*/
2117         regsym /= 1024 ;        /* 256 = 2**10*/
2118     } else if (regsym < 536870912) {    /* 536870912L = 2**29*/
2119         regsym = regsym * 8;        /* 8 = 2**3 */
2120         regsym = regsym / 32768;    /* 32768L = 2**15 */
2121         regsym = adp_khz * regsym;  /* AdpClk in kHz */
2122         regsym = regsym / 128;      /* 128 = 2**7 */
2123         regsym *= 125 ;         /* 125 = 1000/2**3 */
2124         regsym /= 512 ;         /* 128 = 2**9 */
2125     } else {
2126         regsym = regsym * 4;        /* 4 = 2**2 */
2127         regsym = regsym / 32768;    /* 32768L = 2**15 */
2128         regsym = adp_khz * regsym;  /* AdpClk in kHz */
2129         regsym = regsym / 128;      /* 128 = 2**7 */
2130         regsym *= 125 ;         /* 125 = 1000/2**3 */
2131         regsym /= 256 ;         /* 64 = 2**8 */
2132     }
2133
2134     return regsym;
2135 }
2136
2137 static u32 stv0367cab_fsm_status(struct stv0367_state *state)
2138 {
2139     return stv0367_readbits(state, F367CAB_FSM_STATUS);
2140 }
2141
2142 static u32 stv0367cab_qamfec_lock(struct stv0367_state *state)
2143 {
2144     return stv0367_readbits(state,
2145         (state->cab_state->qamfec_status_reg ?
2146          state->cab_state->qamfec_status_reg :
2147          F367CAB_QAMFEC_LOCK));
2148 }
2149
2150 static
2151 enum stv0367_cab_signal_type stv0367cab_fsm_signaltype(u32 qam_fsm_status)
2152 {
2153     enum stv0367_cab_signal_type signaltype = FE_CAB_NOAGC;
2154
2155     switch (qam_fsm_status) {
2156     case 1:
2157         signaltype = FE_CAB_NOAGC;
2158         break;
2159     case 2:
2160         signaltype = FE_CAB_NOTIMING;
2161         break;
2162     case 3:
2163         signaltype = FE_CAB_TIMINGOK;
2164         break;
2165     case 4:
2166         signaltype = FE_CAB_NOCARRIER;
2167         break;
2168     case 5:
2169         signaltype = FE_CAB_CARRIEROK;
2170         break;
2171     case 7:
2172         signaltype = FE_CAB_NOBLIND;
2173         break;
2174     case 8:
2175         signaltype = FE_CAB_BLINDOK;
2176         break;
2177     case 10:
2178         signaltype = FE_CAB_NODEMOD;
2179         break;
2180     case 11:
2181         signaltype = FE_CAB_DEMODOK;
2182         break;
2183     case 12:
2184         signaltype = FE_CAB_DEMODOK;
2185         break;
2186     case 13:
2187         signaltype = FE_CAB_NODEMOD;
2188         break;
2189     case 14:
2190         signaltype = FE_CAB_NOBLIND;
2191         break;
2192     case 15:
2193         signaltype = FE_CAB_NOSIGNAL;
2194         break;
2195     default:
2196         break;
2197     }
2198
2199     return signaltype;
2200 }
2201
2202 static int stv0367cab_read_status(struct dvb_frontend *fe,
2203                   enum fe_status *status)
2204 {
2205     struct stv0367_state *state = fe->demodulator_priv;
2206
2207     dprintk("%s:\n", __func__);
2208
2209     *status = 0;
2210
2211     /* update cab_state->state from QAM_FSM_STATUS */
2212     state->cab_state->state = stv0367cab_fsm_signaltype(
2213         stv0367cab_fsm_status(state));
2214
2215     if (stv0367cab_qamfec_lock(state)) {
2216         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
2217               | FE_HAS_SYNC | FE_HAS_LOCK;
2218         dprintk("%s: stv0367 has locked\n", __func__);
2219     } else {
2220         if (state->cab_state->state > FE_CAB_NOSIGNAL)
2221             *status |= FE_HAS_SIGNAL;
2222
2223         if (state->cab_state->state > FE_CAB_NOCARRIER)
2224             *status |= FE_HAS_CARRIER;
2225
2226         if (state->cab_state->state >= FE_CAB_DEMODOK)
2227             *status |= FE_HAS_VITERBI;
2228
2229         if (state->cab_state->state >= FE_CAB_DATAOK)
2230             *status |= FE_HAS_SYNC;
2231     }
2232
2233     return 0;
2234 }
2235
2236 static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2237 {
2238     struct stv0367_state *state = fe->demodulator_priv;
2239
2240     dprintk("%s:\n", __func__);
2241
2242     if (standby_on) {
2243         stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2244         stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2245         stv0367_writebits(state, F367CAB_STDBY, 1);
2246         stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2247         stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2248         stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2249         stv0367_writebits(state, F367CAB_POFFQ, 1);
2250         stv0367_writebits(state, F367CAB_POFFI, 1);
2251     } else {
2252         stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2253         stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2254         stv0367_writebits(state, F367CAB_STDBY, 0);
2255         stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2256         stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2257         stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2258         stv0367_writebits(state, F367CAB_POFFQ, 0);
2259         stv0367_writebits(state, F367CAB_POFFI, 0);
2260     }
2261
2262     return 0;
2263 }
2264
2265 static int stv0367cab_sleep(struct dvb_frontend *fe)
2266 {
2267     return stv0367cab_standby(fe, 1);
2268 }
2269
2270 static int stv0367cab_init(struct dvb_frontend *fe)
2271 {
2272     struct stv0367_state *state = fe->demodulator_priv;
2273     struct stv0367cab_state *cab_state = state->cab_state;
2274
2275     dprintk("%s:\n", __func__);
2276
2277     stv0367_write_table(state,
2278         stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
2279
2280     switch (state->config->ts_mode) {
2281     case STV0367_DVBCI_CLOCK:
2282         dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2283         stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2284         break;
2285     case STV0367_SERIAL_PUNCT_CLOCK:
2286     case STV0367_SERIAL_CONT_CLOCK:
2287         stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2288         break;
2289     case STV0367_PARALLEL_PUNCT_CLOCK:
2290     case STV0367_OUTPUTMODE_DEFAULT:
2291         stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2292         break;
2293     }
2294
2295     switch (state->config->clk_pol) {
2296     case STV0367_RISINGEDGE_CLOCK:
2297         stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2298         break;
2299     case STV0367_FALLINGEDGE_CLOCK:
2300     case STV0367_CLOCKPOLARITY_DEFAULT:
2301         stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2302         break;
2303     }
2304
2305     stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2306
2307     stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2308
2309     stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2310
2311     stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2312
2313     stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2314
2315     cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2316     cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2317
2318     return 0;
2319 }
2320 static
2321 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2322                          struct dtv_frontend_properties *p)
2323 {
2324     struct stv0367cab_state *cab_state = state->cab_state;
2325     enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2326     u32 QAMFEC_Lock, QAM_Lock, u32_tmp, ifkhz,
2327         LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2328         CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2329     u8  TrackAGCAccum;
2330     s32 tmp;
2331
2332     dprintk("%s:\n", __func__);
2333
2334     stv0367_get_if_khz(state, &ifkhz);
2335
2336     /* Timeouts calculation */
2337     /* A max lock time of 25 ms is allowed for delayed AGC */
2338     AGCTimeOut = 25;
2339     /* 100000 symbols needed by the TRL as a maximum value */
2340     TRLTimeOut = 100000000 / p->symbol_rate;
2341     /* CRLSymbols is the needed number of symbols to achieve a lock
2342        within [-4%, +4%] of the symbol rate.
2343        CRL timeout is calculated
2344        for a lock within [-search_range, +search_range].
2345        EQL timeout can be changed depending on
2346        the micro-reflections we want to handle.
2347        A characterization must be performed
2348        with these echoes to get new timeout values.
2349     */
2350     switch (p->modulation) {
2351     case QAM_16:
2352         CRLSymbols = 150000;
2353         EQLTimeOut = 100;
2354         break;
2355     case QAM_32:
2356         CRLSymbols = 250000;
2357         EQLTimeOut = 100;
2358         break;
2359     case QAM_64:
2360         CRLSymbols = 200000;
2361         EQLTimeOut = 100;
2362         break;
2363     case QAM_128:
2364         CRLSymbols = 250000;
2365         EQLTimeOut = 100;
2366         break;
2367     case QAM_256:
2368         CRLSymbols = 250000;
2369         EQLTimeOut = 100;
2370         break;
2371     default:
2372         CRLSymbols = 200000;
2373         EQLTimeOut = 100;
2374         break;
2375     }
2376 #if 0
2377     if (pIntParams->search_range < 0) {
2378         CRLTimeOut = (25 * CRLSymbols *
2379                 (-pIntParams->search_range / 1000)) /
2380                     (pIntParams->symbol_rate / 1000);
2381     } else
2382 #endif
2383     CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2384                     (p->symbol_rate / 1000);
2385
2386     CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
2387     /* Timeouts below 50ms are coerced */
2388     if (CRLTimeOut < 50)
2389         CRLTimeOut = 50;
2390     /* A maximum of 100 TS packets is needed to get FEC lock even in case
2391     the spectrum inversion needs to be changed.
2392        This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2393     */
2394     FECTimeOut = 20;
2395     DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2396
2397     dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2398
2399     /* Reset the TRL to ensure nothing starts until the
2400        AGC is stable which ensures a better lock time
2401     */
2402     stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2403     /* Set AGC accumulation time to minimum and lock threshold to maximum
2404     in order to speed up the AGC lock */
2405     TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2406     stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2407     /* Modulus Mapper is disabled */
2408     stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2409     /* Disable the sweep function */
2410     stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2411     /* The sweep function is never used, Sweep rate must be set to 0 */
2412     /* Set the derotator frequency in Hz */
2413     stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2414         (1000 * (s32)ifkhz + cab_state->derot_offset));
2415     /* Disable the Allpass Filter when the symbol rate is out of range */
2416     if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
2417         stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2418         stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2419     }
2420 #if 0
2421     /* Check if the tuner is locked */
2422     tuner_lock = stv0367cab_tuner_get_status(fe);
2423     if (tuner_lock == 0)
2424         return FE_367CAB_NOTUNER;
2425 #endif
2426     /* Release the TRL to start demodulator acquisition */
2427     /* Wait for QAM lock */
2428     LockTime = 0;
2429     stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2430     do {
2431         QAM_Lock = stv0367cab_fsm_status(state);
2432         if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2433                             (QAM_Lock == 0x04))
2434             /*
2435              * We don't wait longer, the frequency/phase offset
2436              * must be too big
2437              */
2438             LockTime = DemodTimeOut;
2439         else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2440                             (QAM_Lock == 0x02))
2441             /*
2442              * We don't wait longer, either there is no signal or
2443              * it is not the right symbol rate or it is an analog
2444              * carrier
2445              */
2446         {
2447             LockTime = DemodTimeOut;
2448             u32_tmp = stv0367_readbits(state,
2449                         F367CAB_AGC_PWR_WORD_LO) +
2450                     (stv0367_readbits(state,
2451                         F367CAB_AGC_PWR_WORD_ME) << 8) +
2452                     (stv0367_readbits(state,
2453                         F367CAB_AGC_PWR_WORD_HI) << 16);
2454             if (u32_tmp >= 131072)
2455                 u32_tmp = 262144 - u32_tmp;
2456             u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2457                             F367CAB_AGC_IF_BWSEL)));
2458
2459             if (u32_tmp < stv0367_readbits(state,
2460                         F367CAB_AGC_PWRREF_LO) +
2461                     256 * stv0367_readbits(state,
2462                         F367CAB_AGC_PWRREF_HI) - 10)
2463                 QAM_Lock = 0x0f;
2464         } else {
2465             usleep_range(10000, 20000);
2466             LockTime += 10;
2467         }
2468         dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2469         tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2470
2471         dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2472
2473     } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2474                         (LockTime < DemodTimeOut));
2475
2476     dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2477
2478     tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2479     dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2480     tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2481     dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2482
2483     tmp  = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2484     dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2485
2486     if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2487         /* Wait for FEC lock */
2488         LockTime = 0;
2489         do {
2490             usleep_range(5000, 7000);
2491             LockTime += 5;
2492             QAMFEC_Lock = stv0367cab_qamfec_lock(state);
2493         } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
2494     } else
2495         QAMFEC_Lock = 0;
2496
2497     if (QAMFEC_Lock) {
2498         signalType = FE_CAB_DATAOK;
2499         cab_state->spect_inv = stv0367_readbits(state,
2500                             F367CAB_QUAD_INV);
2501 #if 0
2502 /* not clear for me */
2503         if (ifkhz != 0) {
2504             if (ifkhz > cab_state->adc_clk / 1000) {
2505                 cab_state->freq_khz =
2506                     FE_Cab_TunerGetFrequency(pIntParams->hTuner)
2507                 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2508                 - cab_state->adc_clk / 1000 + ifkhz;
2509             } else {
2510                 cab_state->freq_khz =
2511                         FE_Cab_TunerGetFrequency(pIntParams->hTuner)
2512                         - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2513                         + ifkhz;
2514             }
2515         } else {
2516             cab_state->freq_khz =
2517                 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
2518                 stv0367cab_get_derot_freq(state,
2519                             cab_state->adc_clk) -
2520                 cab_state->adc_clk / 4000;
2521         }
2522 #endif
2523         cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
2524                             cab_state->mclk);
2525         cab_state->locked = 1;
2526
2527         /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
2528     } else
2529         signalType = stv0367cab_fsm_signaltype(QAM_Lock);
2530
2531     /* Set the AGC control values to tracking values */
2532     stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
2533     return signalType;
2534 }
2535
2536 static int stv0367cab_set_frontend(struct dvb_frontend *fe)
2537 {
2538     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2539     struct stv0367_state *state = fe->demodulator_priv;
2540     struct stv0367cab_state *cab_state = state->cab_state;
2541     enum stv0367cab_mod QAMSize = 0;
2542
2543     dprintk("%s: freq = %d, srate = %d\n", __func__,
2544                     p->frequency, p->symbol_rate);
2545
2546     cab_state->derot_offset = 0;
2547
2548     switch (p->modulation) {
2549     case QAM_16:
2550         QAMSize = FE_CAB_MOD_QAM16;
2551         break;
2552     case QAM_32:
2553         QAMSize = FE_CAB_MOD_QAM32;
2554         break;
2555     case QAM_64:
2556         QAMSize = FE_CAB_MOD_QAM64;
2557         break;
2558     case QAM_128:
2559         QAMSize = FE_CAB_MOD_QAM128;
2560         break;
2561     case QAM_256:
2562         QAMSize = FE_CAB_MOD_QAM256;
2563         break;
2564     default:
2565         break;
2566     }
2567
2568     if (state->reinit_on_setfrontend)
2569         stv0367cab_init(fe);
2570
2571     /* Tuner Frequency Setting */
2572     if (fe->ops.tuner_ops.set_params) {
2573         if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
2574             fe->ops.i2c_gate_ctrl(fe, 1);
2575         fe->ops.tuner_ops.set_params(fe);
2576         if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
2577             fe->ops.i2c_gate_ctrl(fe, 0);
2578     }
2579
2580     stv0367cab_SetQamSize(
2581             state,
2582             p->symbol_rate,
2583             QAMSize);
2584
2585     stv0367cab_set_srate(state,
2586             cab_state->adc_clk,
2587             cab_state->mclk,
2588             p->symbol_rate,
2589             QAMSize);
2590     /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
2591     cab_state->state = stv0367cab_algo(state, p);
2592     return 0;
2593 }
2594
2595 static int stv0367cab_get_frontend(struct dvb_frontend *fe,
2596                    struct dtv_frontend_properties *p)
2597 {
2598     struct stv0367_state *state = fe->demodulator_priv;
2599     struct stv0367cab_state *cab_state = state->cab_state;
2600     u32 ifkhz = 0;
2601
2602     enum stv0367cab_mod QAMSize;
2603
2604     dprintk("%s:\n", __func__);
2605
2606     stv0367_get_if_khz(state, &ifkhz);
2607     p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
2608
2609     QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2610     switch (QAMSize) {
2611     case FE_CAB_MOD_QAM16:
2612         p->modulation = QAM_16;
2613         break;
2614     case FE_CAB_MOD_QAM32:
2615         p->modulation = QAM_32;
2616         break;
2617     case FE_CAB_MOD_QAM64:
2618         p->modulation = QAM_64;
2619         break;
2620     case FE_CAB_MOD_QAM128:
2621         p->modulation = QAM_128;
2622         break;
2623     case FE_CAB_MOD_QAM256:
2624         p->modulation = QAM_256;
2625         break;
2626     default:
2627         break;
2628     }
2629
2630     p->frequency = stv0367_get_tuner_freq(fe);
2631
2632     dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
2633
2634     if (ifkhz == 0) {
2635         p->frequency +=
2636             (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
2637             cab_state->adc_clk / 4000);
2638         return 0;
2639     }
2640
2641     if (ifkhz > cab_state->adc_clk / 1000)
2642         p->frequency += (ifkhz
2643             - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2644             - cab_state->adc_clk / 1000);
2645     else
2646         p->frequency += (ifkhz
2647             - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
2648
2649     return 0;
2650 }
2651
2652 #if 0
2653 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
2654             u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
2655 {
2656     stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
2657     stv0367cab_GetPacketsCount(state, Monitor_results);
2658
2659     return;
2660 }
2661
2662 static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
2663 {
2664     struct stv0367_state *state = fe->demodulator_priv;
2665
2666     return 0;
2667 }
2668 #endif
2669 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
2670 {
2671     s32 rfLevel = 0;
2672     s32 RfAgcPwm = 0, IfAgcPwm = 0;
2673     u8 i;
2674
2675     stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
2676
2677     RfAgcPwm =
2678         (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
2679         (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
2680     RfAgcPwm = 100 * RfAgcPwm / 1023;
2681
2682     IfAgcPwm =
2683         stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
2684         (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
2685     if (IfAgcPwm >= 2048)
2686         IfAgcPwm -= 2048;
2687     else
2688         IfAgcPwm += 2048;
2689
2690     IfAgcPwm = 100 * IfAgcPwm / 4095;
2691
2692     /* For DTT75467 on NIM */
2693     if (RfAgcPwm < 90  && IfAgcPwm < 28) {
2694         for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
2695             if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
2696                 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
2697                 break;
2698             }
2699         }
2700         if (i == RF_LOOKUP_TABLE_SIZE)
2701             rfLevel = -56;
2702     } else { /*if IF AGC>10*/
2703         for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
2704             if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
2705                 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
2706                 break;
2707             }
2708         }
2709         if (i == RF_LOOKUP_TABLE2_SIZE)
2710             rfLevel = -72;
2711     }
2712     return rfLevel;
2713 }
2714
2715 static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
2716 {
2717     struct stv0367_state *state = fe->demodulator_priv;
2718
2719     s32 signal =  stv0367cab_get_rf_lvl(state);
2720
2721     dprintk("%s: signal=%d dBm\n", __func__, signal);
2722
2723     if (signal <= -72)
2724         *strength = 65535;
2725     else
2726         *strength = (22 + signal) * (-1311);
2727
2728     dprintk("%s: strength=%d\n", __func__, (*strength));
2729
2730     return 0;
2731 }
2732
2733 static int stv0367cab_snr_power(struct dvb_frontend *fe)
2734 {
2735     struct stv0367_state *state = fe->demodulator_priv;
2736     enum stv0367cab_mod QAMSize;
2737
2738     QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2739     switch (QAMSize) {
2740     case FE_CAB_MOD_QAM4:
2741         return 21904;
2742     case FE_CAB_MOD_QAM16:
2743         return 20480;
2744     case FE_CAB_MOD_QAM32:
2745         return 23040;
2746     case FE_CAB_MOD_QAM64:
2747         return 21504;
2748     case FE_CAB_MOD_QAM128:
2749         return 23616;
2750     case FE_CAB_MOD_QAM256:
2751         return 21760;
2752     case FE_CAB_MOD_QAM1024:
2753         return 21280;
2754     default:
2755         break;
2756     }
2757
2758     return 1;
2759 }
2760
2761 static int stv0367cab_snr_readreg(struct dvb_frontend *fe, int avgdiv)
2762 {
2763     struct stv0367_state *state = fe->demodulator_priv;
2764     u32 regval = 0;
2765     int i;
2766
2767     for (i = 0; i < 10; i++) {
2768         regval += (stv0367_readbits(state, F367CAB_SNR_LO)
2769             + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
2770     }
2771
2772     if (avgdiv)
2773         regval /= 10;
2774
2775     return regval;
2776 }
2777
2778 static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
2779 {
2780     struct stv0367_state *state = fe->demodulator_priv;
2781     u32 noisepercentage;
2782     u32 regval = 0, temp = 0;
2783     int power;
2784
2785     power = stv0367cab_snr_power(fe);
2786     regval = stv0367cab_snr_readreg(fe, 1);
2787
2788     if (regval != 0) {
2789         temp = power
2790             * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
2791         temp /= regval;
2792     }
2793
2794     /* table values, not needed to calculate logarithms */
2795     if (temp >= 5012)
2796         noisepercentage = 100;
2797     else if (temp >= 3981)
2798         noisepercentage = 93;
2799     else if (temp >= 3162)
2800         noisepercentage = 86;
2801     else if (temp >= 2512)
2802         noisepercentage = 79;
2803     else if (temp >= 1995)
2804         noisepercentage = 72;
2805     else if (temp >= 1585)
2806         noisepercentage = 65;
2807     else if (temp >= 1259)
2808         noisepercentage = 58;
2809     else if (temp >= 1000)
2810         noisepercentage = 50;
2811     else if (temp >= 794)
2812         noisepercentage = 43;
2813     else if (temp >= 501)
2814         noisepercentage = 36;
2815     else if (temp >= 316)
2816         noisepercentage = 29;
2817     else if (temp >= 200)
2818         noisepercentage = 22;
2819     else if (temp >= 158)
2820         noisepercentage = 14;
2821     else if (temp >= 126)
2822         noisepercentage = 7;
2823     else
2824         noisepercentage = 0;
2825
2826     dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
2827
2828     *snr = (noisepercentage * 65535) / 100;
2829
2830     return 0;
2831 }
2832
2833 static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
2834 {
2835     struct stv0367_state *state = fe->demodulator_priv;
2836     int corrected, tscount;
2837
2838     *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
2839             | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
2840     corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
2841             | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
2842     tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
2843             | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
2844
2845     dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
2846                 __func__, *ucblocks, corrected, tscount);
2847
2848     return 0;
2849 };
2850
2851 static const struct dvb_frontend_ops stv0367cab_ops = {
2852     .delsys = { SYS_DVBC_ANNEX_A },
2853     .info = {
2854         .name = "ST STV0367 DVB-C",
2855         .frequency_min_hz =  47 * MHz,
2856         .frequency_max_hz = 862 * MHz,
2857         .frequency_stepsize_hz = 62500,
2858         .symbol_rate_min = 870000,
2859         .symbol_rate_max = 11700000,
2860         .caps = 0x400 |/* FE_CAN_QAM_4 */
2861             FE_CAN_QAM_16 | FE_CAN_QAM_32  |
2862             FE_CAN_QAM_64 | FE_CAN_QAM_128 |
2863             FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
2864     },
2865     .release                = stv0367_release,
2866     .init                   = stv0367cab_init,
2867     .sleep                  = stv0367cab_sleep,
2868     .i2c_gate_ctrl              = stv0367cab_gate_ctrl,
2869     .set_frontend               = stv0367cab_set_frontend,
2870     .get_frontend               = stv0367cab_get_frontend,
2871     .read_status                = stv0367cab_read_status,
2872 /*  .read_ber               = stv0367cab_read_ber, */
2873     .read_signal_strength           = stv0367cab_read_strength,
2874     .read_snr               = stv0367cab_read_snr,
2875     .read_ucblocks              = stv0367cab_read_ucblcks,
2876     .get_tune_settings          = stv0367_get_tune_settings,
2877 };
2878
2879 struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
2880                    struct i2c_adapter *i2c)
2881 {
2882     struct stv0367_state *state = NULL;
2883     struct stv0367cab_state *cab_state = NULL;
2884
2885     /* allocate memory for the internal state */
2886     state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2887     if (state == NULL)
2888         goto error;
2889     cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
2890     if (cab_state == NULL)
2891         goto error;
2892
2893     /* setup the state */
2894     state->i2c = i2c;
2895     state->config = config;
2896     cab_state->search_range = 280000;
2897     cab_state->qamfec_status_reg = F367CAB_QAMFEC_LOCK;
2898     state->cab_state = cab_state;
2899     state->fe.ops = stv0367cab_ops;
2900     state->fe.demodulator_priv = state;
2901     state->chip_id = stv0367_readreg(state, 0xf000);
2902
2903     /* demod operation options */
2904     state->use_i2c_gatectrl = 1;
2905     state->deftabs = STV0367_DEFTAB_GENERIC;
2906     state->reinit_on_setfrontend = 1;
2907     state->auto_if_khz = 0;
2908
2909     dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2910
2911     /* check if the demod is there */
2912     if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2913         goto error;
2914
2915     return &state->fe;
2916
2917 error:
2918     kfree(cab_state);
2919     kfree(state);
2920     return NULL;
2921 }
2922 EXPORT_SYMBOL(stv0367cab_attach);
2923
2924 /*
2925  * Functions for operation on Digital Devices hardware
2926  */
2927
2928 static void stv0367ddb_setup_ter(struct stv0367_state *state)
2929 {
2930     stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2931     stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00);
2932     stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */
2933     stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */
2934     stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2935     stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2936
2937     /* Tuner Setup */
2938     /* Buffer Q disabled, I Enabled, unsigned ADC */
2939     stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89);
2940     stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
2941
2942     /* Clock setup */
2943     /* PLL bypassed and disabled */
2944     stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2945     stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */
2946
2947     /* IC runs at 54 MHz with a 27 MHz crystal */
2948     stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
2949
2950     msleep(50);
2951     /* PLL enabled and used */
2952     stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2953
2954     state->activedemod = demod_ter;
2955 }
2956
2957 static void stv0367ddb_setup_cab(struct stv0367_state *state)
2958 {
2959     stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2960     stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01);
2961     stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */
2962     stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */
2963     stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2964     stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2965
2966     /* Tuner Setup */
2967     /* Buffer Q disabled, I Enabled, signed ADC */
2968     stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B);
2969     /* ADCQ disabled */
2970     stv0367_writereg(state, R367TER_DUAL_AD12, 0x04);
2971
2972     /* Clock setup */
2973     /* PLL bypassed and disabled */
2974     stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2975     /* Set QAM */
2976     stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
2977
2978     /* IC runs at 58 MHz with a 27 MHz crystal */
2979     stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
2980
2981     msleep(50);
2982     /* PLL enabled and used */
2983     stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2984
2985     state->cab_state->mclk = stv0367cab_get_mclk(&state->fe,
2986         state->config->xtal);
2987     state->cab_state->adc_clk = stv0367cab_get_adc_freq(&state->fe,
2988         state->config->xtal);
2989
2990     state->activedemod = demod_cab;
2991 }
2992
2993 static int stv0367ddb_set_frontend(struct dvb_frontend *fe)
2994 {
2995     struct stv0367_state *state = fe->demodulator_priv;
2996
2997     switch (fe->dtv_property_cache.delivery_system) {
2998     case SYS_DVBT:
2999         if (state->activedemod != demod_ter)
3000             stv0367ddb_setup_ter(state);
3001
3002         return stv0367ter_set_frontend(fe);
3003     case SYS_DVBC_ANNEX_A:
3004         if (state->activedemod != demod_cab)
3005             stv0367ddb_setup_cab(state);
3006
3007         /* protect against division error oopses */
3008         if (fe->dtv_property_cache.symbol_rate == 0) {
3009             printk(KERN_ERR "Invalid symbol rate\n");
3010             return -EINVAL;
3011         }
3012
3013         return stv0367cab_set_frontend(fe);
3014     default:
3015         break;
3016     }
3017
3018     return -EINVAL;
3019 }
3020
3021 static void stv0367ddb_read_signal_strength(struct dvb_frontend *fe)
3022 {
3023     struct stv0367_state *state = fe->demodulator_priv;
3024     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3025     s32 signalstrength;
3026
3027     switch (state->activedemod) {
3028     case demod_cab:
3029         signalstrength = stv0367cab_get_rf_lvl(state) * 1000;
3030         break;
3031     default:
3032         p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3033         return;
3034     }
3035
3036     p->strength.stat[0].scale = FE_SCALE_DECIBEL;
3037     p->strength.stat[0].uvalue = signalstrength;
3038 }
3039
3040 static void stv0367ddb_read_snr(struct dvb_frontend *fe)
3041 {
3042     struct stv0367_state *state = fe->demodulator_priv;
3043     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3044     int cab_pwr;
3045     u32 regval, tmpval, snrval = 0;
3046
3047     switch (state->activedemod) {
3048     case demod_ter:
3049         snrval = stv0367ter_snr_readreg(fe);
3050         break;
3051     case demod_cab:
3052         cab_pwr = stv0367cab_snr_power(fe);
3053         regval = stv0367cab_snr_readreg(fe, 0);
3054
3055         /* prevent division by zero */
3056         if (!regval) {
3057             snrval = 0;
3058             break;
3059         }
3060
3061         tmpval = (cab_pwr * 320) / regval;
3062         snrval = ((tmpval != 0) ? (intlog2(tmpval) / 5581) : 0);
3063         break;
3064     default:
3065         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3066         return;
3067     }
3068
3069     p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
3070     p->cnr.stat[0].uvalue = snrval;
3071 }
3072
3073 static void stv0367ddb_read_ucblocks(struct dvb_frontend *fe)
3074 {
3075     struct stv0367_state *state = fe->demodulator_priv;
3076     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3077     u32 ucblocks = 0;
3078
3079     switch (state->activedemod) {
3080     case demod_ter:
3081         stv0367ter_read_ucblocks(fe, &ucblocks);
3082         break;
3083     case demod_cab:
3084         stv0367cab_read_ucblcks(fe, &ucblocks);
3085         break;
3086     default:
3087         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3088         return;
3089     }
3090
3091     p->block_error.stat[0].scale = FE_SCALE_COUNTER;
3092     p->block_error.stat[0].uvalue = ucblocks;
3093 }
3094
3095 static int stv0367ddb_read_status(struct dvb_frontend *fe,
3096                   enum fe_status *status)
3097 {
3098     struct stv0367_state *state = fe->demodulator_priv;
3099     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3100     int ret = 0;
3101
3102     switch (state->activedemod) {
3103     case demod_ter:
3104         ret = stv0367ter_read_status(fe, status);
3105         break;
3106     case demod_cab:
3107         ret = stv0367cab_read_status(fe, status);
3108         break;
3109     default:
3110         break;
3111     }
3112
3113     /* stop and report on *_read_status failure */
3114     if (ret)
3115         return ret;
3116
3117     stv0367ddb_read_signal_strength(fe);
3118
3119     /* read carrier/noise when a carrier is detected */
3120     if (*status & FE_HAS_CARRIER)
3121         stv0367ddb_read_snr(fe);
3122     else
3123         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3124
3125     /* read uncorrected blocks on FE_HAS_LOCK */
3126     if (*status & FE_HAS_LOCK)
3127         stv0367ddb_read_ucblocks(fe);
3128     else
3129         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3130
3131     return 0;
3132 }
3133
3134 static int stv0367ddb_get_frontend(struct dvb_frontend *fe,
3135                    struct dtv_frontend_properties *p)
3136 {
3137     struct stv0367_state *state = fe->demodulator_priv;
3138
3139     switch (state->activedemod) {
3140     case demod_ter:
3141         return stv0367ter_get_frontend(fe, p);
3142     case demod_cab:
3143         return stv0367cab_get_frontend(fe, p);
3144     default:
3145         break;
3146     }
3147
3148     return 0;
3149 }
3150
3151 static int stv0367ddb_sleep(struct dvb_frontend *fe)
3152 {
3153     struct stv0367_state *state = fe->demodulator_priv;
3154
3155     switch (state->activedemod) {
3156     case demod_ter:
3157         state->activedemod = demod_none;
3158         return stv0367ter_sleep(fe);
3159     case demod_cab:
3160         state->activedemod = demod_none;
3161         return stv0367cab_sleep(fe);
3162     default:
3163         break;
3164     }
3165
3166     return -EINVAL;
3167 }
3168
3169 static int stv0367ddb_init(struct stv0367_state *state)
3170 {
3171     struct stv0367ter_state *ter_state = state->ter_state;
3172     struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
3173
3174     stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3175
3176     if (stv0367_deftabs[state->deftabs][STV0367_TAB_BASE])
3177         stv0367_write_table(state,
3178             stv0367_deftabs[state->deftabs][STV0367_TAB_BASE]);
3179
3180     stv0367_write_table(state,
3181         stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
3182
3183     stv0367_writereg(state, R367TER_TOPCTRL, 0x00);
3184     stv0367_write_table(state,
3185         stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
3186
3187     stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A);
3188     stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6);
3189     stv0367_writereg(state, R367TER_INC_DEROT1, 0x55);
3190     stv0367_writereg(state, R367TER_INC_DEROT2, 0x55);
3191     stv0367_writereg(state, R367TER_TRL_CTL, 0x14);
3192     stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE);
3193     stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56);
3194     stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0);
3195
3196     /* OFDM TS Setup */
3197
3198     stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3199     stv0367_writereg(state, R367TER_TSCFGM, 0xC0);
3200     stv0367_writereg(state, R367TER_TSCFGL, 0x20);
3201     stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */
3202
3203     stv0367_writereg(state, R367TER_TSCFGH, 0x71);
3204     stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3205
3206     stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3207
3208     /* Also needed for QAM */
3209     stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */
3210
3211     stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A);
3212
3213     /* QAM TS setup, note exact format also depends on descrambler */
3214     /* settings */
3215     /* Inverted Clock, Swap, serial */
3216     stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85);
3217
3218     /* Clock setup (PLL bypassed and disabled) */
3219     stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
3220
3221     /* IC runs at 58 MHz with a 27 MHz crystal */
3222     stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
3223
3224     /* Tuner setup */
3225     /* Buffer Q disabled, I Enabled, signed ADC */
3226     stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b);
3227     stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
3228
3229     /* Improves the C/N lock limit */
3230     stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23);
3231     /* ZIF/IF Automatic mode */
3232     stv0367_writereg(state, R367CAB_IQ_QAM, 0x01);
3233     /* Improving burst noise performances */
3234     stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83);
3235     /* Improving ACI performances */
3236     stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05);
3237
3238     /* PLL enabled and used */
3239     stv0367_writereg(state, R367TER_ANACTRL, 0x00);
3240
3241     stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4)));
3242
3243     ter_state->pBER = 0;
3244     ter_state->first_lock = 0;
3245     ter_state->unlock_counter = 2;
3246
3247     p->strength.len = 1;
3248     p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3249     p->cnr.len = 1;
3250     p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3251     p->block_error.len = 1;
3252     p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3253
3254     return 0;
3255 }
3256
3257 static const struct dvb_frontend_ops stv0367ddb_ops = {
3258     .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT },
3259     .info = {
3260         .name           = "ST STV0367 DDB DVB-C/T",
3261         .frequency_min_hz   =  47 * MHz,
3262         .frequency_max_hz   = 865 * MHz,
3263         .frequency_stepsize_hz  = 166667,
3264         .symbol_rate_min    = 870000,
3265         .symbol_rate_max    = 11700000,
3266         .caps = /* DVB-C */
3267             0x400 |/* FE_CAN_QAM_4 */
3268             FE_CAN_QAM_16 | FE_CAN_QAM_32  |
3269             FE_CAN_QAM_64 | FE_CAN_QAM_128 |
3270             FE_CAN_QAM_256 |
3271             /* DVB-T */
3272             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
3273             FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
3274             FE_CAN_QPSK | FE_CAN_TRANSMISSION_MODE_AUTO |
3275             FE_CAN_RECOVER | FE_CAN_INVERSION_AUTO |
3276             FE_CAN_MUTE_TS
3277     },
3278     .release = stv0367_release,
3279     .sleep = stv0367ddb_sleep,
3280     .i2c_gate_ctrl = stv0367cab_gate_ctrl, /* valid for TER and CAB */
3281     .set_frontend = stv0367ddb_set_frontend,
3282     .get_frontend = stv0367ddb_get_frontend,
3283     .get_tune_settings = stv0367_get_tune_settings,
3284     .read_status = stv0367ddb_read_status,
3285 };
3286
3287 struct dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config,
3288                    struct i2c_adapter *i2c)
3289 {
3290     struct stv0367_state *state = NULL;
3291     struct stv0367ter_state *ter_state = NULL;
3292     struct stv0367cab_state *cab_state = NULL;
3293
3294     /* allocate memory for the internal state */
3295     state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3296     if (state == NULL)
3297         goto error;
3298     ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
3299     if (ter_state == NULL)
3300         goto error;
3301     cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3302     if (cab_state == NULL)
3303         goto error;
3304
3305     /* setup the state */
3306     state->i2c = i2c;
3307     state->config = config;
3308     state->ter_state = ter_state;
3309     cab_state->search_range = 280000;
3310     cab_state->qamfec_status_reg = F367CAB_DESCR_SYNCSTATE;
3311     state->cab_state = cab_state;
3312     state->fe.ops = stv0367ddb_ops;
3313     state->fe.demodulator_priv = state;
3314     state->chip_id = stv0367_readreg(state, R367TER_ID);
3315
3316     /* demod operation options */
3317     state->use_i2c_gatectrl = 0;
3318     state->deftabs = STV0367_DEFTAB_DDB;
3319     state->reinit_on_setfrontend = 0;
3320     state->auto_if_khz = 1;
3321     state->activedemod = demod_none;
3322
3323     dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3324
3325     /* check if the demod is there */
3326     if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3327         goto error;
3328
3329     dev_info(&i2c->dev, "Found %s with ChipID %02X at adr %02X\n",
3330         state->fe.ops.info.name, state->chip_id,
3331         config->demod_address);
3332
3333     stv0367ddb_init(state);
3334
3335     return &state->fe;
3336
3337 error:
3338     kfree(cab_state);
3339     kfree(ter_state);
3340     kfree(state);
3341     return NULL;
3342 }
3343 EXPORT_SYMBOL(stv0367ddb_attach);
3344
3345 MODULE_PARM_DESC(debug, "Set debug");
3346 MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3347
3348 MODULE_AUTHOR("Igor M. Liplianin");
3349 MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3350 MODULE_LICENSE("GPL");