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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003     Driver for STV0297 demodulator
0004 
0005     Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
0006     Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de>
0007 
0008 */
0009 
0010 #include <linux/init.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/string.h>
0014 #include <linux/delay.h>
0015 #include <linux/jiffies.h>
0016 #include <linux/slab.h>
0017 
0018 #include <media/dvb_frontend.h>
0019 #include "stv0297.h"
0020 
0021 struct stv0297_state {
0022     struct i2c_adapter *i2c;
0023     const struct stv0297_config *config;
0024     struct dvb_frontend frontend;
0025 
0026     unsigned long last_ber;
0027     unsigned long base_freq;
0028 };
0029 
0030 #if 1
0031 #define dprintk(x...) printk(x)
0032 #else
0033 #define dprintk(x...)
0034 #endif
0035 
0036 #define STV0297_CLOCK_KHZ   28900
0037 
0038 
0039 static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
0040 {
0041     int ret;
0042     u8 buf[] = { reg, data };
0043     struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
0044 
0045     ret = i2c_transfer(state->i2c, &msg, 1);
0046 
0047     if (ret != 1)
0048         dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
0049             __func__, reg, data, ret);
0050 
0051     return (ret != 1) ? -1 : 0;
0052 }
0053 
0054 static int stv0297_readreg(struct stv0297_state *state, u8 reg)
0055 {
0056     int ret;
0057     u8 b0[] = { reg };
0058     u8 b1[] = { 0 };
0059     struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1},
0060                  {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
0061                    };
0062 
0063     // this device needs a STOP between the register and data
0064     if (state->config->stop_during_read) {
0065         if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
0066             dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
0067             return -1;
0068         }
0069         if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
0070             dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
0071             return -1;
0072         }
0073     } else {
0074         if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
0075             dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret);
0076             return -1;
0077         }
0078     }
0079 
0080     return b1[0];
0081 }
0082 
0083 static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
0084 {
0085     int val;
0086 
0087     val = stv0297_readreg(state, reg);
0088     val &= ~mask;
0089     val |= (data & mask);
0090     stv0297_writereg(state, reg, val);
0091 
0092     return 0;
0093 }
0094 
0095 static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len)
0096 {
0097     int ret;
0098     struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
0099                   &reg1,.len = 1},
0100     {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
0101     };
0102 
0103     // this device needs a STOP between the register and data
0104     if (state->config->stop_during_read) {
0105         if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
0106             dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
0107             return -1;
0108         }
0109         if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
0110             dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
0111             return -1;
0112         }
0113     } else {
0114         if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
0115             dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
0116             return -1;
0117         }
0118     }
0119 
0120     return 0;
0121 }
0122 
0123 static u32 stv0297_get_symbolrate(struct stv0297_state *state)
0124 {
0125     u64 tmp;
0126 
0127     tmp = (u64)(stv0297_readreg(state, 0x55)
0128             | (stv0297_readreg(state, 0x56) << 8)
0129             | (stv0297_readreg(state, 0x57) << 16)
0130             | (stv0297_readreg(state, 0x58) << 24));
0131 
0132     tmp *= STV0297_CLOCK_KHZ;
0133     tmp >>= 32;
0134 
0135     return (u32) tmp;
0136 }
0137 
0138 static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
0139 {
0140     long tmp;
0141 
0142     tmp = 131072L * srate;  /* 131072 = 2^17  */
0143     tmp = tmp / (STV0297_CLOCK_KHZ / 4);    /* 1/4 = 2^-2 */
0144     tmp = tmp * 8192L;  /* 8192 = 2^13 */
0145 
0146     stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
0147     stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
0148     stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
0149     stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
0150 }
0151 
0152 static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
0153 {
0154     long tmp;
0155 
0156     tmp = (long) fshift *262144L;   /* 262144 = 2*18 */
0157     tmp /= symrate;
0158     tmp *= 1024;        /* 1024 = 2*10   */
0159 
0160     // adjust
0161     if (tmp >= 0) {
0162         tmp += 500000;
0163     } else {
0164         tmp -= 500000;
0165     }
0166     tmp /= 1000000;
0167 
0168     stv0297_writereg(state, 0x60, tmp & 0xFF);
0169     stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
0170 }
0171 
0172 static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
0173 {
0174     long tmp;
0175 
0176     /* symrate is hardcoded to 10000 */
0177     tmp = offset * 26844L;  /* (2**28)/10000 */
0178     if (tmp < 0)
0179         tmp += 0x10000000;
0180     tmp &= 0x0FFFFFFF;
0181 
0182     stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
0183     stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
0184     stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
0185     stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
0186 }
0187 
0188 /*
0189 static long stv0297_get_carrieroffset(struct stv0297_state *state)
0190 {
0191     s64 tmp;
0192 
0193     stv0297_writereg(state, 0x6B, 0x00);
0194 
0195     tmp = stv0297_readreg(state, 0x66);
0196     tmp |= (stv0297_readreg(state, 0x67) << 8);
0197     tmp |= (stv0297_readreg(state, 0x68) << 16);
0198     tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
0199 
0200     tmp *= stv0297_get_symbolrate(state);
0201     tmp >>= 28;
0202 
0203     return (s32) tmp;
0204 }
0205 */
0206 
0207 static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
0208 {
0209     s32 tmp;
0210 
0211     if (freq > 10000)
0212         freq -= STV0297_CLOCK_KHZ;
0213 
0214     tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
0215     tmp = (freq * 1000) / tmp;
0216     if (tmp > 0xffff)
0217         tmp = 0xffff;
0218 
0219     stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
0220     stv0297_writereg(state, 0x21, tmp >> 8);
0221     stv0297_writereg(state, 0x20, tmp);
0222 }
0223 
0224 static int stv0297_set_qam(struct stv0297_state *state,
0225                enum fe_modulation modulation)
0226 {
0227     int val = 0;
0228 
0229     switch (modulation) {
0230     case QAM_16:
0231         val = 0;
0232         break;
0233 
0234     case QAM_32:
0235         val = 1;
0236         break;
0237 
0238     case QAM_64:
0239         val = 4;
0240         break;
0241 
0242     case QAM_128:
0243         val = 2;
0244         break;
0245 
0246     case QAM_256:
0247         val = 3;
0248         break;
0249 
0250     default:
0251         return -EINVAL;
0252     }
0253 
0254     stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
0255 
0256     return 0;
0257 }
0258 
0259 static int stv0297_set_inversion(struct stv0297_state *state,
0260                  enum fe_spectral_inversion inversion)
0261 {
0262     int val = 0;
0263 
0264     switch (inversion) {
0265     case INVERSION_OFF:
0266         val = 0;
0267         break;
0268 
0269     case INVERSION_ON:
0270         val = 1;
0271         break;
0272 
0273     default:
0274         return -EINVAL;
0275     }
0276 
0277     stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
0278 
0279     return 0;
0280 }
0281 
0282 static int stv0297_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
0283 {
0284     struct stv0297_state *state = fe->demodulator_priv;
0285 
0286     if (enable) {
0287         stv0297_writereg(state, 0x87, 0x78);
0288         stv0297_writereg(state, 0x86, 0xc8);
0289     }
0290 
0291     return 0;
0292 }
0293 
0294 static int stv0297_init(struct dvb_frontend *fe)
0295 {
0296     struct stv0297_state *state = fe->demodulator_priv;
0297     int i;
0298 
0299     /* load init table */
0300     for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)
0301         stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]);
0302     msleep(200);
0303 
0304     state->last_ber = 0;
0305 
0306     return 0;
0307 }
0308 
0309 static int stv0297_sleep(struct dvb_frontend *fe)
0310 {
0311     struct stv0297_state *state = fe->demodulator_priv;
0312 
0313     stv0297_writereg_mask(state, 0x80, 1, 1);
0314 
0315     return 0;
0316 }
0317 
0318 static int stv0297_read_status(struct dvb_frontend *fe,
0319                    enum fe_status *status)
0320 {
0321     struct stv0297_state *state = fe->demodulator_priv;
0322 
0323     u8 sync = stv0297_readreg(state, 0xDF);
0324 
0325     *status = 0;
0326     if (sync & 0x80)
0327         *status |=
0328             FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
0329     return 0;
0330 }
0331 
0332 static int stv0297_read_ber(struct dvb_frontend *fe, u32 * ber)
0333 {
0334     struct stv0297_state *state = fe->demodulator_priv;
0335     u8 BER[3];
0336 
0337     stv0297_readregs(state, 0xA0, BER, 3);
0338     if (!(BER[0] & 0x80)) {
0339         state->last_ber = BER[2] << 8 | BER[1];
0340         stv0297_writereg_mask(state, 0xA0, 0x80, 0x80);
0341     }
0342 
0343     *ber = state->last_ber;
0344 
0345     return 0;
0346 }
0347 
0348 
0349 static int stv0297_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
0350 {
0351     struct stv0297_state *state = fe->demodulator_priv;
0352     u8 STRENGTH[3];
0353     u16 tmp;
0354 
0355     stv0297_readregs(state, 0x41, STRENGTH, 3);
0356     tmp = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];
0357     if (STRENGTH[2] & 0x20) {
0358         if (tmp < 0x200)
0359             tmp = 0;
0360         else
0361             tmp = tmp - 0x200;
0362     } else {
0363         if (tmp > 0x1ff)
0364             tmp = 0;
0365         else
0366             tmp = 0x1ff - tmp;
0367     }
0368     *strength = (tmp << 7) | (tmp >> 2);
0369     return 0;
0370 }
0371 
0372 static int stv0297_read_snr(struct dvb_frontend *fe, u16 * snr)
0373 {
0374     struct stv0297_state *state = fe->demodulator_priv;
0375     u8 SNR[2];
0376 
0377     stv0297_readregs(state, 0x07, SNR, 2);
0378     *snr = SNR[1] << 8 | SNR[0];
0379 
0380     return 0;
0381 }
0382 
0383 static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
0384 {
0385     struct stv0297_state *state = fe->demodulator_priv;
0386 
0387     stv0297_writereg_mask(state, 0xDF, 0x03, 0x03); /* freeze the counters */
0388 
0389     *ucblocks = (stv0297_readreg(state, 0xD5) << 8)
0390         | stv0297_readreg(state, 0xD4);
0391 
0392     stv0297_writereg_mask(state, 0xDF, 0x03, 0x02); /* clear the counters */
0393     stv0297_writereg_mask(state, 0xDF, 0x03, 0x01); /* re-enable the counters */
0394 
0395     return 0;
0396 }
0397 
0398 static int stv0297_set_frontend(struct dvb_frontend *fe)
0399 {
0400     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0401     struct stv0297_state *state = fe->demodulator_priv;
0402     int u_threshold;
0403     int initial_u;
0404     int blind_u;
0405     int delay;
0406     int sweeprate;
0407     int carrieroffset;
0408     unsigned long timeout;
0409     enum fe_spectral_inversion inversion;
0410 
0411     switch (p->modulation) {
0412     case QAM_16:
0413     case QAM_32:
0414     case QAM_64:
0415         delay = 100;
0416         sweeprate = 1000;
0417         break;
0418 
0419     case QAM_128:
0420     case QAM_256:
0421         delay = 200;
0422         sweeprate = 500;
0423         break;
0424 
0425     default:
0426         return -EINVAL;
0427     }
0428 
0429     // determine inversion dependent parameters
0430     inversion = p->inversion;
0431     if (state->config->invert)
0432         inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
0433     carrieroffset = -330;
0434     switch (inversion) {
0435     case INVERSION_OFF:
0436         break;
0437 
0438     case INVERSION_ON:
0439         sweeprate = -sweeprate;
0440         carrieroffset = -carrieroffset;
0441         break;
0442 
0443     default:
0444         return -EINVAL;
0445     }
0446 
0447     stv0297_init(fe);
0448     if (fe->ops.tuner_ops.set_params) {
0449         fe->ops.tuner_ops.set_params(fe);
0450         if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
0451     }
0452 
0453     /* clear software interrupts */
0454     stv0297_writereg(state, 0x82, 0x0);
0455 
0456     /* set initial demodulation frequency */
0457     stv0297_set_initialdemodfreq(state, 7250);
0458 
0459     /* setup AGC */
0460     stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
0461     stv0297_writereg(state, 0x41, 0x00);
0462     stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
0463     stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
0464     stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
0465     stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
0466     stv0297_writereg(state, 0x72, 0x00);
0467     stv0297_writereg(state, 0x73, 0x00);
0468     stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
0469     stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
0470     stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
0471 
0472     /* setup STL */
0473     stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
0474     stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
0475     stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
0476     stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
0477     stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
0478 
0479     /* disable frequency sweep */
0480     stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
0481 
0482     /* reset deinterleaver */
0483     stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
0484     stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
0485 
0486     /* ??? */
0487     stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
0488     stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
0489 
0490     /* reset equaliser */
0491     u_threshold = stv0297_readreg(state, 0x00) & 0xf;
0492     initial_u = stv0297_readreg(state, 0x01) >> 4;
0493     blind_u = stv0297_readreg(state, 0x01) & 0xf;
0494     stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
0495     stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
0496     stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
0497     stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
0498     stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
0499 
0500     /* data comes from internal A/D */
0501     stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
0502 
0503     /* clear phase registers */
0504     stv0297_writereg(state, 0x63, 0x00);
0505     stv0297_writereg(state, 0x64, 0x00);
0506     stv0297_writereg(state, 0x65, 0x00);
0507     stv0297_writereg(state, 0x66, 0x00);
0508     stv0297_writereg(state, 0x67, 0x00);
0509     stv0297_writereg(state, 0x68, 0x00);
0510     stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
0511 
0512     /* set parameters */
0513     stv0297_set_qam(state, p->modulation);
0514     stv0297_set_symbolrate(state, p->symbol_rate / 1000);
0515     stv0297_set_sweeprate(state, sweeprate, p->symbol_rate / 1000);
0516     stv0297_set_carrieroffset(state, carrieroffset);
0517     stv0297_set_inversion(state, inversion);
0518 
0519     /* kick off lock */
0520     /* Disable corner detection for higher QAMs */
0521     if (p->modulation == QAM_128 ||
0522         p->modulation == QAM_256)
0523         stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
0524     else
0525         stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
0526 
0527     stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
0528     stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
0529     stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
0530     stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
0531     stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
0532     stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
0533     stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
0534 
0535     /* wait for WGAGC lock */
0536     timeout = jiffies + msecs_to_jiffies(2000);
0537     while (time_before(jiffies, timeout)) {
0538         msleep(10);
0539         if (stv0297_readreg(state, 0x43) & 0x08)
0540             break;
0541     }
0542     if (time_after(jiffies, timeout)) {
0543         goto timeout;
0544     }
0545     msleep(20);
0546 
0547     /* wait for equaliser partial convergence */
0548     timeout = jiffies + msecs_to_jiffies(500);
0549     while (time_before(jiffies, timeout)) {
0550         msleep(10);
0551 
0552         if (stv0297_readreg(state, 0x82) & 0x04) {
0553             break;
0554         }
0555     }
0556     if (time_after(jiffies, timeout)) {
0557         goto timeout;
0558     }
0559 
0560     /* wait for equaliser full convergence */
0561     timeout = jiffies + msecs_to_jiffies(delay);
0562     while (time_before(jiffies, timeout)) {
0563         msleep(10);
0564 
0565         if (stv0297_readreg(state, 0x82) & 0x08) {
0566             break;
0567         }
0568     }
0569     if (time_after(jiffies, timeout)) {
0570         goto timeout;
0571     }
0572 
0573     /* disable sweep */
0574     stv0297_writereg_mask(state, 0x6a, 1, 0);
0575     stv0297_writereg_mask(state, 0x88, 8, 0);
0576 
0577     /* wait for main lock */
0578     timeout = jiffies + msecs_to_jiffies(20);
0579     while (time_before(jiffies, timeout)) {
0580         msleep(10);
0581 
0582         if (stv0297_readreg(state, 0xDF) & 0x80) {
0583             break;
0584         }
0585     }
0586     if (time_after(jiffies, timeout)) {
0587         goto timeout;
0588     }
0589     msleep(100);
0590 
0591     /* is it still locked after that delay? */
0592     if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
0593         goto timeout;
0594     }
0595 
0596     /* success!! */
0597     stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
0598     state->base_freq = p->frequency;
0599     return 0;
0600 
0601 timeout:
0602     stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
0603     return 0;
0604 }
0605 
0606 static int stv0297_get_frontend(struct dvb_frontend *fe,
0607                 struct dtv_frontend_properties *p)
0608 {
0609     struct stv0297_state *state = fe->demodulator_priv;
0610     int reg_00, reg_83;
0611 
0612     reg_00 = stv0297_readreg(state, 0x00);
0613     reg_83 = stv0297_readreg(state, 0x83);
0614 
0615     p->frequency = state->base_freq;
0616     p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
0617     if (state->config->invert)
0618         p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
0619     p->symbol_rate = stv0297_get_symbolrate(state) * 1000;
0620     p->fec_inner = FEC_NONE;
0621 
0622     switch ((reg_00 >> 4) & 0x7) {
0623     case 0:
0624         p->modulation = QAM_16;
0625         break;
0626     case 1:
0627         p->modulation = QAM_32;
0628         break;
0629     case 2:
0630         p->modulation = QAM_128;
0631         break;
0632     case 3:
0633         p->modulation = QAM_256;
0634         break;
0635     case 4:
0636         p->modulation = QAM_64;
0637         break;
0638     }
0639 
0640     return 0;
0641 }
0642 
0643 static void stv0297_release(struct dvb_frontend *fe)
0644 {
0645     struct stv0297_state *state = fe->demodulator_priv;
0646     kfree(state);
0647 }
0648 
0649 static const struct dvb_frontend_ops stv0297_ops;
0650 
0651 struct dvb_frontend *stv0297_attach(const struct stv0297_config *config,
0652                     struct i2c_adapter *i2c)
0653 {
0654     struct stv0297_state *state = NULL;
0655 
0656     /* allocate memory for the internal state */
0657     state = kzalloc(sizeof(struct stv0297_state), GFP_KERNEL);
0658     if (state == NULL)
0659         goto error;
0660 
0661     /* setup the state */
0662     state->config = config;
0663     state->i2c = i2c;
0664     state->last_ber = 0;
0665     state->base_freq = 0;
0666 
0667     /* check if the demod is there */
0668     if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
0669         goto error;
0670 
0671     /* create dvb_frontend */
0672     memcpy(&state->frontend.ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
0673     state->frontend.demodulator_priv = state;
0674     return &state->frontend;
0675 
0676 error:
0677     kfree(state);
0678     return NULL;
0679 }
0680 
0681 static const struct dvb_frontend_ops stv0297_ops = {
0682     .delsys = { SYS_DVBC_ANNEX_A },
0683     .info = {
0684          .name = "ST STV0297 DVB-C",
0685          .frequency_min_hz = 47 * MHz,
0686          .frequency_max_hz = 862 * MHz,
0687          .frequency_stepsize_hz = 62500,
0688          .symbol_rate_min = 870000,
0689          .symbol_rate_max = 11700000,
0690          .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
0691          FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
0692 
0693     .release = stv0297_release,
0694 
0695     .init = stv0297_init,
0696     .sleep = stv0297_sleep,
0697     .i2c_gate_ctrl = stv0297_i2c_gate_ctrl,
0698 
0699     .set_frontend = stv0297_set_frontend,
0700     .get_frontend = stv0297_get_frontend,
0701 
0702     .read_status = stv0297_read_status,
0703     .read_ber = stv0297_read_ber,
0704     .read_signal_strength = stv0297_read_signal_strength,
0705     .read_snr = stv0297_read_snr,
0706     .read_ucblocks = stv0297_read_ucblocks,
0707 };
0708 
0709 MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
0710 MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
0711 MODULE_LICENSE("GPL");
0712 
0713 EXPORT_SYMBOL(stv0297_attach);
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