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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003     STB0899 Multistandard Frontend driver
0004     Copyright (C) Manu Abraham (abraham.manu@gmail.com)
0005 
0006     Copyright (C) ST Microelectronics
0007 
0008 */
0009 
0010 #ifndef __STB0899_CFG_H
0011 #define __STB0899_CFG_H
0012 
0013 static const struct stb0899_s2_reg  stb0899_s2_init_2[] = {
0014 
0015     { STB0899_OFF0_DMD_STATUS   , STB0899_BASE_DMD_STATUS   , 0x00000103 }, /* DMDSTATUS    */
0016     { STB0899_OFF0_CRL_FREQ     , STB0899_BASE_CRL_FREQ     , 0x3ed1da56 }, /* CRLFREQ  */
0017     { STB0899_OFF0_BTR_FREQ     , STB0899_BASE_BTR_FREQ     , 0x00004000 }, /* BTRFREQ  */
0018     { STB0899_OFF0_IF_AGC_GAIN  , STB0899_BASE_IF_AGC_GAIN  , 0x00002ade }, /* IFAGCGAIN    */
0019     { STB0899_OFF0_BB_AGC_GAIN  , STB0899_BASE_BB_AGC_GAIN  , 0x000001bc }, /* BBAGCGAIN    */
0020     { STB0899_OFF0_DC_OFFSET    , STB0899_BASE_DC_OFFSET    , 0x00000200 }, /* DCOFFSET */
0021     { STB0899_OFF0_DMD_CNTRL    , STB0899_BASE_DMD_CNTRL    , 0x0000000f }, /* DMDCNTRL */
0022 
0023     { STB0899_OFF0_IF_AGC_CNTRL , STB0899_BASE_IF_AGC_CNTRL , 0x03fb4a20 }, /* IFAGCCNTRL   */
0024     { STB0899_OFF0_BB_AGC_CNTRL , STB0899_BASE_BB_AGC_CNTRL , 0x00200c97 }, /* BBAGCCNTRL   */
0025 
0026     { STB0899_OFF0_CRL_CNTRL    , STB0899_BASE_CRL_CNTRL    , 0x00000016 }, /* CRLCNTRL */
0027     { STB0899_OFF0_CRL_PHS_INIT , STB0899_BASE_CRL_PHS_INIT , 0x00000000 }, /* CRLPHSINIT   */
0028     { STB0899_OFF0_CRL_FREQ_INIT    , STB0899_BASE_CRL_FREQ_INIT    , 0x00000000 }, /* CRLFREQINIT  */
0029     { STB0899_OFF0_CRL_LOOP_GAIN    , STB0899_BASE_CRL_LOOP_GAIN    , 0x00000000 }, /* CRLLOOPGAIN  */
0030     { STB0899_OFF0_CRL_NOM_FREQ , STB0899_BASE_CRL_NOM_FREQ , 0x3ed097b6 }, /* CRLNOMFREQ   */
0031     { STB0899_OFF0_CRL_SWP_RATE , STB0899_BASE_CRL_SWP_RATE , 0x00000000 }, /* CRLSWPRATE   */
0032     { STB0899_OFF0_CRL_MAX_SWP  , STB0899_BASE_CRL_MAX_SWP  , 0x00000000 }, /* CRLMAXSWP    */
0033     { STB0899_OFF0_CRL_LK_CNTRL , STB0899_BASE_CRL_LK_CNTRL , 0x0f6cdc01 }, /* CRLLKCNTRL   */
0034     { STB0899_OFF0_DECIM_CNTRL  , STB0899_BASE_DECIM_CNTRL  , 0x00000000 }, /* DECIMCNTRL   */
0035     { STB0899_OFF0_BTR_CNTRL    , STB0899_BASE_BTR_CNTRL    , 0x00003993 }, /* BTRCNTRL */
0036     { STB0899_OFF0_BTR_LOOP_GAIN    , STB0899_BASE_BTR_LOOP_GAIN    , 0x000d3c6f }, /* BTRLOOPGAIN  */
0037     { STB0899_OFF0_BTR_PHS_INIT , STB0899_BASE_BTR_PHS_INIT , 0x00000000 }, /* BTRPHSINIT   */
0038     { STB0899_OFF0_BTR_FREQ_INIT    , STB0899_BASE_BTR_FREQ_INIT    , 0x00000000 }, /* BTRFREQINIT  */
0039     { STB0899_OFF0_BTR_NOM_FREQ , STB0899_BASE_BTR_NOM_FREQ , 0x0238e38e }, /* BTRNOMFREQ   */
0040     { STB0899_OFF0_BTR_LK_CNTRL , STB0899_BASE_BTR_LK_CNTRL , 0x00000000 }, /* BTRLKCNTRL   */
0041     { STB0899_OFF0_DECN_CNTRL   , STB0899_BASE_DECN_CNTRL   , 0x00000000 }, /* DECNCNTRL    */
0042     { STB0899_OFF0_TP_CNTRL     , STB0899_BASE_TP_CNTRL     , 0x00000000 }, /* TPCNTRL  */
0043     { STB0899_OFF0_TP_BUF_STATUS    , STB0899_BASE_TP_BUF_STATUS    , 0x00000000 }, /* TPBUFSTATUS  */
0044     { STB0899_OFF0_DC_ESTIM     , STB0899_BASE_DC_ESTIM     , 0x00000000 }, /* DCESTIM  */
0045     { STB0899_OFF0_FLL_CNTRL    , STB0899_BASE_FLL_CNTRL    , 0x00000000 }, /* FLLCNTRL */
0046     { STB0899_OFF0_FLL_FREQ_WD  , STB0899_BASE_FLL_FREQ_WD  , 0x40070000 }, /* FLLFREQWD    */
0047     { STB0899_OFF0_ANTI_ALIAS_SEL   , STB0899_BASE_ANTI_ALIAS_SEL   , 0x00000001 }, /* ANTIALIASSEL */
0048     { STB0899_OFF0_RRC_ALPHA    , STB0899_BASE_RRC_ALPHA    , 0x00000002 }, /* RRCALPHA */
0049     { STB0899_OFF0_DC_ADAPT_LSHFT   , STB0899_BASE_DC_ADAPT_LSHFT   , 0x00000000 }, /* DCADAPTISHFT */
0050     { STB0899_OFF0_IMB_OFFSET   , STB0899_BASE_IMB_OFFSET   , 0x0000fe01 }, /* IMBOFFSET    */
0051     { STB0899_OFF0_IMB_ESTIMATE , STB0899_BASE_IMB_ESTIMATE , 0x00000000 }, /* IMBESTIMATE  */
0052     { STB0899_OFF0_IMB_CNTRL    , STB0899_BASE_IMB_CNTRL    , 0x00000001 }, /* IMBCNTRL */
0053     { STB0899_OFF0_IF_AGC_CNTRL2    , STB0899_BASE_IF_AGC_CNTRL2    , 0x00005007 }, /* IFAGCCNTRL2  */
0054     { STB0899_OFF0_DMD_CNTRL2   , STB0899_BASE_DMD_CNTRL2   , 0x00000002 }, /* DMDCNTRL2    */
0055     { STB0899_OFF0_TP_BUFFER    , STB0899_BASE_TP_BUFFER    , 0x00000000 }, /* TPBUFFER */
0056     { STB0899_OFF0_TP_BUFFER1   , STB0899_BASE_TP_BUFFER1   , 0x00000000 }, /* TPBUFFER1    */
0057     { STB0899_OFF0_TP_BUFFER2   , STB0899_BASE_TP_BUFFER2   , 0x00000000 }, /* TPBUFFER2    */
0058     { STB0899_OFF0_TP_BUFFER3   , STB0899_BASE_TP_BUFFER3   , 0x00000000 }, /* TPBUFFER3    */
0059     { STB0899_OFF0_TP_BUFFER4   , STB0899_BASE_TP_BUFFER4   , 0x00000000 }, /* TPBUFFER4    */
0060     { STB0899_OFF0_TP_BUFFER5   , STB0899_BASE_TP_BUFFER5   , 0x00000000 }, /* TPBUFFER5    */
0061     { STB0899_OFF0_TP_BUFFER6   , STB0899_BASE_TP_BUFFER6   , 0x00000000 }, /* TPBUFFER6    */
0062     { STB0899_OFF0_TP_BUFFER7   , STB0899_BASE_TP_BUFFER7   , 0x00000000 }, /* TPBUFFER7    */
0063     { STB0899_OFF0_TP_BUFFER8   , STB0899_BASE_TP_BUFFER8   , 0x00000000 }, /* TPBUFFER8    */
0064     { STB0899_OFF0_TP_BUFFER9   , STB0899_BASE_TP_BUFFER9   , 0x00000000 }, /* TPBUFFER9    */
0065     { STB0899_OFF0_TP_BUFFER10  , STB0899_BASE_TP_BUFFER10  , 0x00000000 }, /* TPBUFFER10   */
0066     { STB0899_OFF0_TP_BUFFER11  , STB0899_BASE_TP_BUFFER11  , 0x00000000 }, /* TPBUFFER11   */
0067     { STB0899_OFF0_TP_BUFFER12  , STB0899_BASE_TP_BUFFER12  , 0x00000000 }, /* TPBUFFER12   */
0068     { STB0899_OFF0_TP_BUFFER13  , STB0899_BASE_TP_BUFFER13  , 0x00000000 }, /* TPBUFFER13   */
0069     { STB0899_OFF0_TP_BUFFER14  , STB0899_BASE_TP_BUFFER14  , 0x00000000 }, /* TPBUFFER14   */
0070     { STB0899_OFF0_TP_BUFFER15  , STB0899_BASE_TP_BUFFER15  , 0x00000000 }, /* TPBUFFER15   */
0071     { STB0899_OFF0_TP_BUFFER16  , STB0899_BASE_TP_BUFFER16  , 0x0000ff00 }, /* TPBUFFER16   */
0072     { STB0899_OFF0_TP_BUFFER17  , STB0899_BASE_TP_BUFFER17  , 0x00000100 }, /* TPBUFFER17   */
0073     { STB0899_OFF0_TP_BUFFER18  , STB0899_BASE_TP_BUFFER18  , 0x0000fe01 }, /* TPBUFFER18   */
0074     { STB0899_OFF0_TP_BUFFER19  , STB0899_BASE_TP_BUFFER19  , 0x000004fe }, /* TPBUFFER19   */
0075     { STB0899_OFF0_TP_BUFFER20  , STB0899_BASE_TP_BUFFER20  , 0x0000cfe7 }, /* TPBUFFER20   */
0076     { STB0899_OFF0_TP_BUFFER21  , STB0899_BASE_TP_BUFFER21  , 0x0000bec6 }, /* TPBUFFER21   */
0077     { STB0899_OFF0_TP_BUFFER22  , STB0899_BASE_TP_BUFFER22  , 0x0000c2bf }, /* TPBUFFER22   */
0078     { STB0899_OFF0_TP_BUFFER23  , STB0899_BASE_TP_BUFFER23  , 0x0000c1c1 }, /* TPBUFFER23   */
0079     { STB0899_OFF0_TP_BUFFER24  , STB0899_BASE_TP_BUFFER24  , 0x0000c1c1 }, /* TPBUFFER24   */
0080     { STB0899_OFF0_TP_BUFFER25  , STB0899_BASE_TP_BUFFER25  , 0x0000c1c1 }, /* TPBUFFER25   */
0081     { STB0899_OFF0_TP_BUFFER26  , STB0899_BASE_TP_BUFFER26  , 0x0000c1c1 }, /* TPBUFFER26   */
0082     { STB0899_OFF0_TP_BUFFER27  , STB0899_BASE_TP_BUFFER27  , 0x0000c1c0 }, /* TPBUFFER27   */
0083     { STB0899_OFF0_TP_BUFFER28  , STB0899_BASE_TP_BUFFER28  , 0x0000c0c0 }, /* TPBUFFER28   */
0084     { STB0899_OFF0_TP_BUFFER29  , STB0899_BASE_TP_BUFFER29  , 0x0000c1c1 }, /* TPBUFFER29   */
0085     { STB0899_OFF0_TP_BUFFER30  , STB0899_BASE_TP_BUFFER30  , 0x0000c1c1 }, /* TPBUFFER30   */
0086     { STB0899_OFF0_TP_BUFFER31  , STB0899_BASE_TP_BUFFER31  , 0x0000c0c1 }, /* TPBUFFER31   */
0087     { STB0899_OFF0_TP_BUFFER32  , STB0899_BASE_TP_BUFFER32  , 0x0000c0c1 }, /* TPBUFFER32   */
0088     { STB0899_OFF0_TP_BUFFER33  , STB0899_BASE_TP_BUFFER33  , 0x0000c1c1 }, /* TPBUFFER33   */
0089     { STB0899_OFF0_TP_BUFFER34  , STB0899_BASE_TP_BUFFER34  , 0x0000c1c1 }, /* TPBUFFER34   */
0090     { STB0899_OFF0_TP_BUFFER35  , STB0899_BASE_TP_BUFFER35  , 0x0000c0c1 }, /* TPBUFFER35   */
0091     { STB0899_OFF0_TP_BUFFER36  , STB0899_BASE_TP_BUFFER36  , 0x0000c1c1 }, /* TPBUFFER36   */
0092     { STB0899_OFF0_TP_BUFFER37  , STB0899_BASE_TP_BUFFER37  , 0x0000c0c1 }, /* TPBUFFER37   */
0093     { STB0899_OFF0_TP_BUFFER38  , STB0899_BASE_TP_BUFFER38  , 0x0000c1c1 }, /* TPBUFFER38   */
0094     { STB0899_OFF0_TP_BUFFER39  , STB0899_BASE_TP_BUFFER39  , 0x0000c0c0 }, /* TPBUFFER39   */
0095     { STB0899_OFF0_TP_BUFFER40  , STB0899_BASE_TP_BUFFER40  , 0x0000c1c0 }, /* TPBUFFER40   */
0096     { STB0899_OFF0_TP_BUFFER41  , STB0899_BASE_TP_BUFFER41  , 0x0000c1c1 }, /* TPBUFFER41   */
0097     { STB0899_OFF0_TP_BUFFER42  , STB0899_BASE_TP_BUFFER42  , 0x0000c0c0 }, /* TPBUFFER42   */
0098     { STB0899_OFF0_TP_BUFFER43  , STB0899_BASE_TP_BUFFER43  , 0x0000c1c0 }, /* TPBUFFER43   */
0099     { STB0899_OFF0_TP_BUFFER44  , STB0899_BASE_TP_BUFFER44  , 0x0000c0c1 }, /* TPBUFFER44   */
0100     { STB0899_OFF0_TP_BUFFER45  , STB0899_BASE_TP_BUFFER45  , 0x0000c1be }, /* TPBUFFER45   */
0101     { STB0899_OFF0_TP_BUFFER46  , STB0899_BASE_TP_BUFFER46  , 0x0000c1c9 }, /* TPBUFFER46   */
0102     { STB0899_OFF0_TP_BUFFER47  , STB0899_BASE_TP_BUFFER47  , 0x0000c0da }, /* TPBUFFER47   */
0103     { STB0899_OFF0_TP_BUFFER48  , STB0899_BASE_TP_BUFFER48  , 0x0000c0ba }, /* TPBUFFER48   */
0104     { STB0899_OFF0_TP_BUFFER49  , STB0899_BASE_TP_BUFFER49  , 0x0000c1c4 }, /* TPBUFFER49   */
0105     { STB0899_OFF0_TP_BUFFER50  , STB0899_BASE_TP_BUFFER50  , 0x0000c1bf }, /* TPBUFFER50   */
0106     { STB0899_OFF0_TP_BUFFER51  , STB0899_BASE_TP_BUFFER51  , 0x0000c0c1 }, /* TPBUFFER51   */
0107     { STB0899_OFF0_TP_BUFFER52  , STB0899_BASE_TP_BUFFER52  , 0x0000c1c0 }, /* TPBUFFER52   */
0108     { STB0899_OFF0_TP_BUFFER53  , STB0899_BASE_TP_BUFFER53  , 0x0000c0c1 }, /* TPBUFFER53   */
0109     { STB0899_OFF0_TP_BUFFER54  , STB0899_BASE_TP_BUFFER54  , 0x0000c1c1 }, /* TPBUFFER54   */
0110     { STB0899_OFF0_TP_BUFFER55  , STB0899_BASE_TP_BUFFER55  , 0x0000c1c1 }, /* TPBUFFER55   */
0111     { STB0899_OFF0_TP_BUFFER56  , STB0899_BASE_TP_BUFFER56  , 0x0000c1c1 }, /* TPBUFFER56   */
0112     { STB0899_OFF0_TP_BUFFER57  , STB0899_BASE_TP_BUFFER57  , 0x0000c1c1 }, /* TPBUFFER57   */
0113     { STB0899_OFF0_TP_BUFFER58  , STB0899_BASE_TP_BUFFER58  , 0x0000c1c1 }, /* TPBUFFER58   */
0114     { STB0899_OFF0_TP_BUFFER59  , STB0899_BASE_TP_BUFFER59  , 0x0000c1c1 }, /* TPBUFFER59   */
0115     { STB0899_OFF0_TP_BUFFER60  , STB0899_BASE_TP_BUFFER60  , 0x0000c1c1 }, /* TPBUFFER60   */
0116     { STB0899_OFF0_TP_BUFFER61  , STB0899_BASE_TP_BUFFER61  , 0x0000c1c1 }, /* TPBUFFER61   */
0117     { STB0899_OFF0_TP_BUFFER62  , STB0899_BASE_TP_BUFFER62  , 0x0000c1c1 }, /* TPBUFFER62   */
0118     { STB0899_OFF0_TP_BUFFER63  , STB0899_BASE_TP_BUFFER63  , 0x0000c1c0 }, /* TPBUFFER63   */
0119     { STB0899_OFF0_RESET_CNTRL  , STB0899_BASE_RESET_CNTRL  , 0x00000001 }, /* RESETCNTRL   */
0120     { STB0899_OFF0_ACM_ENABLE   , STB0899_BASE_ACM_ENABLE   , 0x00005654 }, /* ACMENABLE    */
0121     { STB0899_OFF0_DESCR_CNTRL  , STB0899_BASE_DESCR_CNTRL  , 0x00000000 }, /* DESCRCNTRL   */
0122     { STB0899_OFF0_CSM_CNTRL1   , STB0899_BASE_CSM_CNTRL1   , 0x00020019 }, /* CSMCNTRL1    */
0123     { STB0899_OFF0_CSM_CNTRL2   , STB0899_BASE_CSM_CNTRL2   , 0x004b3237 }, /* CSMCNTRL2    */
0124     { STB0899_OFF0_CSM_CNTRL3   , STB0899_BASE_CSM_CNTRL3   , 0x0003dd17 }, /* CSMCNTRL3    */
0125     { STB0899_OFF0_CSM_CNTRL4   , STB0899_BASE_CSM_CNTRL4   , 0x00008008 }, /* CSMCNTRL4    */
0126     { STB0899_OFF0_UWP_CNTRL1   , STB0899_BASE_UWP_CNTRL1   , 0x002a3106 }, /* UWPCNTRL1    */
0127     { STB0899_OFF0_UWP_CNTRL2   , STB0899_BASE_UWP_CNTRL2   , 0x0006140a }, /* UWPCNTRL2    */
0128     { STB0899_OFF0_UWP_STAT1    , STB0899_BASE_UWP_STAT1    , 0x00008000 }, /* UWPSTAT1 */
0129     { STB0899_OFF0_UWP_STAT2    , STB0899_BASE_UWP_STAT2    , 0x00000000 }, /* UWPSTAT2 */
0130     { STB0899_OFF0_DMD_STAT2    , STB0899_BASE_DMD_STAT2    , 0x00000000 }, /* DMDSTAT2 */
0131     { STB0899_OFF0_FREQ_ADJ_SCALE   , STB0899_BASE_FREQ_ADJ_SCALE   , 0x00000471 }, /* FREQADJSCALE */
0132     { STB0899_OFF0_UWP_CNTRL3   , STB0899_BASE_UWP_CNTRL3   , 0x017b0465 }, /* UWPCNTRL3    */
0133     { STB0899_OFF0_SYM_CLK_SEL  , STB0899_BASE_SYM_CLK_SEL  , 0x00000002 }, /* SYMCLKSEL    */
0134     { STB0899_OFF0_SOF_SRCH_TO  , STB0899_BASE_SOF_SRCH_TO  , 0x00196464 }, /* SOFSRCHTO    */
0135     { STB0899_OFF0_ACQ_CNTRL1   , STB0899_BASE_ACQ_CNTRL1   , 0x00000603 }, /* ACQCNTRL1    */
0136     { STB0899_OFF0_ACQ_CNTRL2   , STB0899_BASE_ACQ_CNTRL2   , 0x02046666 }, /* ACQCNTRL2    */
0137     { STB0899_OFF0_ACQ_CNTRL3   , STB0899_BASE_ACQ_CNTRL3   , 0x10046583 }, /* ACQCNTRL3    */
0138     { STB0899_OFF0_FE_SETTLE    , STB0899_BASE_FE_SETTLE    , 0x00010404 }, /* FESETTLE */
0139     { STB0899_OFF0_AC_DWELL     , STB0899_BASE_AC_DWELL     , 0x0002aa8a }, /* ACDWELL  */
0140     { STB0899_OFF0_ACQUIRE_TRIG , STB0899_BASE_ACQUIRE_TRIG , 0x00000000 }, /* ACQUIRETRIG  */
0141     { STB0899_OFF0_LOCK_LOST    , STB0899_BASE_LOCK_LOST    , 0x00000001 }, /* LOCKLOST */
0142     { STB0899_OFF0_ACQ_STAT1    , STB0899_BASE_ACQ_STAT1    , 0x00000500 }, /* ACQSTAT1 */
0143     { STB0899_OFF0_ACQ_TIMEOUT  , STB0899_BASE_ACQ_TIMEOUT  , 0x0028a0a0 }, /* ACQTIMEOUT   */
0144     { STB0899_OFF0_ACQ_TIME     , STB0899_BASE_ACQ_TIME     , 0x00000000 }, /* ACQTIME  */
0145     { STB0899_OFF0_FINAL_AGC_CNTRL  , STB0899_BASE_FINAL_AGC_CNTRL  , 0x00800c17 }, /* FINALAGCCNTRL*/
0146     { STB0899_OFF0_FINAL_AGC_GAIN   , STB0899_BASE_FINAL_AGC_GAIN   , 0x00000000 }, /* FINALAGCCGAIN*/
0147     { STB0899_OFF0_EQUALIZER_INIT   , STB0899_BASE_EQUALIZER_INIT   , 0x00000000 }, /* EQUILIZERINIT*/
0148     { STB0899_OFF0_EQ_CNTRL     , STB0899_BASE_EQ_CNTRL     , 0x00054802 }, /* EQCNTL   */
0149     { STB0899_OFF0_EQ_I_INIT_COEFF_0, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF0 */
0150     { STB0899_OFF1_EQ_I_INIT_COEFF_1, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF1 */
0151     { STB0899_OFF2_EQ_I_INIT_COEFF_2, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF2 */
0152     { STB0899_OFF3_EQ_I_INIT_COEFF_3, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF3 */
0153     { STB0899_OFF4_EQ_I_INIT_COEFF_4, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF4 */
0154     { STB0899_OFF5_EQ_I_INIT_COEFF_5, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000400 }, /* EQIINITCOEFF5 */
0155     { STB0899_OFF6_EQ_I_INIT_COEFF_6, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF6 */
0156     { STB0899_OFF7_EQ_I_INIT_COEFF_7, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF7 */
0157     { STB0899_OFF8_EQ_I_INIT_COEFF_8, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF8 */
0158     { STB0899_OFF9_EQ_I_INIT_COEFF_9, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF9 */
0159     { STB0899_OFFa_EQ_I_INIT_COEFF_10,STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF10*/
0160     { STB0899_OFF0_EQ_Q_INIT_COEFF_0, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF0 */
0161     { STB0899_OFF1_EQ_Q_INIT_COEFF_1, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF1 */
0162     { STB0899_OFF2_EQ_Q_INIT_COEFF_2, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF2 */
0163     { STB0899_OFF3_EQ_Q_INIT_COEFF_3, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF3 */
0164     { STB0899_OFF4_EQ_Q_INIT_COEFF_4, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF4 */
0165     { STB0899_OFF5_EQ_Q_INIT_COEFF_5, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF5 */
0166     { STB0899_OFF6_EQ_Q_INIT_COEFF_6, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF6 */
0167     { STB0899_OFF7_EQ_Q_INIT_COEFF_7, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF7 */
0168     { STB0899_OFF8_EQ_Q_INIT_COEFF_8, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF8 */
0169     { STB0899_OFF9_EQ_Q_INIT_COEFF_9, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF9 */
0170     { STB0899_OFFa_EQ_Q_INIT_COEFF_10,STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF10*/
0171     { STB0899_OFF0_EQ_I_OUT_COEFF_0 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT0 */
0172     { STB0899_OFF1_EQ_I_OUT_COEFF_1 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT1 */
0173     { STB0899_OFF2_EQ_I_OUT_COEFF_2 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT2 */
0174     { STB0899_OFF3_EQ_I_OUT_COEFF_3 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT3 */
0175     { STB0899_OFF4_EQ_I_OUT_COEFF_4 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT4 */
0176     { STB0899_OFF5_EQ_I_OUT_COEFF_5 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT5 */
0177     { STB0899_OFF6_EQ_I_OUT_COEFF_6 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT6 */
0178     { STB0899_OFF7_EQ_I_OUT_COEFF_7 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT7 */
0179     { STB0899_OFF8_EQ_I_OUT_COEFF_8 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT8 */
0180     { STB0899_OFF9_EQ_I_OUT_COEFF_9 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT9 */
0181     { STB0899_OFFa_EQ_I_OUT_COEFF_10,STB0899_BASE_EQ_I_OUT_COEFF_N  , 0x00000000 }, /* EQICOEFFSOUT10*/
0182     { STB0899_OFF0_EQ_Q_OUT_COEFF_0 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT0 */
0183     { STB0899_OFF1_EQ_Q_OUT_COEFF_1 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT1 */
0184     { STB0899_OFF2_EQ_Q_OUT_COEFF_2 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT2 */
0185     { STB0899_OFF3_EQ_Q_OUT_COEFF_3 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT3 */
0186     { STB0899_OFF4_EQ_Q_OUT_COEFF_4 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT4 */
0187     { STB0899_OFF5_EQ_Q_OUT_COEFF_5 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT5 */
0188     { STB0899_OFF6_EQ_Q_OUT_COEFF_6 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT6 */
0189     { STB0899_OFF7_EQ_Q_OUT_COEFF_7 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT7 */
0190     { STB0899_OFF8_EQ_Q_OUT_COEFF_8 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT8 */
0191     { STB0899_OFF9_EQ_Q_OUT_COEFF_9 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT9 */
0192     { STB0899_OFFa_EQ_Q_OUT_COEFF_10, STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT10*/
0193     { 0xffff            , 0xffffffff            , 0xffffffff },
0194 };
0195 static const struct stb0899_s2_reg stb0899_s2_init_4[] = {
0196     { STB0899_OFF0_BLOCK_LNGTH  , STB0899_BASE_BLOCK_LNGTH  , 0x00000008 }, /* BLOCKLNGTH   */
0197     { STB0899_OFF0_ROW_STR      , STB0899_BASE_ROW_STR      , 0x000000b4 }, /* ROWSTR   */
0198     { STB0899_OFF0_BN_END_ADDR  , STB0899_BASE_BN_END_ADDR  , 0x000004b5 }, /* BNANDADDR    */
0199     { STB0899_OFF0_CN_END_ADDR  , STB0899_BASE_CN_END_ADDR  , 0x00000b4b }, /* CNANDADDR    */
0200     { STB0899_OFF0_INFO_LENGTH  , STB0899_BASE_INFO_LENGTH  , 0x00000078 }, /* INFOLENGTH   */
0201     { STB0899_OFF0_BOT_ADDR     , STB0899_BASE_BOT_ADDR     , 0x000001e0 }, /* BOT_ADDR */
0202     { STB0899_OFF0_BCH_BLK_LN   , STB0899_BASE_BCH_BLK_LN   , 0x0000a8c0 }, /* BCHBLKLN */
0203     { STB0899_OFF0_BCH_T        , STB0899_BASE_BCH_T        , 0x0000000c }, /* BCHT     */
0204     { STB0899_OFF0_CNFG_MODE    , STB0899_BASE_CNFG_MODE    , 0x00000001 }, /* CNFGMODE */
0205     { STB0899_OFF0_LDPC_STAT    , STB0899_BASE_LDPC_STAT    , 0x0000000d }, /* LDPCSTAT */
0206     { STB0899_OFF0_ITER_SCALE   , STB0899_BASE_ITER_SCALE   , 0x00000040 }, /* ITERSCALE    */
0207     { STB0899_OFF0_INPUT_MODE   , STB0899_BASE_INPUT_MODE   , 0x00000000 }, /* INPUTMODE    */
0208     { STB0899_OFF0_LDPCDECRST   , STB0899_BASE_LDPCDECRST   , 0x00000000 }, /* LDPCDECRST   */
0209     { STB0899_OFF0_CLK_PER_BYTE_RW  , STB0899_BASE_CLK_PER_BYTE_RW  , 0x00000008 }, /* CLKPERBYTE   */
0210     { STB0899_OFF0_BCH_ERRORS   , STB0899_BASE_BCH_ERRORS   , 0x00000000 }, /* BCHERRORS    */
0211     { STB0899_OFF0_LDPC_ERRORS  , STB0899_BASE_LDPC_ERRORS  , 0x00000000 }, /* LDPCERRORS   */
0212     { STB0899_OFF0_BCH_MODE     , STB0899_BASE_BCH_MODE     , 0x00000000 }, /* BCHMODE  */
0213     { STB0899_OFF0_ERR_ACC_PER  , STB0899_BASE_ERR_ACC_PER  , 0x00000008 }, /* ERRACCPER    */
0214     { STB0899_OFF0_BCH_ERR_ACC  , STB0899_BASE_BCH_ERR_ACC  , 0x00000000 }, /* BCHERRACC    */
0215     { STB0899_OFF0_FEC_TP_SEL   , STB0899_BASE_FEC_TP_SEL   , 0x00000000 }, /* FECTPSEL */
0216     { 0xffff            , 0xffffffff            , 0xffffffff },
0217 };
0218 
0219 static const struct stb0899_s1_reg stb0899_s1_init_5[] = {
0220     { STB0899_TSTCK     , 0x00 },
0221     { STB0899_TSTRES    , 0x00 },
0222     { STB0899_TSTOUT    , 0x00 },
0223     { STB0899_TSTIN     , 0x00 },
0224     { STB0899_TSTSYS    , 0x00 },
0225     { STB0899_TSTCHIP   , 0x00 },
0226     { STB0899_TSTFREE   , 0x00 },
0227     { STB0899_TSTI2C    , 0x00 },
0228     { STB0899_BITSPEEDM , 0x00 },
0229     { STB0899_BITSPEEDL , 0x00 },
0230     { STB0899_TBUSBIT   , 0x00 },
0231     { STB0899_TSTDIS    , 0x00 },
0232     { STB0899_TSTDISRX  , 0x00 },
0233     { STB0899_TSTJETON  , 0x00 },
0234     { STB0899_TSTDCADJ  , 0x00 },
0235     { STB0899_TSTAGC1   , 0x00 },
0236     { STB0899_TSTAGC1N  , 0x00 },
0237     { STB0899_TSTPOLYPH , 0x00 },
0238     { STB0899_TSTR      , 0x00 },
0239     { STB0899_TSTAGC2   , 0x00 },
0240     { STB0899_TSTCTL1   , 0x00 },
0241     { STB0899_TSTCTL2   , 0x00 },
0242     { STB0899_TSTCTL3   , 0x00 },
0243     { STB0899_TSTDEMAP  , 0x00 },
0244     { STB0899_TSTDEMAP2 , 0x00 },
0245     { STB0899_TSTDEMMON , 0x00 },
0246     { STB0899_TSTRATE   , 0x00 },
0247     { STB0899_TSTSELOUT , 0x00 },
0248     { STB0899_TSYNC     , 0x00 },
0249     { STB0899_TSTERR    , 0x00 },
0250     { STB0899_TSTRAM1   , 0x00 },
0251     { STB0899_TSTVSELOUT    , 0x00 },
0252     { STB0899_TSTFORCEIN    , 0x00 },
0253     { STB0899_TSTRS1    , 0x00 },
0254     { STB0899_TSTRS2    , 0x00 },
0255     { STB0899_TSTRS3    , 0x00 },
0256     { STB0899_GHOSTREG  , 0x81 },
0257     { 0xffff        , 0xff },
0258 };
0259 
0260 #define STB0899_DVBS2_ESNO_AVE          3
0261 #define STB0899_DVBS2_ESNO_QUANT        32
0262 #define STB0899_DVBS2_AVFRAMES_COARSE       10
0263 #define STB0899_DVBS2_AVFRAMES_FINE     20
0264 #define STB0899_DVBS2_MISS_THRESHOLD        6
0265 #define STB0899_DVBS2_UWP_THRESHOLD_ACQ     1125
0266 #define STB0899_DVBS2_UWP_THRESHOLD_TRACK   758
0267 #define STB0899_DVBS2_UWP_THRESHOLD_SOF     1350
0268 #define STB0899_DVBS2_SOF_SEARCH_TIMEOUT    1664100
0269 
0270 #define STB0899_DVBS2_BTR_NCO_BITS      28
0271 #define STB0899_DVBS2_BTR_GAIN_SHIFT_OFFSET 15
0272 #define STB0899_DVBS2_CRL_NCO_BITS      30
0273 #define STB0899_DVBS2_LDPC_MAX_ITER     70
0274 
0275 #endif //__STB0899_CFG_H
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