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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003     STB0899 Multistandard Frontend driver
0004     Copyright (C) Manu Abraham (abraham.manu@gmail.com)
0005 
0006     Copyright (C) ST Microelectronics
0007 
0008 */
0009 
0010 #include <linux/bitops.h>
0011 #include "stb0899_drv.h"
0012 #include "stb0899_priv.h"
0013 #include "stb0899_reg.h"
0014 
0015 static inline u32 stb0899_do_div(u64 n, u32 d)
0016 {
0017     /* wrap do_div() for ease of use */
0018 
0019     do_div(n, d);
0020     return n;
0021 }
0022 
0023 #if 0
0024 /* These functions are currently unused */
0025 /*
0026  * stb0899_calc_srate
0027  * Compute symbol rate
0028  */
0029 static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
0030 {
0031     u64 tmp;
0032 
0033     /* srate = (SFR * master_clk) >> 20 */
0034 
0035     /* sfr is of size 20 bit, stored with an offset of 4 bit */
0036     tmp = (((u32)sfr[0]) << 16) | (((u32)sfr[1]) << 8) | sfr[2];
0037     tmp &= ~0xf;
0038     tmp *= master_clk;
0039     tmp >>= 24;
0040 
0041     return tmp;
0042 }
0043 
0044 /*
0045  * stb0899_get_srate
0046  * Get the current symbol rate
0047  */
0048 static u32 stb0899_get_srate(struct stb0899_state *state)
0049 {
0050     struct stb0899_internal *internal = &state->internal;
0051     u8 sfr[3];
0052 
0053     stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
0054 
0055     return stb0899_calc_srate(internal->master_clk, sfr);
0056 }
0057 #endif
0058 
0059 /*
0060  * stb0899_set_srate
0061  * Set symbol frequency
0062  * MasterClock: master clock frequency (hz)
0063  * SymbolRate: symbol rate (bauds)
0064  * return symbol frequency
0065  */
0066 static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
0067 {
0068     u32 tmp;
0069     u8 sfr[3];
0070 
0071     dprintk(state->verbose, FE_DEBUG, 1, "-->");
0072     /*
0073      * in order to have the maximum precision, the symbol rate entered into
0074      * the chip is computed as the closest value of the "true value".
0075      * In this purpose, the symbol rate value is rounded (1 is added on the bit
0076      * below the LSB )
0077      *
0078      * srate = (SFR * master_clk) >> 20
0079      *      <=>
0080      *   SFR = srate << 20 / master_clk
0081      *
0082      * rounded:
0083      *   SFR = (srate << 21 + master_clk) / (2 * master_clk)
0084      *
0085      * stored as 20 bit number with an offset of 4 bit:
0086      *   sfr = SFR << 4;
0087      */
0088 
0089     tmp = stb0899_do_div((((u64)srate) << 21) + master_clk, 2 * master_clk);
0090     tmp <<= 4;
0091 
0092     sfr[0] = tmp >> 16;
0093     sfr[1] = tmp >>  8;
0094     sfr[2] = tmp;
0095 
0096     stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
0097 
0098     return srate;
0099 }
0100 
0101 /*
0102  * stb0899_calc_derot_time
0103  * Compute the amount of time needed by the derotator to lock
0104  * SymbolRate: Symbol rate
0105  * return: derotator time constant (ms)
0106  */
0107 static long stb0899_calc_derot_time(long srate)
0108 {
0109     if (srate > 0)
0110         return (100000 / (srate / 1000));
0111     else
0112         return 0;
0113 }
0114 
0115 /*
0116  * stb0899_carr_width
0117  * Compute the width of the carrier
0118  * return: width of carrier (kHz or Mhz)
0119  */
0120 long stb0899_carr_width(struct stb0899_state *state)
0121 {
0122     struct stb0899_internal *internal = &state->internal;
0123 
0124     return (internal->srate + (internal->srate * internal->rolloff) / 100);
0125 }
0126 
0127 /*
0128  * stb0899_first_subrange
0129  * Compute the first subrange of the search
0130  */
0131 static void stb0899_first_subrange(struct stb0899_state *state)
0132 {
0133     struct stb0899_internal *internal   = &state->internal;
0134     struct stb0899_params *params       = &state->params;
0135     struct stb0899_config *config       =  state->config;
0136 
0137     int range = 0;
0138     u32 bandwidth = 0;
0139 
0140     if (config->tuner_get_bandwidth) {
0141         stb0899_i2c_gate_ctrl(&state->frontend, 1);
0142         config->tuner_get_bandwidth(&state->frontend, &bandwidth);
0143         stb0899_i2c_gate_ctrl(&state->frontend, 0);
0144         range = bandwidth - stb0899_carr_width(state) / 2;
0145     }
0146 
0147     if (range > 0)
0148         internal->sub_range = min(internal->srch_range, range);
0149     else
0150         internal->sub_range = 0;
0151 
0152     internal->freq = params->freq;
0153     internal->tuner_offst = 0L;
0154     internal->sub_dir = 1;
0155 }
0156 
0157 /*
0158  * stb0899_check_tmg
0159  * check for timing lock
0160  * internal.Ttiming: time to wait for loop lock
0161  */
0162 static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
0163 {
0164     struct stb0899_internal *internal = &state->internal;
0165     int lock;
0166     u8 reg;
0167     s8 timing;
0168 
0169     msleep(internal->t_derot);
0170 
0171     stb0899_write_reg(state, STB0899_RTF, 0xf2);
0172     reg = stb0899_read_reg(state, STB0899_TLIR);
0173     lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
0174     timing = stb0899_read_reg(state, STB0899_RTF);
0175 
0176     if (lock >= 42) {
0177         if ((lock > 48) && (abs(timing) >= 110)) {
0178             internal->status = ANALOGCARRIER;
0179             dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
0180         } else {
0181             internal->status = TIMINGOK;
0182             dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
0183         }
0184     } else {
0185         internal->status = NOTIMING;
0186         dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
0187     }
0188     return internal->status;
0189 }
0190 
0191 /*
0192  * stb0899_search_tmg
0193  * perform a fs/2 zig-zag to find timing
0194  */
0195 static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
0196 {
0197     struct stb0899_internal *internal = &state->internal;
0198     struct stb0899_params *params = &state->params;
0199 
0200     short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
0201     int index = 0;
0202     u8 cfr[2];
0203 
0204     internal->status = NOTIMING;
0205 
0206     /* timing loop computation & symbol rate optimisation   */
0207     derot_limit = (internal->sub_range / 2L) / internal->mclk;
0208     derot_step = (params->srate / 2L) / internal->mclk;
0209 
0210     while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
0211         index++;
0212         derot_freq += index * internal->direction * derot_step; /* next derot zig zag position  */
0213 
0214         if (abs(derot_freq) > derot_limit)
0215             next_loop--;
0216 
0217         if (next_loop) {
0218             STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
0219             STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
0220             stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency     */
0221         }
0222         internal->direction = -internal->direction; /* Change zigzag direction      */
0223     }
0224 
0225     if (internal->status == TIMINGOK) {
0226         stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency      */
0227         internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
0228         dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
0229     }
0230 
0231     return internal->status;
0232 }
0233 
0234 /*
0235  * stb0899_check_carrier
0236  * Check for carrier found
0237  */
0238 static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
0239 {
0240     struct stb0899_internal *internal = &state->internal;
0241     u8 reg;
0242 
0243     msleep(internal->t_derot); /* wait for derotator ok */
0244 
0245     reg = stb0899_read_reg(state, STB0899_CFD);
0246     STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
0247     stb0899_write_reg(state, STB0899_CFD, reg);
0248 
0249     reg = stb0899_read_reg(state, STB0899_DSTATUS);
0250     dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
0251     if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
0252         internal->status = CARRIEROK;
0253         dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
0254     } else {
0255         internal->status = NOCARRIER;
0256         dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
0257     }
0258 
0259     return internal->status;
0260 }
0261 
0262 /*
0263  * stb0899_search_carrier
0264  * Search for a QPSK carrier with the derotator
0265  */
0266 static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
0267 {
0268     struct stb0899_internal *internal = &state->internal;
0269 
0270     short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
0271     int index = 0;
0272     u8 cfr[2];
0273     u8 reg;
0274 
0275     internal->status = NOCARRIER;
0276     derot_limit = (internal->sub_range / 2L) / internal->mclk;
0277     derot_freq = internal->derot_freq;
0278 
0279     reg = stb0899_read_reg(state, STB0899_CFD);
0280     STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
0281     stb0899_write_reg(state, STB0899_CFD, reg);
0282 
0283     do {
0284         dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
0285         if (stb0899_check_carrier(state) == NOCARRIER) {
0286             index++;
0287             last_derot_freq = derot_freq;
0288             derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */
0289 
0290             if(abs(derot_freq) > derot_limit)
0291                 next_loop--;
0292 
0293             if (next_loop) {
0294                 reg = stb0899_read_reg(state, STB0899_CFD);
0295                 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
0296                 stb0899_write_reg(state, STB0899_CFD, reg);
0297 
0298                 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
0299                 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
0300                 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
0301             }
0302         }
0303 
0304         internal->direction = -internal->direction; /* Change zigzag direction */
0305     } while ((internal->status != CARRIEROK) && next_loop);
0306 
0307     if (internal->status == CARRIEROK) {
0308         stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
0309         internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
0310         dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
0311     } else {
0312         internal->derot_freq = last_derot_freq;
0313     }
0314 
0315     return internal->status;
0316 }
0317 
0318 /*
0319  * stb0899_check_data
0320  * Check for data found
0321  */
0322 static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
0323 {
0324     struct stb0899_internal *internal = &state->internal;
0325     struct stb0899_params *params = &state->params;
0326 
0327     int lock = 0, index = 0, dataTime = 500, loop;
0328     u8 reg;
0329 
0330     internal->status = NODATA;
0331 
0332     /* RESET FEC    */
0333     reg = stb0899_read_reg(state, STB0899_TSTRES);
0334     STB0899_SETFIELD_VAL(FRESACS, reg, 1);
0335     stb0899_write_reg(state, STB0899_TSTRES, reg);
0336     msleep(1);
0337     reg = stb0899_read_reg(state, STB0899_TSTRES);
0338     STB0899_SETFIELD_VAL(FRESACS, reg, 0);
0339     stb0899_write_reg(state, STB0899_TSTRES, reg);
0340 
0341     if (params->srate <= 2000000)
0342         dataTime = 2000;
0343     else if (params->srate <= 5000000)
0344         dataTime = 1500;
0345     else if (params->srate <= 15000000)
0346         dataTime = 1000;
0347     else
0348         dataTime = 500;
0349 
0350     /* clear previous failed END_LOOPVIT */
0351     stb0899_read_reg(state, STB0899_VSTATUS);
0352 
0353     stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop  */
0354     while (1) {
0355         /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP    */
0356         reg = stb0899_read_reg(state, STB0899_VSTATUS);
0357         lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
0358         loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
0359 
0360         if (lock || loop || (index > dataTime))
0361             break;
0362         index++;
0363     }
0364 
0365     if (lock) { /* DATA LOCK indicator  */
0366         internal->status = DATAOK;
0367         dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
0368     }
0369 
0370     return internal->status;
0371 }
0372 
0373 /*
0374  * stb0899_search_data
0375  * Search for a QPSK carrier with the derotator
0376  */
0377 static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
0378 {
0379     short int derot_freq, derot_step, derot_limit, next_loop = 3;
0380     u8 cfr[2];
0381     u8 reg;
0382     int index = 1;
0383 
0384     struct stb0899_internal *internal = &state->internal;
0385     struct stb0899_params *params = &state->params;
0386 
0387     derot_step = (params->srate / 4L) / internal->mclk;
0388     derot_limit = (internal->sub_range / 2L) / internal->mclk;
0389     derot_freq = internal->derot_freq;
0390 
0391     do {
0392         if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
0393 
0394             derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */
0395             if (abs(derot_freq) > derot_limit)
0396                 next_loop--;
0397 
0398             if (next_loop) {
0399                 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
0400                 reg = stb0899_read_reg(state, STB0899_CFD);
0401                 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
0402                 stb0899_write_reg(state, STB0899_CFD, reg);
0403 
0404                 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
0405                 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
0406                 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
0407 
0408                 stb0899_check_carrier(state);
0409                 index++;
0410             }
0411         }
0412         internal->direction = -internal->direction; /* change zig zag direction */
0413     } while ((internal->status != DATAOK) && next_loop);
0414 
0415     if (internal->status == DATAOK) {
0416         stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
0417 
0418         /* store autodetected IQ swapping as default for DVB-S2 tuning */
0419         reg = stb0899_read_reg(state, STB0899_IQSWAP);
0420         if (STB0899_GETFIELD(SYM, reg))
0421             internal->inversion = IQ_SWAP_ON;
0422         else
0423             internal->inversion = IQ_SWAP_OFF;
0424 
0425         internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
0426         dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
0427     }
0428 
0429     return internal->status;
0430 }
0431 
0432 /*
0433  * stb0899_check_range
0434  * check if the found frequency is in the correct range
0435  */
0436 static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
0437 {
0438     struct stb0899_internal *internal = &state->internal;
0439     struct stb0899_params *params = &state->params;
0440 
0441     int range_offst, tp_freq;
0442 
0443     range_offst = internal->srch_range / 2000;
0444     tp_freq = internal->freq - (internal->derot_freq * internal->mclk) / 1000;
0445 
0446     if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
0447         internal->status = RANGEOK;
0448         dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
0449     } else {
0450         internal->status = OUTOFRANGE;
0451         dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
0452     }
0453 
0454     return internal->status;
0455 }
0456 
0457 /*
0458  * NextSubRange
0459  * Compute the next subrange of the search
0460  */
0461 static void next_sub_range(struct stb0899_state *state)
0462 {
0463     struct stb0899_internal *internal = &state->internal;
0464     struct stb0899_params *params = &state->params;
0465 
0466     long old_sub_range;
0467 
0468     if (internal->sub_dir > 0) {
0469         old_sub_range = internal->sub_range;
0470         internal->sub_range = min((internal->srch_range / 2) -
0471                       (internal->tuner_offst + internal->sub_range / 2),
0472                        internal->sub_range);
0473 
0474         if (internal->sub_range < 0)
0475             internal->sub_range = 0;
0476 
0477         internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
0478     }
0479 
0480     internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
0481     internal->sub_dir = -internal->sub_dir;
0482 }
0483 
0484 /*
0485  * stb0899_dvbs_algo
0486  * Search for a signal, timing, carrier and data for a
0487  * given frequency in a given range
0488  */
0489 enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
0490 {
0491     struct stb0899_params *params       = &state->params;
0492     struct stb0899_internal *internal   = &state->internal;
0493     struct stb0899_config *config       = state->config;
0494 
0495     u8 bclc, reg;
0496     u8 cfr[2];
0497     u8 eq_const[10];
0498     s32 clnI = 3;
0499     u32 bandwidth = 0;
0500 
0501     /* BETA values rated @ 99MHz    */
0502     s32 betaTab[5][4] = {
0503            /*  5   10   20   30MBps */
0504         { 37,  34,  32,  31 }, /* QPSK 1/2  */
0505         { 37,  35,  33,  31 }, /* QPSK 2/3  */
0506         { 37,  35,  33,  31 }, /* QPSK 3/4  */
0507         { 37,  36,  33,  32 }, /* QPSK 5/6  */
0508         { 37,  36,  33,  32 }  /* QPSK 7/8  */
0509     };
0510 
0511     internal->direction = 1;
0512 
0513     stb0899_set_srate(state, internal->master_clk, params->srate);
0514     /* Carrier loop optimization versus symbol rate for acquisition*/
0515     if (params->srate <= 5000000) {
0516         stb0899_write_reg(state, STB0899_ACLC, 0x89);
0517         bclc = stb0899_read_reg(state, STB0899_BCLC);
0518         STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
0519         stb0899_write_reg(state, STB0899_BCLC, bclc);
0520         clnI = 0;
0521     } else if (params->srate <= 15000000) {
0522         stb0899_write_reg(state, STB0899_ACLC, 0xc9);
0523         bclc = stb0899_read_reg(state, STB0899_BCLC);
0524         STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
0525         stb0899_write_reg(state, STB0899_BCLC, bclc);
0526         clnI = 1;
0527     } else if(params->srate <= 25000000) {
0528         stb0899_write_reg(state, STB0899_ACLC, 0x89);
0529         bclc = stb0899_read_reg(state, STB0899_BCLC);
0530         STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
0531         stb0899_write_reg(state, STB0899_BCLC, bclc);
0532         clnI = 2;
0533     } else {
0534         stb0899_write_reg(state, STB0899_ACLC, 0xc8);
0535         bclc = stb0899_read_reg(state, STB0899_BCLC);
0536         STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
0537         stb0899_write_reg(state, STB0899_BCLC, bclc);
0538         clnI = 3;
0539     }
0540 
0541     dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
0542     /* Set the timing loop to acquisition   */
0543     stb0899_write_reg(state, STB0899_RTC, 0x46);
0544     stb0899_write_reg(state, STB0899_CFD, 0xee);
0545 
0546     /* !! WARNING !!
0547      * Do not read any status variables while acquisition,
0548      * If any needed, read before the acquisition starts
0549      * querying status while acquiring causes the
0550      * acquisition to go bad and hence no locks.
0551      */
0552     dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
0553         internal->derot_percent, params->srate, internal->mclk);
0554 
0555     /* Initial calculations */
0556     internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol  */
0557     internal->t_derot = stb0899_calc_derot_time(params->srate);
0558     internal->t_data = 500;
0559 
0560     dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
0561     /* RESET Stream merger  */
0562     reg = stb0899_read_reg(state, STB0899_TSTRES);
0563     STB0899_SETFIELD_VAL(FRESRS, reg, 1);
0564     stb0899_write_reg(state, STB0899_TSTRES, reg);
0565 
0566     /*
0567      * Set KDIVIDER to an intermediate value between
0568      * 1/2 and 7/8 for acquisition
0569      */
0570     reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
0571     STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
0572     stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
0573 
0574     stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */
0575     stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
0576 
0577     stb0899_first_subrange(state);
0578     do {
0579         /* Initialisations */
0580         cfr[0] = cfr[1] = 0;
0581         stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency   */
0582 
0583         stb0899_write_reg(state, STB0899_RTF, 0);
0584         reg = stb0899_read_reg(state, STB0899_CFD);
0585         STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
0586         stb0899_write_reg(state, STB0899_CFD, reg);
0587 
0588         internal->derot_freq = 0;
0589         internal->status = NOAGC1;
0590 
0591         /* enable tuner I/O */
0592         stb0899_i2c_gate_ctrl(&state->frontend, 1);
0593 
0594         /* Move tuner to frequency */
0595         dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
0596         if (state->config->tuner_set_frequency)
0597             state->config->tuner_set_frequency(&state->frontend, internal->freq);
0598 
0599         if (state->config->tuner_get_frequency)
0600             state->config->tuner_get_frequency(&state->frontend, &internal->freq);
0601 
0602         msleep(internal->t_agc1 + internal->t_agc2 + internal->t_derot); /* AGC1, AGC2 and timing loop  */
0603         dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
0604         internal->status = AGC1OK;
0605 
0606         /* There is signal in the band  */
0607         if (config->tuner_get_bandwidth)
0608             config->tuner_get_bandwidth(&state->frontend, &bandwidth);
0609 
0610         /* disable tuner I/O */
0611         stb0899_i2c_gate_ctrl(&state->frontend, 0);
0612 
0613         if (params->srate <= bandwidth / 2)
0614             stb0899_search_tmg(state); /* For low rates (SCPC)  */
0615         else
0616             stb0899_check_tmg(state); /* For high rates (MCPC)  */
0617 
0618         if (internal->status == TIMINGOK) {
0619             dprintk(state->verbose, FE_DEBUG, 1,
0620                 "TIMING OK ! Derot freq=%d, mclk=%d",
0621                 internal->derot_freq, internal->mclk);
0622 
0623             if (stb0899_search_carrier(state) == CARRIEROK) {   /* Search for carrier   */
0624                 dprintk(state->verbose, FE_DEBUG, 1,
0625                     "CARRIER OK ! Derot freq=%d, mclk=%d",
0626                     internal->derot_freq, internal->mclk);
0627 
0628                 if (stb0899_search_data(state) == DATAOK) { /* Check for data   */
0629                     dprintk(state->verbose, FE_DEBUG, 1,
0630                         "DATA OK ! Derot freq=%d, mclk=%d",
0631                         internal->derot_freq, internal->mclk);
0632 
0633                     if (stb0899_check_range(state) == RANGEOK) {
0634                         dprintk(state->verbose, FE_DEBUG, 1,
0635                             "RANGE OK ! derot freq=%d, mclk=%d",
0636                             internal->derot_freq, internal->mclk);
0637 
0638                         internal->freq = params->freq - ((internal->derot_freq * internal->mclk) / 1000);
0639                         reg = stb0899_read_reg(state, STB0899_PLPARM);
0640                         internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
0641                         dprintk(state->verbose, FE_DEBUG, 1,
0642                             "freq=%d, internal resultant freq=%d",
0643                             params->freq, internal->freq);
0644 
0645                         dprintk(state->verbose, FE_DEBUG, 1,
0646                             "internal puncture rate=%d",
0647                             internal->fecrate);
0648                     }
0649                 }
0650             }
0651         }
0652         if (internal->status != RANGEOK)
0653             next_sub_range(state);
0654 
0655     } while (internal->sub_range && internal->status != RANGEOK);
0656 
0657     /* Set the timing loop to tracking  */
0658     stb0899_write_reg(state, STB0899_RTC, 0x33);
0659     stb0899_write_reg(state, STB0899_CFD, 0xf7);
0660     /* if locked and range ok, set Kdiv */
0661     if (internal->status == RANGEOK) {
0662         dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
0663         stb0899_write_reg(state, STB0899_EQON, 0x41);       /* Equalizer OFF while acquiring    */
0664         stb0899_write_reg(state, STB0899_VITSYNC, 0x39);    /* SN to b'11 for acquisition       */
0665 
0666         /*
0667          * Carrier loop optimization versus
0668          * symbol Rate/Puncture Rate for Tracking
0669          */
0670         reg = stb0899_read_reg(state, STB0899_BCLC);
0671         switch (internal->fecrate) {
0672         case STB0899_FEC_1_2:       /* 13   */
0673             stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a);
0674             STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
0675             stb0899_write_reg(state, STB0899_BCLC, reg);
0676             break;
0677         case STB0899_FEC_2_3:       /* 18   */
0678             stb0899_write_reg(state, STB0899_DEMAPVIT, 44);
0679             STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
0680             stb0899_write_reg(state, STB0899_BCLC, reg);
0681             break;
0682         case STB0899_FEC_3_4:       /* 21   */
0683             stb0899_write_reg(state, STB0899_DEMAPVIT, 60);
0684             STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
0685             stb0899_write_reg(state, STB0899_BCLC, reg);
0686             break;
0687         case STB0899_FEC_5_6:       /* 24   */
0688             stb0899_write_reg(state, STB0899_DEMAPVIT, 75);
0689             STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
0690             stb0899_write_reg(state, STB0899_BCLC, reg);
0691             break;
0692         case STB0899_FEC_6_7:       /* 25   */
0693             stb0899_write_reg(state, STB0899_DEMAPVIT, 88);
0694             stb0899_write_reg(state, STB0899_ACLC, 0x88);
0695             stb0899_write_reg(state, STB0899_BCLC, 0x9a);
0696             break;
0697         case STB0899_FEC_7_8:       /* 26   */
0698             stb0899_write_reg(state, STB0899_DEMAPVIT, 94);
0699             STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
0700             stb0899_write_reg(state, STB0899_BCLC, reg);
0701             break;
0702         default:
0703             dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
0704             break;
0705         }
0706         /* release stream merger RESET  */
0707         reg = stb0899_read_reg(state, STB0899_TSTRES);
0708         STB0899_SETFIELD_VAL(FRESRS, reg, 0);
0709         stb0899_write_reg(state, STB0899_TSTRES, reg);
0710 
0711         /* disable carrier detector */
0712         reg = stb0899_read_reg(state, STB0899_CFD);
0713         STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
0714         stb0899_write_reg(state, STB0899_CFD, reg);
0715 
0716         stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
0717     }
0718 
0719     return internal->status;
0720 }
0721 
0722 /*
0723  * stb0899_dvbs2_config_uwp
0724  * Configure UWP state machine
0725  */
0726 static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
0727 {
0728     struct stb0899_internal *internal = &state->internal;
0729     struct stb0899_config *config = state->config;
0730     u32 uwp1, uwp2, uwp3, reg;
0731 
0732     uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
0733     uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
0734     uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
0735 
0736     STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
0737     STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
0738     STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
0739 
0740     STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
0741     STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
0742     STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
0743 
0744     STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
0745     STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
0746 
0747     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
0748     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
0749     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
0750 
0751     reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
0752     STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
0753     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
0754 }
0755 
0756 /*
0757  * stb0899_dvbs2_config_csm_auto
0758  * Set CSM to AUTO mode
0759  */
0760 static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
0761 {
0762     u32 reg;
0763 
0764     reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
0765     STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
0766     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
0767 }
0768 
0769 static long Log2Int(int number)
0770 {
0771     int i;
0772 
0773     i = 0;
0774     while ((1 << i) <= abs(number))
0775         i++;
0776 
0777     if (number == 0)
0778         i = 1;
0779 
0780     return i - 1;
0781 }
0782 
0783 /*
0784  * stb0899_dvbs2_calc_srate
0785  * compute BTR_NOM_FREQ for the symbol rate
0786  */
0787 static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
0788 {
0789     struct stb0899_internal *internal   = &state->internal;
0790     struct stb0899_config *config       = state->config;
0791 
0792     u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
0793     u32 master_clk, srate;
0794 
0795     dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
0796     dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
0797     dec_rate = Log2Int(dec_ratio);
0798     decim = 1 << dec_rate;
0799     master_clk = internal->master_clk / 1000;
0800     srate = internal->srate / 1000;
0801 
0802     if (decim <= 4) {
0803         intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
0804         remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
0805     } else {
0806         intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
0807         remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
0808     }
0809     btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
0810 
0811     return btr_nom_freq;
0812 }
0813 
0814 /*
0815  * stb0899_dvbs2_calc_dev
0816  * compute the correction to be applied to symbol rate
0817  */
0818 static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
0819 {
0820     struct stb0899_internal *internal = &state->internal;
0821     u32 dec_ratio, correction, master_clk, srate;
0822 
0823     dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
0824     dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
0825 
0826     master_clk = internal->master_clk / 1000;   /* for integer Calculation*/
0827     srate = internal->srate / 1000; /* for integer Calculation*/
0828     correction = (512 * master_clk) / (2 * dec_ratio * srate);
0829 
0830     return  correction;
0831 }
0832 
0833 /*
0834  * stb0899_dvbs2_set_srate
0835  * Set DVBS2 symbol rate
0836  */
0837 static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
0838 {
0839     struct stb0899_internal *internal = &state->internal;
0840 
0841     u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
0842     u32 correction, freq_adj, band_lim, decim_cntrl, reg;
0843     u8 anti_alias;
0844 
0845     /*set decimation to 1*/
0846     dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
0847     dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
0848     dec_rate = Log2Int(dec_ratio);
0849 
0850     win_sel = 0;
0851     if (dec_rate >= 5)
0852         win_sel = dec_rate - 4;
0853 
0854     decim = (1 << dec_rate);
0855     /* (FSamp/Fsymbol *100) for integer Calculation */
0856     f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
0857 
0858     if (f_sym <= 2250)  /* don't band limit signal going into btr block*/
0859         band_lim = 1;
0860     else
0861         band_lim = 0;   /* band limit signal going into btr block*/
0862 
0863     decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
0864     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
0865 
0866     if (f_sym <= 3450)
0867         anti_alias = 0;
0868     else if (f_sym <= 4250)
0869         anti_alias = 1;
0870     else
0871         anti_alias = 2;
0872 
0873     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
0874     btr_nom_freq = stb0899_dvbs2_calc_srate(state);
0875     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
0876 
0877     correction = stb0899_dvbs2_calc_dev(state);
0878     reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
0879     STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
0880     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
0881 
0882     /* scale UWP+CSM frequency to sample rate*/
0883     freq_adj =  internal->srate / (internal->master_clk / 4096);
0884     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
0885 }
0886 
0887 /*
0888  * stb0899_dvbs2_set_btr_loopbw
0889  * set bit timing loop bandwidth as a percentage of the symbol rate
0890  */
0891 static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
0892 {
0893     struct stb0899_internal *internal   = &state->internal;
0894     struct stb0899_config *config       = state->config;
0895 
0896     u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
0897     s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
0898     s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
0899     u32 decim, K, wn, k_direct, k_indirect;
0900     u32 reg;
0901 
0902     dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
0903     dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
0904     dec_rate = Log2Int(dec_ratio);
0905     decim = (1 << dec_rate);
0906 
0907     sym_peak *= 576000;
0908     K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
0909     K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
0910 
0911     if (K != 0) {
0912         K = sym_peak / K;
0913         wn = (4 * zeta * zeta) + 1000000;
0914         wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn;  /*wn =wn 10^-8*/
0915 
0916         k_indirect = (wn * wn) / K; /*kindirect = kindirect 10^-6*/
0917         k_direct   = (2 * wn * zeta) / K;   /*kDirect = kDirect 10^-2*/
0918         k_direct  *= 100;
0919 
0920         k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
0921         k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
0922         k_btr1 = k_direct / (1 << k_direct_shift);
0923         k_btr1 /= 10000;
0924 
0925         k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
0926         k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
0927         k_btr0 = k_indirect * (1 << (-k_indirect_shift));
0928         k_btr0 /= 1000000;
0929 
0930         k_btr2_rshft = 0;
0931         if (k_btr0_rshft > 15) {
0932             k_btr2_rshft = k_btr0_rshft - 15;
0933             k_btr0_rshft = 15;
0934         }
0935         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
0936         STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
0937         STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
0938         STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
0939         STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
0940         STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
0941         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
0942     } else
0943         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
0944 }
0945 
0946 /*
0947  * stb0899_dvbs2_set_carr_freq
0948  * set nominal frequency for carrier search
0949  */
0950 static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
0951 {
0952     struct stb0899_config *config = state->config;
0953     s32 crl_nom_freq;
0954     u32 reg;
0955 
0956     crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
0957     crl_nom_freq *= carr_freq;
0958     reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
0959     STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
0960     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
0961 }
0962 
0963 /*
0964  * stb0899_dvbs2_init_calc
0965  * Initialize DVBS2 UWP, CSM, carrier and timing loops
0966  */
0967 static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
0968 {
0969     struct stb0899_internal *internal = &state->internal;
0970     s32 steps, step_size;
0971     u32 range, reg;
0972 
0973     /* config uwp and csm */
0974     stb0899_dvbs2_config_uwp(state);
0975     stb0899_dvbs2_config_csm_auto(state);
0976 
0977     /* initialize BTR   */
0978     stb0899_dvbs2_set_srate(state);
0979     stb0899_dvbs2_set_btr_loopbw(state);
0980 
0981     if (internal->srate / 1000000 >= 15)
0982         step_size = (1 << 17) / 5;
0983     else if (internal->srate / 1000000 >= 10)
0984         step_size = (1 << 17) / 7;
0985     else if (internal->srate / 1000000 >= 5)
0986         step_size = (1 << 17) / 10;
0987     else
0988         step_size = (1 << 17) / 4;
0989 
0990     range = internal->srch_range / 1000000;
0991     steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
0992     steps = (steps + 6) / 10;
0993     steps = (steps == 0) ? 1 : steps;
0994     if (steps % 2 == 0)
0995         stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
0996                        (internal->step_size * (internal->srate / 20000000)),
0997                        (internal->master_clk) / 1000000);
0998     else
0999         stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
1000 
1001     /*Set Carrier Search params (zigzag, num steps and freq step size*/
1002     reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
1003     STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
1004     STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
1005     STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
1006     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
1007 }
1008 
1009 /*
1010  * stb0899_dvbs2_btr_init
1011  * initialize the timing loop
1012  */
1013 static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
1014 {
1015     u32 reg;
1016 
1017     /* set enable BTR loopback  */
1018     reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
1019     STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
1020     STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
1021     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
1022 
1023     /* fix btr freq accum at 0  */
1024     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
1025     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
1026 
1027     /* fix btr freq accum at 0  */
1028     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
1029     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
1030 }
1031 
1032 /*
1033  * stb0899_dvbs2_reacquire
1034  * trigger a DVB-S2 acquisition
1035  */
1036 static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
1037 {
1038     u32 reg = 0;
1039 
1040     /* demod soft reset */
1041     STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
1042     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1043 
1044     /*Reset Timing Loop */
1045     stb0899_dvbs2_btr_init(state);
1046 
1047     /* reset Carrier loop   */
1048     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
1049     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
1050     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
1051     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
1052     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
1053 
1054     /*release demod soft reset  */
1055     reg = 0;
1056     STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
1057     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1058 
1059     /* start acquisition process    */
1060     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
1061     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
1062 
1063     /* equalizer Init   */
1064     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
1065 
1066     /*Start equilizer   */
1067     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
1068 
1069     reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1070     STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
1071     STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
1072     STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
1073     STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
1074     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1075 
1076     /* RESET Packet delineator  */
1077     stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
1078 }
1079 
1080 /*
1081  * stb0899_dvbs2_get_dmd_status
1082  * get DVB-S2 Demod LOCK status
1083  */
1084 static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
1085 {
1086     int time = -10, lock = 0, uwp, csm;
1087     u32 reg;
1088 
1089     do {
1090         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1091         dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1092         if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
1093             dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
1094         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1095         dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
1096         uwp = STB0899_GETFIELD(UWP_LOCK, reg);
1097         csm = STB0899_GETFIELD(CSM_LOCK, reg);
1098         if (uwp && csm)
1099             lock = 1;
1100 
1101         time += 10;
1102         msleep(10);
1103 
1104     } while ((!lock) && (time <= timeout));
1105 
1106     if (lock) {
1107         dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
1108         return DVBS2_DEMOD_LOCK;
1109     } else {
1110         return DVBS2_DEMOD_NOLOCK;
1111     }
1112 }
1113 
1114 /*
1115  * stb0899_dvbs2_get_data_lock
1116  * get FEC status
1117  */
1118 static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
1119 {
1120     int time = 0, lock = 0;
1121     u8 reg;
1122 
1123     while ((!lock) && (time < timeout)) {
1124         reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1125         dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
1126         lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
1127         time++;
1128     }
1129 
1130     return lock;
1131 }
1132 
1133 /*
1134  * stb0899_dvbs2_get_fec_status
1135  * get DVB-S2 FEC LOCK status
1136  */
1137 static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
1138 {
1139     int time = 0, Locked;
1140 
1141     do {
1142         Locked = stb0899_dvbs2_get_data_lock(state, 1);
1143         time++;
1144         msleep(1);
1145 
1146     } while ((!Locked) && (time < timeout));
1147 
1148     if (Locked) {
1149         dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
1150         return DVBS2_FEC_LOCK;
1151     } else {
1152         return DVBS2_FEC_NOLOCK;
1153     }
1154 }
1155 
1156 
1157 /*
1158  * stb0899_dvbs2_init_csm
1159  * set parameters for manual mode
1160  */
1161 static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
1162 {
1163     struct stb0899_internal *internal = &state->internal;
1164 
1165     s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
1166     s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
1167     u32 csm1, csm2, csm3, csm4;
1168 
1169     if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
1170         switch (modcod) {
1171         case STB0899_QPSK_12:
1172             gamma_acq       = 25;
1173             gamma_rho_acq       = 2700;
1174             gamma_trk       = 12;
1175             gamma_rho_trk       = 180;
1176             lock_count_thr      = 8;
1177             break;
1178         case STB0899_QPSK_35:
1179             gamma_acq       = 38;
1180             gamma_rho_acq       = 7182;
1181             gamma_trk       = 14;
1182             gamma_rho_trk       = 308;
1183             lock_count_thr      = 8;
1184             break;
1185         case STB0899_QPSK_23:
1186             gamma_acq       = 42;
1187             gamma_rho_acq       = 9408;
1188             gamma_trk       = 17;
1189             gamma_rho_trk       = 476;
1190             lock_count_thr      = 8;
1191             break;
1192         case STB0899_QPSK_34:
1193             gamma_acq       = 53;
1194             gamma_rho_acq       = 16642;
1195             gamma_trk       = 19;
1196             gamma_rho_trk       = 646;
1197             lock_count_thr      = 8;
1198             break;
1199         case STB0899_QPSK_45:
1200             gamma_acq       = 53;
1201             gamma_rho_acq       = 17119;
1202             gamma_trk       = 22;
1203             gamma_rho_trk       = 880;
1204             lock_count_thr      = 8;
1205             break;
1206         case STB0899_QPSK_56:
1207             gamma_acq       = 55;
1208             gamma_rho_acq       = 19250;
1209             gamma_trk       = 23;
1210             gamma_rho_trk       = 989;
1211             lock_count_thr      = 8;
1212             break;
1213         case STB0899_QPSK_89:
1214             gamma_acq       = 60;
1215             gamma_rho_acq       = 24240;
1216             gamma_trk       = 24;
1217             gamma_rho_trk       = 1176;
1218             lock_count_thr      = 8;
1219             break;
1220         case STB0899_QPSK_910:
1221             gamma_acq       = 66;
1222             gamma_rho_acq       = 29634;
1223             gamma_trk       = 24;
1224             gamma_rho_trk       = 1176;
1225             lock_count_thr      = 8;
1226             break;
1227         default:
1228             gamma_acq       = 66;
1229             gamma_rho_acq       = 29634;
1230             gamma_trk       = 24;
1231             gamma_rho_trk       = 1176;
1232             lock_count_thr      = 8;
1233             break;
1234         }
1235 
1236         csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1237         STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
1238         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1239 
1240         csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1241         csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
1242         csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
1243         csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
1244 
1245         STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
1246         STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
1247         STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
1248         STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
1249         STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
1250         STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
1251         STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
1252         STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
1253         STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
1254         STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
1255         STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
1256 
1257         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1258         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
1259         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
1260         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
1261     }
1262 }
1263 
1264 /*
1265  * stb0899_dvbs2_get_srate
1266  * get DVB-S2 Symbol Rate
1267  */
1268 static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
1269 {
1270     struct stb0899_internal *internal = &state->internal;
1271     struct stb0899_config *config = state->config;
1272 
1273     u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
1274     int div1, div2, rem1, rem2;
1275 
1276     div1 = config->btr_nco_bits / 2;
1277     div2 = config->btr_nco_bits - div1 - 1;
1278 
1279     bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
1280 
1281     reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
1282     decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
1283     decimRate = (1 << decimRate);
1284 
1285     intval1 = internal->master_clk / (1 << div1);
1286     intval2 = bTrNomFreq / (1 << div2);
1287 
1288     rem1 = internal->master_clk % (1 << div1);
1289     rem2 = bTrNomFreq % (1 << div2);
1290     /* only for integer calculation */
1291     srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
1292     srate /= decimRate; /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
1293 
1294     return  srate;
1295 }
1296 
1297 /*
1298  * stb0899_dvbs2_algo
1299  * Search for signal, timing, carrier and data for a given
1300  * frequency in a given range
1301  */
1302 enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
1303 {
1304     struct stb0899_internal *internal = &state->internal;
1305     enum stb0899_modcod modcod;
1306 
1307     s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
1308     int i = 0;
1309     u32 reg, csm1;
1310 
1311     if (internal->srate <= 2000000) {
1312         searchTime  = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs       */
1313         FecLockTime = 350;  /* 350  ms max time to lock FEC, SYMB <= 2Mbs           */
1314     } else if (internal->srate <= 5000000) {
1315         searchTime  = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs    */
1316         FecLockTime = 170;  /* 170  ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs     */
1317     } else if (internal->srate <= 10000000) {
1318         searchTime  = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs    */
1319         FecLockTime = 80;   /* 80  ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs     */
1320     } else if (internal->srate <= 15000000) {
1321         searchTime  = 500;  /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs    */
1322         FecLockTime = 50;   /* 50  ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs        */
1323     } else if (internal->srate <= 20000000) {
1324         searchTime  = 300;  /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs   */
1325         FecLockTime = 30;   /* 50  ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs        */
1326     } else if (internal->srate <= 25000000) {
1327         searchTime  = 250;  /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs  */
1328         FecLockTime = 25;   /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs     */
1329     } else {
1330         searchTime  = 150;  /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs        */
1331         FecLockTime = 20;   /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs     */
1332     }
1333 
1334     /* Maintain Stream Merger in reset during acquisition   */
1335     reg = stb0899_read_reg(state, STB0899_TSTRES);
1336     STB0899_SETFIELD_VAL(FRESRS, reg, 1);
1337     stb0899_write_reg(state, STB0899_TSTRES, reg);
1338 
1339     /* enable tuner I/O */
1340     stb0899_i2c_gate_ctrl(&state->frontend, 1);
1341 
1342     /* Move tuner to frequency  */
1343     if (state->config->tuner_set_frequency)
1344         state->config->tuner_set_frequency(&state->frontend, internal->freq);
1345     if (state->config->tuner_get_frequency)
1346         state->config->tuner_get_frequency(&state->frontend, &internal->freq);
1347 
1348     /* disable tuner I/O */
1349     stb0899_i2c_gate_ctrl(&state->frontend, 0);
1350 
1351     /* Set IF AGC to acquisition    */
1352     reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1353     STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg,  4);
1354     STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
1355     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1356 
1357     reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1358     STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
1359     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1360 
1361     /* Initialisation   */
1362     stb0899_dvbs2_init_calc(state);
1363 
1364     reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1365     switch (internal->inversion) {
1366     case IQ_SWAP_OFF:
1367         STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
1368         break;
1369     case IQ_SWAP_ON:
1370         STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1371         break;
1372     }
1373     stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1374     stb0899_dvbs2_reacquire(state);
1375 
1376     /* Wait for demod lock (UWP and CSM)    */
1377     internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1378 
1379     if (internal->status == DVBS2_DEMOD_LOCK) {
1380         dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
1381         i = 0;
1382         /* Demod Locked, check FEC status   */
1383         internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1384 
1385         /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
1386         while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1387             /*  Read the frequency offset*/
1388             offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1389 
1390             /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1391             reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1392             STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1393             stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1394             stb0899_dvbs2_reacquire(state);
1395             internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1396             i++;
1397         }
1398     }
1399 
1400     if (internal->status != DVBS2_FEC_LOCK) {
1401         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1402         iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
1403         /* IQ Spectrum Inversion    */
1404         STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
1405         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1406         /* start acquistion process */
1407         stb0899_dvbs2_reacquire(state);
1408 
1409         /* Wait for demod lock (UWP and CSM)    */
1410         internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1411         if (internal->status == DVBS2_DEMOD_LOCK) {
1412             i = 0;
1413             /* Demod Locked, check FEC  */
1414             internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1415             /*try thrice for false locks, (UWP and CSM Locked but no FEC)   */
1416             while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1417                 /*  Read the frequency offset*/
1418                 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1419 
1420                 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1421                 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1422                 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1423                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1424 
1425                 stb0899_dvbs2_reacquire(state);
1426                 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1427                 i++;
1428             }
1429         }
1430 /*
1431         if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
1432             pParams->IQLocked = !iqSpectrum;
1433 */
1434     }
1435     if (internal->status == DVBS2_FEC_LOCK) {
1436         dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
1437         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1438         modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1439         pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1440 
1441         if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1442               (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
1443               (pilots == 1)) {
1444 
1445             stb0899_dvbs2_init_csm(state, pilots, modcod);
1446             /* Wait for UWP,CSM and data LOCK 20ms max  */
1447             internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1448 
1449             i = 0;
1450             while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1451                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1452                 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
1453                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1454                 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1455                 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
1456                 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1457 
1458                 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1459                 i++;
1460             }
1461         }
1462 
1463         if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1464               (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
1465               (pilots == 1)) {
1466 
1467             /* Equalizer Disable update  */
1468             reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1469             STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
1470             stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1471         }
1472 
1473         /* slow down the Equalizer once locked  */
1474         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1475         STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
1476         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1477 
1478         /* Store signal parameters  */
1479         offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1480 
1481         offsetfreq = sign_extend32(offsetfreq, 29);
1482 
1483         offsetfreq = offsetfreq / ((1 << 30) / 1000);
1484         offsetfreq *= (internal->master_clk / 1000000);
1485 
1486         /* store current inversion for next run */
1487         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1488         if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
1489             internal->inversion = IQ_SWAP_ON;
1490         else
1491             internal->inversion = IQ_SWAP_OFF;
1492 
1493         internal->freq = internal->freq + offsetfreq;
1494         internal->srate = stb0899_dvbs2_get_srate(state);
1495 
1496         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1497         internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1498         internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1499         internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
1500 
1501          /* Set IF AGC to tracking  */
1502         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1503         STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg,  3);
1504 
1505         /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
1506         if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
1507             STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
1508 
1509         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1510 
1511         reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1512         STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
1513         stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1514     }
1515 
1516     /* Release Stream Merger Reset      */
1517     reg = stb0899_read_reg(state, STB0899_TSTRES);
1518     STB0899_SETFIELD_VAL(FRESRS, reg, 0);
1519     stb0899_write_reg(state, STB0899_TSTRES, reg);
1520 
1521     return internal->status;
1522 }
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