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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003    Driver for the Spase sp887x demodulator
0004 */
0005 
0006 /*
0007  * This driver needs external firmware. Please use the command
0008  * "<kerneldir>/scripts/get_dvb_firmware sp887x" to
0009  * download/extract it, and then copy it to /usr/lib/hotplug/firmware
0010  * or /lib/firmware (depending on configuration of firmware hotplug).
0011  */
0012 #define SP887X_DEFAULT_FIRMWARE "dvb-fe-sp887x.fw"
0013 
0014 #include <linux/init.h>
0015 #include <linux/module.h>
0016 #include <linux/device.h>
0017 #include <linux/firmware.h>
0018 #include <linux/string.h>
0019 #include <linux/slab.h>
0020 
0021 #include <media/dvb_frontend.h>
0022 #include "sp887x.h"
0023 
0024 
0025 struct sp887x_state {
0026     struct i2c_adapter* i2c;
0027     const struct sp887x_config* config;
0028     struct dvb_frontend frontend;
0029 
0030     /* demodulator private data */
0031     u8 initialised:1;
0032 };
0033 
0034 static int debug;
0035 #define dprintk(args...) \
0036     do { \
0037         if (debug) printk(KERN_DEBUG "sp887x: " args); \
0038     } while (0)
0039 
0040 static int i2c_writebytes (struct sp887x_state* state, u8 *buf, u8 len)
0041 {
0042     struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = len };
0043     int err;
0044 
0045     if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
0046         printk ("%s: i2c write error (addr %02x, err == %i)\n",
0047             __func__, state->config->demod_address, err);
0048         return -EREMOTEIO;
0049     }
0050 
0051     return 0;
0052 }
0053 
0054 static int sp887x_writereg (struct sp887x_state* state, u16 reg, u16 data)
0055 {
0056     u8 b0 [] = { reg >> 8 , reg & 0xff, data >> 8, data & 0xff };
0057     struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 4 };
0058     int ret;
0059 
0060     if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1) {
0061         /*
0062          *  in case of soft reset we ignore ACK errors...
0063          */
0064         if (!(reg == 0xf1a && data == 0x000 &&
0065             (ret == -EREMOTEIO || ret == -EFAULT)))
0066         {
0067             printk("%s: writereg error (reg %03x, data %03x, ret == %i)\n",
0068                    __func__, reg & 0xffff, data & 0xffff, ret);
0069             return ret;
0070         }
0071     }
0072 
0073     return 0;
0074 }
0075 
0076 static int sp887x_readreg (struct sp887x_state* state, u16 reg)
0077 {
0078     u8 b0 [] = { reg >> 8 , reg & 0xff };
0079     u8 b1 [2];
0080     int ret;
0081     struct i2c_msg msg[] = {{ .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 },
0082              { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 2 }};
0083 
0084     if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) {
0085         printk("%s: readreg error (ret == %i)\n", __func__, ret);
0086         return -1;
0087     }
0088 
0089     return (((b1[0] << 8) | b1[1]) & 0xfff);
0090 }
0091 
0092 static void sp887x_microcontroller_stop (struct sp887x_state* state)
0093 {
0094     dprintk("%s\n", __func__);
0095     sp887x_writereg(state, 0xf08, 0x000);
0096     sp887x_writereg(state, 0xf09, 0x000);
0097 
0098     /* microcontroller STOP */
0099     sp887x_writereg(state, 0xf00, 0x000);
0100 }
0101 
0102 static void sp887x_microcontroller_start (struct sp887x_state* state)
0103 {
0104     dprintk("%s\n", __func__);
0105     sp887x_writereg(state, 0xf08, 0x000);
0106     sp887x_writereg(state, 0xf09, 0x000);
0107 
0108     /* microcontroller START */
0109     sp887x_writereg(state, 0xf00, 0x001);
0110 }
0111 
0112 static void sp887x_setup_agc (struct sp887x_state* state)
0113 {
0114     /* setup AGC parameters */
0115     dprintk("%s\n", __func__);
0116     sp887x_writereg(state, 0x33c, 0x054);
0117     sp887x_writereg(state, 0x33b, 0x04c);
0118     sp887x_writereg(state, 0x328, 0x000);
0119     sp887x_writereg(state, 0x327, 0x005);
0120     sp887x_writereg(state, 0x326, 0x001);
0121     sp887x_writereg(state, 0x325, 0x001);
0122     sp887x_writereg(state, 0x324, 0x001);
0123     sp887x_writereg(state, 0x318, 0x050);
0124     sp887x_writereg(state, 0x317, 0x3fe);
0125     sp887x_writereg(state, 0x316, 0x001);
0126     sp887x_writereg(state, 0x313, 0x005);
0127     sp887x_writereg(state, 0x312, 0x002);
0128     sp887x_writereg(state, 0x306, 0x000);
0129     sp887x_writereg(state, 0x303, 0x000);
0130 }
0131 
0132 #define BLOCKSIZE 30
0133 #define FW_SIZE 0x4000
0134 /*
0135  *  load firmware and setup MPEG interface...
0136  */
0137 static int sp887x_initial_setup (struct dvb_frontend* fe, const struct firmware *fw)
0138 {
0139     struct sp887x_state* state = fe->demodulator_priv;
0140     u8 buf [BLOCKSIZE + 2];
0141     int i;
0142     int fw_size = fw->size;
0143     const unsigned char *mem = fw->data + 10;
0144 
0145     dprintk("%s\n", __func__);
0146 
0147     /* ignore the first 10 bytes, then we expect 0x4000 bytes of firmware */
0148     if (fw_size < FW_SIZE + 10)
0149         return -ENODEV;
0150 
0151     /* soft reset */
0152     sp887x_writereg(state, 0xf1a, 0x000);
0153 
0154     sp887x_microcontroller_stop (state);
0155 
0156     printk ("%s: firmware upload... ", __func__);
0157 
0158     /* setup write pointer to -1 (end of memory) */
0159     /* bit 0x8000 in address is set to enable 13bit mode */
0160     sp887x_writereg(state, 0x8f08, 0x1fff);
0161 
0162     /* dummy write (wrap around to start of memory) */
0163     sp887x_writereg(state, 0x8f0a, 0x0000);
0164 
0165     for (i = 0; i < FW_SIZE; i += BLOCKSIZE) {
0166         int c = BLOCKSIZE;
0167         int err;
0168 
0169         if (c > FW_SIZE - i)
0170             c = FW_SIZE - i;
0171 
0172         /* bit 0x8000 in address is set to enable 13bit mode */
0173         /* bit 0x4000 enables multibyte read/write transfers */
0174         /* write register is 0xf0a */
0175         buf[0] = 0xcf;
0176         buf[1] = 0x0a;
0177 
0178         memcpy(&buf[2], mem + i, c);
0179 
0180         if ((err = i2c_writebytes (state, buf, c+2)) < 0) {
0181             printk ("failed.\n");
0182             printk ("%s: i2c error (err == %i)\n", __func__, err);
0183             return err;
0184         }
0185     }
0186 
0187     /* don't write RS bytes between packets */
0188     sp887x_writereg(state, 0xc13, 0x001);
0189 
0190     /* suppress clock if (!data_valid) */
0191     sp887x_writereg(state, 0xc14, 0x000);
0192 
0193     /* setup MPEG interface... */
0194     sp887x_writereg(state, 0xc1a, 0x872);
0195     sp887x_writereg(state, 0xc1b, 0x001);
0196     sp887x_writereg(state, 0xc1c, 0x000); /* parallel mode (serial mode == 1) */
0197     sp887x_writereg(state, 0xc1a, 0x871);
0198 
0199     /* ADC mode, 2 for MT8872, 3 for SP8870/SP8871 */
0200     sp887x_writereg(state, 0x301, 0x002);
0201 
0202     sp887x_setup_agc(state);
0203 
0204     /* bit 0x010: enable data valid signal */
0205     sp887x_writereg(state, 0xd00, 0x010);
0206     sp887x_writereg(state, 0x0d1, 0x000);
0207     return 0;
0208 };
0209 
0210 static int configure_reg0xc05(struct dtv_frontend_properties *p, u16 *reg0xc05)
0211 {
0212     int known_parameters = 1;
0213 
0214     *reg0xc05 = 0x000;
0215 
0216     switch (p->modulation) {
0217     case QPSK:
0218         break;
0219     case QAM_16:
0220         *reg0xc05 |= (1 << 10);
0221         break;
0222     case QAM_64:
0223         *reg0xc05 |= (2 << 10);
0224         break;
0225     case QAM_AUTO:
0226         known_parameters = 0;
0227         break;
0228     default:
0229         return -EINVAL;
0230     }
0231 
0232     switch (p->hierarchy) {
0233     case HIERARCHY_NONE:
0234         break;
0235     case HIERARCHY_1:
0236         *reg0xc05 |= (1 << 7);
0237         break;
0238     case HIERARCHY_2:
0239         *reg0xc05 |= (2 << 7);
0240         break;
0241     case HIERARCHY_4:
0242         *reg0xc05 |= (3 << 7);
0243         break;
0244     case HIERARCHY_AUTO:
0245         known_parameters = 0;
0246         break;
0247     default:
0248         return -EINVAL;
0249     }
0250 
0251     switch (p->code_rate_HP) {
0252     case FEC_1_2:
0253         break;
0254     case FEC_2_3:
0255         *reg0xc05 |= (1 << 3);
0256         break;
0257     case FEC_3_4:
0258         *reg0xc05 |= (2 << 3);
0259         break;
0260     case FEC_5_6:
0261         *reg0xc05 |= (3 << 3);
0262         break;
0263     case FEC_7_8:
0264         *reg0xc05 |= (4 << 3);
0265         break;
0266     case FEC_AUTO:
0267         known_parameters = 0;
0268         break;
0269     default:
0270         return -EINVAL;
0271     }
0272 
0273     if (known_parameters)
0274         *reg0xc05 |= (2 << 1);  /* use specified parameters */
0275     else
0276         *reg0xc05 |= (1 << 1);  /* enable autoprobing */
0277 
0278     return 0;
0279 }
0280 
0281 /*
0282  *  estimates division of two 24bit numbers,
0283  *  derived from the ves1820/stv0299 driver code
0284  */
0285 static void divide (int n, int d, int *quotient_i, int *quotient_f)
0286 {
0287     unsigned int q, r;
0288 
0289     r = (n % d) << 8;
0290     q = (r / d);
0291 
0292     if (quotient_i)
0293         *quotient_i = q;
0294 
0295     if (quotient_f) {
0296         r = (r % d) << 8;
0297         q = (q << 8) | (r / d);
0298         r = (r % d) << 8;
0299         *quotient_f = (q << 8) | (r / d);
0300     }
0301 }
0302 
0303 static void sp887x_correct_offsets (struct sp887x_state* state,
0304                     struct dtv_frontend_properties *p,
0305                     int actual_freq)
0306 {
0307     static const u32 srate_correction [] = { 1879617, 4544878, 8098561 };
0308     int bw_index;
0309     int freq_offset = actual_freq - p->frequency;
0310     int sysclock = 61003; //[kHz]
0311     int ifreq = 36000000;
0312     int freq;
0313     int frequency_shift;
0314 
0315     switch (p->bandwidth_hz) {
0316     default:
0317     case 8000000:
0318         bw_index = 0;
0319         break;
0320     case 7000000:
0321         bw_index = 1;
0322         break;
0323     case 6000000:
0324         bw_index = 2;
0325         break;
0326     }
0327 
0328     if (p->inversion == INVERSION_ON)
0329         freq = ifreq - freq_offset;
0330     else
0331         freq = ifreq + freq_offset;
0332 
0333     divide(freq / 333, sysclock, NULL, &frequency_shift);
0334 
0335     if (p->inversion == INVERSION_ON)
0336         frequency_shift = -frequency_shift;
0337 
0338     /* sample rate correction */
0339     sp887x_writereg(state, 0x319, srate_correction[bw_index] >> 12);
0340     sp887x_writereg(state, 0x31a, srate_correction[bw_index] & 0xfff);
0341 
0342     /* carrier offset correction */
0343     sp887x_writereg(state, 0x309, frequency_shift >> 12);
0344     sp887x_writereg(state, 0x30a, frequency_shift & 0xfff);
0345 }
0346 
0347 static int sp887x_setup_frontend_parameters(struct dvb_frontend *fe)
0348 {
0349     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0350     struct sp887x_state* state = fe->demodulator_priv;
0351     unsigned actual_freq;
0352     int err;
0353     u16 val, reg0xc05;
0354 
0355     if (p->bandwidth_hz != 8000000 &&
0356         p->bandwidth_hz != 7000000 &&
0357         p->bandwidth_hz != 6000000)
0358         return -EINVAL;
0359 
0360     if ((err = configure_reg0xc05(p, &reg0xc05)))
0361         return err;
0362 
0363     sp887x_microcontroller_stop(state);
0364 
0365     /* setup the PLL */
0366     if (fe->ops.tuner_ops.set_params) {
0367         fe->ops.tuner_ops.set_params(fe);
0368         if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
0369     }
0370     if (fe->ops.tuner_ops.get_frequency) {
0371         fe->ops.tuner_ops.get_frequency(fe, &actual_freq);
0372         if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
0373     } else {
0374         actual_freq = p->frequency;
0375     }
0376 
0377     /* read status reg in order to clear <pending irqs */
0378     sp887x_readreg(state, 0x200);
0379 
0380     sp887x_correct_offsets(state, p, actual_freq);
0381 
0382     /* filter for 6/7/8 Mhz channel */
0383     if (p->bandwidth_hz == 6000000)
0384         val = 2;
0385     else if (p->bandwidth_hz == 7000000)
0386         val = 1;
0387     else
0388         val = 0;
0389 
0390     sp887x_writereg(state, 0x311, val);
0391 
0392     /* scan order: 2k first = 0, 8k first = 1 */
0393     if (p->transmission_mode == TRANSMISSION_MODE_2K)
0394         sp887x_writereg(state, 0x338, 0x000);
0395     else
0396         sp887x_writereg(state, 0x338, 0x001);
0397 
0398     sp887x_writereg(state, 0xc05, reg0xc05);
0399 
0400     if (p->bandwidth_hz == 6000000)
0401         val = 2 << 3;
0402     else if (p->bandwidth_hz == 7000000)
0403         val = 3 << 3;
0404     else
0405         val = 0 << 3;
0406 
0407     /* enable OFDM and SAW bits as lock indicators in sync register 0xf17,
0408      * optimize algorithm for given bandwidth...
0409      */
0410     sp887x_writereg(state, 0xf14, 0x160 | val);
0411     sp887x_writereg(state, 0xf15, 0x000);
0412 
0413     sp887x_microcontroller_start(state);
0414     return 0;
0415 }
0416 
0417 static int sp887x_read_status(struct dvb_frontend *fe, enum fe_status *status)
0418 {
0419     struct sp887x_state* state = fe->demodulator_priv;
0420     u16 snr12 = sp887x_readreg(state, 0xf16);
0421     u16 sync0x200 = sp887x_readreg(state, 0x200);
0422     u16 sync0xf17 = sp887x_readreg(state, 0xf17);
0423 
0424     *status = 0;
0425 
0426     if (snr12 > 0x00f)
0427         *status |= FE_HAS_SIGNAL;
0428 
0429     //if (sync0x200 & 0x004)
0430     //  *status |= FE_HAS_SYNC | FE_HAS_CARRIER;
0431 
0432     //if (sync0x200 & 0x008)
0433     //  *status |= FE_HAS_VITERBI;
0434 
0435     if ((sync0xf17 & 0x00f) == 0x002) {
0436         *status |= FE_HAS_LOCK;
0437         *status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_CARRIER;
0438     }
0439 
0440     if (sync0x200 & 0x001) {    /* tuner adjustment requested...*/
0441         int steps = (sync0x200 >> 4) & 0x00f;
0442         if (steps & 0x008)
0443             steps = -steps;
0444         dprintk("sp887x: implement tuner adjustment (%+i steps)!!\n",
0445                steps);
0446     }
0447 
0448     return 0;
0449 }
0450 
0451 static int sp887x_read_ber(struct dvb_frontend* fe, u32* ber)
0452 {
0453     struct sp887x_state* state = fe->demodulator_priv;
0454 
0455     *ber = (sp887x_readreg(state, 0xc08) & 0x3f) |
0456            (sp887x_readreg(state, 0xc07) << 6);
0457     sp887x_writereg(state, 0xc08, 0x000);
0458     sp887x_writereg(state, 0xc07, 0x000);
0459     if (*ber >= 0x3fff0)
0460         *ber = ~0;
0461 
0462     return 0;
0463 }
0464 
0465 static int sp887x_read_signal_strength(struct dvb_frontend* fe, u16* strength)
0466 {
0467     struct sp887x_state* state = fe->demodulator_priv;
0468 
0469     u16 snr12 = sp887x_readreg(state, 0xf16);
0470     u32 signal = 3 * (snr12 << 4);
0471     *strength = (signal < 0xffff) ? signal : 0xffff;
0472 
0473     return 0;
0474 }
0475 
0476 static int sp887x_read_snr(struct dvb_frontend* fe, u16* snr)
0477 {
0478     struct sp887x_state* state = fe->demodulator_priv;
0479 
0480     u16 snr12 = sp887x_readreg(state, 0xf16);
0481     *snr = (snr12 << 4) | (snr12 >> 8);
0482 
0483     return 0;
0484 }
0485 
0486 static int sp887x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
0487 {
0488     struct sp887x_state* state = fe->demodulator_priv;
0489 
0490     *ucblocks = sp887x_readreg(state, 0xc0c);
0491     if (*ucblocks == 0xfff)
0492         *ucblocks = ~0;
0493 
0494     return 0;
0495 }
0496 
0497 static int sp887x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
0498 {
0499     struct sp887x_state* state = fe->demodulator_priv;
0500 
0501     if (enable) {
0502         return sp887x_writereg(state, 0x206, 0x001);
0503     } else {
0504         return sp887x_writereg(state, 0x206, 0x000);
0505     }
0506 }
0507 
0508 static int sp887x_sleep(struct dvb_frontend* fe)
0509 {
0510     struct sp887x_state* state = fe->demodulator_priv;
0511 
0512     /* tristate TS output and disable interface pins */
0513     sp887x_writereg(state, 0xc18, 0x000);
0514 
0515     return 0;
0516 }
0517 
0518 static int sp887x_init(struct dvb_frontend* fe)
0519 {
0520     struct sp887x_state* state = fe->demodulator_priv;
0521     const struct firmware *fw = NULL;
0522     int ret;
0523 
0524     if (!state->initialised) {
0525         /* request the firmware, this will block until someone uploads it */
0526         printk("sp887x: waiting for firmware upload (%s)...\n", SP887X_DEFAULT_FIRMWARE);
0527         ret = state->config->request_firmware(fe, &fw, SP887X_DEFAULT_FIRMWARE);
0528         if (ret) {
0529             printk("sp887x: no firmware upload (timeout or file not found?)\n");
0530             return ret;
0531         }
0532 
0533         ret = sp887x_initial_setup(fe, fw);
0534         release_firmware(fw);
0535         if (ret) {
0536             printk("sp887x: writing firmware to device failed\n");
0537             return ret;
0538         }
0539         printk("sp887x: firmware upload complete\n");
0540         state->initialised = 1;
0541     }
0542 
0543     /* enable TS output and interface pins */
0544     sp887x_writereg(state, 0xc18, 0x00d);
0545 
0546     return 0;
0547 }
0548 
0549 static int sp887x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
0550 {
0551     fesettings->min_delay_ms = 350;
0552     fesettings->step_size = 166666*2;
0553     fesettings->max_drift = (166666*2)+1;
0554     return 0;
0555 }
0556 
0557 static void sp887x_release(struct dvb_frontend* fe)
0558 {
0559     struct sp887x_state* state = fe->demodulator_priv;
0560     kfree(state);
0561 }
0562 
0563 static const struct dvb_frontend_ops sp887x_ops;
0564 
0565 struct dvb_frontend* sp887x_attach(const struct sp887x_config* config,
0566                    struct i2c_adapter* i2c)
0567 {
0568     struct sp887x_state* state = NULL;
0569 
0570     /* allocate memory for the internal state */
0571     state = kzalloc(sizeof(struct sp887x_state), GFP_KERNEL);
0572     if (state == NULL) goto error;
0573 
0574     /* setup the state */
0575     state->config = config;
0576     state->i2c = i2c;
0577     state->initialised = 0;
0578 
0579     /* check if the demod is there */
0580     if (sp887x_readreg(state, 0x0200) < 0) goto error;
0581 
0582     /* create dvb_frontend */
0583     memcpy(&state->frontend.ops, &sp887x_ops, sizeof(struct dvb_frontend_ops));
0584     state->frontend.demodulator_priv = state;
0585     return &state->frontend;
0586 
0587 error:
0588     kfree(state);
0589     return NULL;
0590 }
0591 
0592 static const struct dvb_frontend_ops sp887x_ops = {
0593     .delsys = { SYS_DVBT },
0594     .info = {
0595         .name = "Spase SP887x DVB-T",
0596         .frequency_min_hz =  50500 * kHz,
0597         .frequency_max_hz = 858000 * kHz,
0598         .frequency_stepsize_hz = 166666,
0599         .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
0600             FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
0601             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
0602             FE_CAN_RECOVER
0603     },
0604 
0605     .release = sp887x_release,
0606 
0607     .init = sp887x_init,
0608     .sleep = sp887x_sleep,
0609     .i2c_gate_ctrl = sp887x_i2c_gate_ctrl,
0610 
0611     .set_frontend = sp887x_setup_frontend_parameters,
0612     .get_tune_settings = sp887x_get_tune_settings,
0613 
0614     .read_status = sp887x_read_status,
0615     .read_ber = sp887x_read_ber,
0616     .read_signal_strength = sp887x_read_signal_strength,
0617     .read_snr = sp887x_read_snr,
0618     .read_ucblocks = sp887x_read_ucblocks,
0619 };
0620 
0621 module_param(debug, int, 0644);
0622 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
0623 
0624 MODULE_DESCRIPTION("Spase sp887x DVB-T demodulator driver");
0625 MODULE_LICENSE("GPL");
0626 
0627 EXPORT_SYMBOL(sp887x_attach);
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