media/dvb-frontends/si2165_priv.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Driver for Silicon Labs SI2165 DVB-C/-T Demodulator
0004  *
0005  * Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org>
0006  */
0007
0008 #ifndef _DVB_SI2165_PRIV
0009 #define _DVB_SI2165_PRIV
0010
0011 #define SI2165_FIRMWARE_REV_D "dvb-demod-si2165.fw"
0012
0013 struct si2165_config {
0014     /* i2c addr
0015      * possible values: 0x64,0x65,0x66,0x67
0016      */
0017     u8 i2c_addr;
0018
0019     /* external clock or XTAL */
0020     u8 chip_mode;
0021
0022     /* frequency of external clock or xtal in Hz
0023      * possible values: 4000000, 16000000, 20000000, 240000000, 27000000
0024      */
0025     u32 ref_freq_hz;
0026
0027     /* invert the spectrum */
0028     bool inversion;
0029 };
0030
0031 #define STATISTICS_PERIOD_PKT_COUNT 30000u
0032 #define STATISTICS_PERIOD_BIT_COUNT (STATISTICS_PERIOD_PKT_COUNT * 204 * 8)
0033
0034 #define REG_CHIP_MODE           0x0000
0035 #define REG_CHIP_REVCODE        0x0023
0036 #define REV_CHIP_TYPE           0x0118
0037 #define REG_CHIP_INIT           0x0050
0038 #define REG_INIT_DONE           0x0054
0039 #define REG_START_INIT          0x0096
0040 #define REG_PLL_DIVL            0x00a0
0041 #define REG_RST_ALL         0x00c0
0042 #define REG_LOCK_TIMEOUT        0x00c4
0043 #define REG_AUTO_RESET          0x00cb
0044 #define REG_OVERSAMP            0x00e4
0045 #define REG_IF_FREQ_SHIFT       0x00e8
0046 #define REG_DVB_STANDARD        0x00ec
0047 #define REG_DSP_CLOCK           0x0104
0048 #define REG_ADC_RI8         0x0123
0049 #define REG_ADC_RI1         0x012a
0050 #define REG_ADC_RI2         0x012b
0051 #define REG_ADC_RI3         0x012c
0052 #define REG_ADC_RI4         0x012d
0053 #define REG_ADC_RI5         0x012e
0054 #define REG_ADC_RI6         0x012f
0055 #define REG_AGC_CRESTF_DBX8     0x0150
0056 #define REG_AGC_UNFREEZE_THR        0x015b
0057 #define REG_AGC2_MIN            0x016e
0058 #define REG_AGC2_KACQ           0x016c
0059 #define REG_AGC2_KLOC           0x016d
0060 #define REG_AGC2_OUTPUT         0x0170
0061 #define REG_AGC2_CLKDIV         0x0171
0062 #define REG_AGC_IF_TRI          0x018b
0063 #define REG_AGC_IF_SLR          0x0190
0064 #define REG_AAF_CRESTF_DBX8     0x01a0
0065 #define REG_ACI_CRESTF_DBX8     0x01c8
0066 #define REG_SWEEP_STEP          0x0232
0067 #define REG_KP_LOCK         0x023a
0068 #define REG_UNKNOWN_24C         0x024c
0069 #define REG_CENTRAL_TAP         0x0261
0070 #define REG_C_N             0x026c
0071 #define REG_EQ_AUTO_CONTROL     0x0278
0072 #define REG_UNKNOWN_27C         0x027c
0073 #define REG_START_SYNCHRO       0x02e0
0074 #define REG_REQ_CONSTELLATION       0x02f4
0075 #define REG_T_BANDWIDTH         0x0308
0076 #define REG_FREQ_SYNC_RANGE     0x030c
0077 #define REG_IMPULSIVE_NOISE_REM     0x031c
0078 #define REG_WDOG_AND_BOOT       0x0341
0079 #define REG_PATCH_VERSION       0x0344
0080 #define REG_ADDR_JUMP           0x0348
0081 #define REG_UNKNOWN_350         0x0350
0082 #define REG_EN_RST_ERROR        0x035c
0083 #define REG_DCOM_CONTROL_BYTE       0x0364
0084 #define REG_DCOM_ADDR           0x0368
0085 #define REG_DCOM_DATA           0x036c
0086 #define REG_RST_CRC         0x0379
0087 #define REG_GP_REG0_LSB         0x0384
0088 #define REG_GP_REG0_MSB         0x0387
0089 #define REG_CRC             0x037a
0090 #define REG_CHECK_SIGNAL        0x03a8
0091 #define REG_CBER_RST            0x0424
0092 #define REG_CBER_BIT            0x0428
0093 #define REG_CBER_ERR            0x0430
0094 #define REG_CBER_AVAIL          0x0434
0095 #define REG_PS_LOCK         0x0440
0096 #define REG_UNCOR_CNT           0x0468
0097 #define REG_BER_RST         0x046c
0098 #define REG_BER_PKT         0x0470
0099 #define REG_BER_BIT         0x0478
0100 #define REG_BER_AVAIL           0x047c
0101 #define REG_FEC_LOCK            0x04e0
0102 #define REG_TS_DATA_MODE        0x04e4
0103 #define REG_TS_CLK_MODE         0x04e5
0104 #define REG_TS_TRI          0x04ef
0105 #define REG_TS_SLR          0x04f4
0106 #define REG_RSSI_ENABLE         0x0641
0107 #define REG_RSSI_PAD_CTRL       0x0646
0108 #define REG_TS_PARALLEL_MODE        0x08f8
0109
0110 #endif /* _DVB_SI2165_PRIV */