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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for
0004  *    Samsung S5H1420 and
0005  *    PnpNetwork PN1010 QPSK Demodulator
0006  *
0007  * Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
0008  * Copyright (C) 2005-8 Patrick Boettcher <pb@linuxtv.org>
0009  */
0010 
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/init.h>
0014 #include <linux/string.h>
0015 #include <linux/slab.h>
0016 #include <linux/delay.h>
0017 #include <linux/jiffies.h>
0018 #include <asm/div64.h>
0019 
0020 #include <linux/i2c.h>
0021 
0022 
0023 #include <media/dvb_frontend.h>
0024 #include "s5h1420.h"
0025 #include "s5h1420_priv.h"
0026 
0027 #define TONE_FREQ 22000
0028 
0029 struct s5h1420_state {
0030     struct i2c_adapter* i2c;
0031     const struct s5h1420_config* config;
0032 
0033     struct dvb_frontend frontend;
0034     struct i2c_adapter tuner_i2c_adapter;
0035 
0036     u8 CON_1_val;
0037 
0038     u8 postlocked:1;
0039     u32 fclk;
0040     u32 tunedfreq;
0041     enum fe_code_rate fec_inner;
0042     u32 symbol_rate;
0043 
0044     /* FIXME: ugly workaround for flexcop's incapable i2c-controller
0045      * it does not support repeated-start, workaround: write addr-1
0046      * and then read
0047      */
0048     u8 shadow[256];
0049 };
0050 
0051 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
0052 static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
0053                      struct dvb_frontend_tune_settings* fesettings);
0054 
0055 
0056 static int debug;
0057 module_param(debug, int, 0644);
0058 MODULE_PARM_DESC(debug, "enable debugging");
0059 
0060 #define dprintk(x...) do { \
0061     if (debug) \
0062         printk(KERN_DEBUG "S5H1420: " x); \
0063 } while (0)
0064 
0065 static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg)
0066 {
0067     int ret;
0068     u8 b[2];
0069     struct i2c_msg msg[] = {
0070         { .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 },
0071         { .addr = state->config->demod_address, .flags = 0, .buf = &reg, .len = 1 },
0072         { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 },
0073     };
0074 
0075     b[0] = (reg - 1) & 0xff;
0076     b[1] = state->shadow[(reg - 1) & 0xff];
0077 
0078     if (state->config->repeated_start_workaround) {
0079         ret = i2c_transfer(state->i2c, msg, 3);
0080         if (ret != 3)
0081             return ret;
0082     } else {
0083         ret = i2c_transfer(state->i2c, &msg[1], 1);
0084         if (ret != 1)
0085             return ret;
0086         ret = i2c_transfer(state->i2c, &msg[2], 1);
0087         if (ret != 1)
0088             return ret;
0089     }
0090 
0091     /* dprintk("rd(%02x): %02x %02x\n", state->config->demod_address, reg, b[0]); */
0092 
0093     return b[0];
0094 }
0095 
0096 static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
0097 {
0098     u8 buf[] = { reg, data };
0099     struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
0100     int err;
0101 
0102     /* dprintk("wr(%02x): %02x %02x\n", state->config->demod_address, reg, data); */
0103     err = i2c_transfer(state->i2c, &msg, 1);
0104     if (err != 1) {
0105         dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
0106         return -EREMOTEIO;
0107     }
0108     state->shadow[reg] = data;
0109 
0110     return 0;
0111 }
0112 
0113 static int s5h1420_set_voltage(struct dvb_frontend *fe,
0114                    enum fe_sec_voltage voltage)
0115 {
0116     struct s5h1420_state* state = fe->demodulator_priv;
0117 
0118     dprintk("enter %s\n", __func__);
0119 
0120     switch(voltage) {
0121     case SEC_VOLTAGE_13:
0122         s5h1420_writereg(state, 0x3c,
0123                  (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);
0124         break;
0125 
0126     case SEC_VOLTAGE_18:
0127         s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03);
0128         break;
0129 
0130     case SEC_VOLTAGE_OFF:
0131         s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd);
0132         break;
0133     }
0134 
0135     dprintk("leave %s\n", __func__);
0136     return 0;
0137 }
0138 
0139 static int s5h1420_set_tone(struct dvb_frontend *fe,
0140                 enum fe_sec_tone_mode tone)
0141 {
0142     struct s5h1420_state* state = fe->demodulator_priv;
0143 
0144     dprintk("enter %s\n", __func__);
0145     switch(tone) {
0146     case SEC_TONE_ON:
0147         s5h1420_writereg(state, 0x3b,
0148                  (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);
0149         break;
0150 
0151     case SEC_TONE_OFF:
0152         s5h1420_writereg(state, 0x3b,
0153                  (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
0154         break;
0155     }
0156     dprintk("leave %s\n", __func__);
0157 
0158     return 0;
0159 }
0160 
0161 static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
0162                     struct dvb_diseqc_master_cmd* cmd)
0163 {
0164     struct s5h1420_state* state = fe->demodulator_priv;
0165     u8 val;
0166     int i;
0167     unsigned long timeout;
0168     int result = 0;
0169 
0170     dprintk("enter %s\n", __func__);
0171     if (cmd->msg_len > sizeof(cmd->msg))
0172         return -EINVAL;
0173 
0174     /* setup for DISEQC */
0175     val = s5h1420_readreg(state, 0x3b);
0176     s5h1420_writereg(state, 0x3b, 0x02);
0177     msleep(15);
0178 
0179     /* write the DISEQC command bytes */
0180     for(i=0; i< cmd->msg_len; i++) {
0181         s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
0182     }
0183 
0184     /* kick off transmission */
0185     s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
0186                       ((cmd->msg_len-1) << 4) | 0x08);
0187 
0188     /* wait for transmission to complete */
0189     timeout = jiffies + ((100*HZ) / 1000);
0190     while(time_before(jiffies, timeout)) {
0191         if (!(s5h1420_readreg(state, 0x3b) & 0x08))
0192             break;
0193 
0194         msleep(5);
0195     }
0196     if (time_after(jiffies, timeout))
0197         result = -ETIMEDOUT;
0198 
0199     /* restore original settings */
0200     s5h1420_writereg(state, 0x3b, val);
0201     msleep(15);
0202     dprintk("leave %s\n", __func__);
0203     return result;
0204 }
0205 
0206 static int s5h1420_recv_slave_reply (struct dvb_frontend* fe,
0207                      struct dvb_diseqc_slave_reply* reply)
0208 {
0209     struct s5h1420_state* state = fe->demodulator_priv;
0210     u8 val;
0211     int i;
0212     int length;
0213     unsigned long timeout;
0214     int result = 0;
0215 
0216     /* setup for DISEQC receive */
0217     val = s5h1420_readreg(state, 0x3b);
0218     s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive mode? */
0219     msleep(15);
0220 
0221     /* wait for reception to complete */
0222     timeout = jiffies + ((reply->timeout*HZ) / 1000);
0223     while(time_before(jiffies, timeout)) {
0224         if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */
0225             break;
0226 
0227         msleep(5);
0228     }
0229     if (time_after(jiffies, timeout)) {
0230         result = -ETIMEDOUT;
0231         goto exit;
0232     }
0233 
0234     /* check error flag - FIXME: not sure what this does - docs do not describe
0235      * beyond "error flag for diseqc receive data :( */
0236     if (s5h1420_readreg(state, 0x49)) {
0237         result = -EIO;
0238         goto exit;
0239     }
0240 
0241     /* check length */
0242     length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4;
0243     if (length > sizeof(reply->msg)) {
0244         result = -EOVERFLOW;
0245         goto exit;
0246     }
0247     reply->msg_len = length;
0248 
0249     /* extract data */
0250     for(i=0; i< length; i++) {
0251         reply->msg[i] = s5h1420_readreg(state, 0x3d + i);
0252     }
0253 
0254 exit:
0255     /* restore original settings */
0256     s5h1420_writereg(state, 0x3b, val);
0257     msleep(15);
0258     return result;
0259 }
0260 
0261 static int s5h1420_send_burst(struct dvb_frontend *fe,
0262                   enum fe_sec_mini_cmd minicmd)
0263 {
0264     struct s5h1420_state* state = fe->demodulator_priv;
0265     u8 val;
0266     int result = 0;
0267     unsigned long timeout;
0268 
0269     /* setup for tone burst */
0270     val = s5h1420_readreg(state, 0x3b);
0271     s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01);
0272 
0273     /* set value for B position if requested */
0274     if (minicmd == SEC_MINI_B) {
0275         s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04);
0276     }
0277     msleep(15);
0278 
0279     /* start transmission */
0280     s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
0281 
0282     /* wait for transmission to complete */
0283     timeout = jiffies + ((100*HZ) / 1000);
0284     while(time_before(jiffies, timeout)) {
0285         if (!(s5h1420_readreg(state, 0x3b) & 0x08))
0286             break;
0287 
0288         msleep(5);
0289     }
0290     if (time_after(jiffies, timeout))
0291         result = -ETIMEDOUT;
0292 
0293     /* restore original settings */
0294     s5h1420_writereg(state, 0x3b, val);
0295     msleep(15);
0296     return result;
0297 }
0298 
0299 static enum fe_status s5h1420_get_status_bits(struct s5h1420_state *state)
0300 {
0301     u8 val;
0302     enum fe_status status = 0;
0303 
0304     val = s5h1420_readreg(state, 0x14);
0305     if (val & 0x02)
0306         status |=  FE_HAS_SIGNAL;
0307     if (val & 0x01)
0308         status |=  FE_HAS_CARRIER;
0309     val = s5h1420_readreg(state, 0x36);
0310     if (val & 0x01)
0311         status |=  FE_HAS_VITERBI;
0312     if (val & 0x20)
0313         status |=  FE_HAS_SYNC;
0314     if (status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI|FE_HAS_SYNC))
0315         status |=  FE_HAS_LOCK;
0316 
0317     return status;
0318 }
0319 
0320 static int s5h1420_read_status(struct dvb_frontend *fe,
0321                    enum fe_status *status)
0322 {
0323     struct s5h1420_state* state = fe->demodulator_priv;
0324     u8 val;
0325 
0326     dprintk("enter %s\n", __func__);
0327 
0328     if (status == NULL)
0329         return -EINVAL;
0330 
0331     /* determine lock state */
0332     *status = s5h1420_get_status_bits(state);
0333 
0334     /* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
0335     the inversion, wait a bit and check again */
0336     if (*status == (FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI)) {
0337         val = s5h1420_readreg(state, Vit10);
0338         if ((val & 0x07) == 0x03) {
0339             if (val & 0x08)
0340                 s5h1420_writereg(state, Vit09, 0x13);
0341             else
0342                 s5h1420_writereg(state, Vit09, 0x1b);
0343 
0344             /* wait a bit then update lock status */
0345             mdelay(200);
0346             *status = s5h1420_get_status_bits(state);
0347         }
0348     }
0349 
0350     /* perform post lock setup */
0351     if ((*status & FE_HAS_LOCK) && !state->postlocked) {
0352 
0353         /* calculate the data rate */
0354         u32 tmp = s5h1420_getsymbolrate(state);
0355         switch (s5h1420_readreg(state, Vit10) & 0x07) {
0356         case 0: tmp = (tmp * 2 * 1) / 2; break;
0357         case 1: tmp = (tmp * 2 * 2) / 3; break;
0358         case 2: tmp = (tmp * 2 * 3) / 4; break;
0359         case 3: tmp = (tmp * 2 * 5) / 6; break;
0360         case 4: tmp = (tmp * 2 * 6) / 7; break;
0361         case 5: tmp = (tmp * 2 * 7) / 8; break;
0362         }
0363 
0364         if (tmp == 0) {
0365             printk(KERN_ERR "s5h1420: avoided division by 0\n");
0366             tmp = 1;
0367         }
0368         tmp = state->fclk / tmp;
0369 
0370 
0371         /* set the MPEG_CLK_INTL for the calculated data rate */
0372         if (tmp < 2)
0373             val = 0x00;
0374         else if (tmp < 5)
0375             val = 0x01;
0376         else if (tmp < 9)
0377             val = 0x02;
0378         else if (tmp < 13)
0379             val = 0x03;
0380         else if (tmp < 17)
0381             val = 0x04;
0382         else if (tmp < 25)
0383             val = 0x05;
0384         else if (tmp < 33)
0385             val = 0x06;
0386         else
0387             val = 0x07;
0388         dprintk("for MPEG_CLK_INTL %d %x\n", tmp, val);
0389 
0390         s5h1420_writereg(state, FEC01, 0x18);
0391         s5h1420_writereg(state, FEC01, 0x10);
0392         s5h1420_writereg(state, FEC01, val);
0393 
0394         /* Enable "MPEG_Out" */
0395         val = s5h1420_readreg(state, Mpeg02);
0396         s5h1420_writereg(state, Mpeg02, val | (1 << 6));
0397 
0398         /* kicker disable */
0399         val = s5h1420_readreg(state, QPSK01) & 0x7f;
0400         s5h1420_writereg(state, QPSK01, val);
0401 
0402         /* DC freeze TODO it was never activated by default or it can stay activated */
0403 
0404         if (s5h1420_getsymbolrate(state) >= 20000000) {
0405             s5h1420_writereg(state, Loop04, 0x8a);
0406             s5h1420_writereg(state, Loop05, 0x6a);
0407         } else {
0408             s5h1420_writereg(state, Loop04, 0x58);
0409             s5h1420_writereg(state, Loop05, 0x27);
0410         }
0411 
0412         /* post-lock processing has been done! */
0413         state->postlocked = 1;
0414     }
0415 
0416     dprintk("leave %s\n", __func__);
0417 
0418     return 0;
0419 }
0420 
0421 static int s5h1420_read_ber(struct dvb_frontend* fe, u32* ber)
0422 {
0423     struct s5h1420_state* state = fe->demodulator_priv;
0424 
0425     s5h1420_writereg(state, 0x46, 0x1d);
0426     mdelay(25);
0427 
0428     *ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
0429 
0430     return 0;
0431 }
0432 
0433 static int s5h1420_read_signal_strength(struct dvb_frontend* fe, u16* strength)
0434 {
0435     struct s5h1420_state* state = fe->demodulator_priv;
0436 
0437     u8 val = s5h1420_readreg(state, 0x15);
0438 
0439     *strength =  (u16) ((val << 8) | val);
0440 
0441     return 0;
0442 }
0443 
0444 static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
0445 {
0446     struct s5h1420_state* state = fe->demodulator_priv;
0447 
0448     s5h1420_writereg(state, 0x46, 0x1f);
0449     mdelay(25);
0450 
0451     *ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
0452 
0453     return 0;
0454 }
0455 
0456 static void s5h1420_reset(struct s5h1420_state* state)
0457 {
0458     dprintk("%s\n", __func__);
0459     s5h1420_writereg (state, 0x01, 0x08);
0460     s5h1420_writereg (state, 0x01, 0x00);
0461     udelay(10);
0462 }
0463 
0464 static void s5h1420_setsymbolrate(struct s5h1420_state* state,
0465                   struct dtv_frontend_properties *p)
0466 {
0467     u8 v;
0468     u64 val;
0469 
0470     dprintk("enter %s\n", __func__);
0471 
0472     val = ((u64) p->symbol_rate / 1000ULL) * (1ULL<<24);
0473     if (p->symbol_rate < 29000000)
0474         val *= 2;
0475     do_div(val, (state->fclk / 1000));
0476 
0477     dprintk("symbol rate register: %06llx\n", (unsigned long long)val);
0478 
0479     v = s5h1420_readreg(state, Loop01);
0480     s5h1420_writereg(state, Loop01, v & 0x7f);
0481     s5h1420_writereg(state, Tnco01, val >> 16);
0482     s5h1420_writereg(state, Tnco02, val >> 8);
0483     s5h1420_writereg(state, Tnco03, val & 0xff);
0484     s5h1420_writereg(state, Loop01,  v | 0x80);
0485     dprintk("leave %s\n", __func__);
0486 }
0487 
0488 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
0489 {
0490     return state->symbol_rate;
0491 }
0492 
0493 static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
0494 {
0495     int val;
0496     u8 v;
0497 
0498     dprintk("enter %s\n", __func__);
0499 
0500     /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
0501      * divide fclk by 1000000 to get the correct value. */
0502     val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
0503 
0504     dprintk("phase rotator/freqoffset: %d %06x\n", freqoffset, val);
0505 
0506     v = s5h1420_readreg(state, Loop01);
0507     s5h1420_writereg(state, Loop01, v & 0xbf);
0508     s5h1420_writereg(state, Pnco01, val >> 16);
0509     s5h1420_writereg(state, Pnco02, val >> 8);
0510     s5h1420_writereg(state, Pnco03, val & 0xff);
0511     s5h1420_writereg(state, Loop01, v | 0x40);
0512     dprintk("leave %s\n", __func__);
0513 }
0514 
0515 static int s5h1420_getfreqoffset(struct s5h1420_state* state)
0516 {
0517     int val;
0518 
0519     s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
0520     val  = s5h1420_readreg(state, 0x0e) << 16;
0521     val |= s5h1420_readreg(state, 0x0f) << 8;
0522     val |= s5h1420_readreg(state, 0x10);
0523     s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
0524 
0525     if (val & 0x800000)
0526         val |= 0xff000000;
0527 
0528     /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
0529      * divide fclk by 1000000 to get the correct value. */
0530     val = (((-val) * (state->fclk/1000000)) / (1<<24));
0531 
0532     return val;
0533 }
0534 
0535 static void s5h1420_setfec_inversion(struct s5h1420_state* state,
0536                      struct dtv_frontend_properties *p)
0537 {
0538     u8 inversion = 0;
0539     u8 vit08, vit09;
0540 
0541     dprintk("enter %s\n", __func__);
0542 
0543     if (p->inversion == INVERSION_OFF)
0544         inversion = state->config->invert ? 0x08 : 0;
0545     else if (p->inversion == INVERSION_ON)
0546         inversion = state->config->invert ? 0 : 0x08;
0547 
0548     if ((p->fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
0549         vit08 = 0x3f;
0550         vit09 = 0;
0551     } else {
0552         switch (p->fec_inner) {
0553         case FEC_1_2:
0554             vit08 = 0x01;
0555             vit09 = 0x10;
0556             break;
0557 
0558         case FEC_2_3:
0559             vit08 = 0x02;
0560             vit09 = 0x11;
0561             break;
0562 
0563         case FEC_3_4:
0564             vit08 = 0x04;
0565             vit09 = 0x12;
0566             break;
0567 
0568         case FEC_5_6:
0569             vit08 = 0x08;
0570             vit09 = 0x13;
0571             break;
0572 
0573         case FEC_6_7:
0574             vit08 = 0x10;
0575             vit09 = 0x14;
0576             break;
0577 
0578         case FEC_7_8:
0579             vit08 = 0x20;
0580             vit09 = 0x15;
0581             break;
0582 
0583         default:
0584             return;
0585         }
0586     }
0587     vit09 |= inversion;
0588     dprintk("fec: %02x %02x\n", vit08, vit09);
0589     s5h1420_writereg(state, Vit08, vit08);
0590     s5h1420_writereg(state, Vit09, vit09);
0591     dprintk("leave %s\n", __func__);
0592 }
0593 
0594 static enum fe_code_rate s5h1420_getfec(struct s5h1420_state *state)
0595 {
0596     switch(s5h1420_readreg(state, 0x32) & 0x07) {
0597     case 0:
0598         return FEC_1_2;
0599 
0600     case 1:
0601         return FEC_2_3;
0602 
0603     case 2:
0604         return FEC_3_4;
0605 
0606     case 3:
0607         return FEC_5_6;
0608 
0609     case 4:
0610         return FEC_6_7;
0611 
0612     case 5:
0613         return FEC_7_8;
0614     }
0615 
0616     return FEC_NONE;
0617 }
0618 
0619 static enum fe_spectral_inversion
0620 s5h1420_getinversion(struct s5h1420_state *state)
0621 {
0622     if (s5h1420_readreg(state, 0x32) & 0x08)
0623         return INVERSION_ON;
0624 
0625     return INVERSION_OFF;
0626 }
0627 
0628 static int s5h1420_set_frontend(struct dvb_frontend *fe)
0629 {
0630     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0631     struct s5h1420_state* state = fe->demodulator_priv;
0632     int frequency_delta;
0633     struct dvb_frontend_tune_settings fesettings;
0634 
0635     dprintk("enter %s\n", __func__);
0636 
0637     /* check if we should do a fast-tune */
0638     s5h1420_get_tune_settings(fe, &fesettings);
0639     frequency_delta = p->frequency - state->tunedfreq;
0640     if ((frequency_delta > -fesettings.max_drift) &&
0641             (frequency_delta < fesettings.max_drift) &&
0642             (frequency_delta != 0) &&
0643             (state->fec_inner == p->fec_inner) &&
0644             (state->symbol_rate == p->symbol_rate)) {
0645 
0646         if (fe->ops.tuner_ops.set_params) {
0647             fe->ops.tuner_ops.set_params(fe);
0648             if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
0649         }
0650         if (fe->ops.tuner_ops.get_frequency) {
0651             u32 tmp;
0652             fe->ops.tuner_ops.get_frequency(fe, &tmp);
0653             if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
0654             s5h1420_setfreqoffset(state, p->frequency - tmp);
0655         } else {
0656             s5h1420_setfreqoffset(state, 0);
0657         }
0658         dprintk("simple tune\n");
0659         return 0;
0660     }
0661     dprintk("tuning demod\n");
0662 
0663     /* first of all, software reset */
0664     s5h1420_reset(state);
0665 
0666     /* set s5h1420 fclk PLL according to desired symbol rate */
0667     if (p->symbol_rate > 33000000)
0668         state->fclk = 80000000;
0669     else if (p->symbol_rate > 28500000)
0670         state->fclk = 59000000;
0671     else if (p->symbol_rate > 25000000)
0672         state->fclk = 86000000;
0673     else if (p->symbol_rate > 1900000)
0674         state->fclk = 88000000;
0675     else
0676         state->fclk = 44000000;
0677 
0678     dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
0679     s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
0680     s5h1420_writereg(state, PLL02, 0x40);
0681     s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
0682 
0683     /* TODO DC offset removal, config parameter ? */
0684     if (p->symbol_rate > 29000000)
0685         s5h1420_writereg(state, QPSK01, 0xae | 0x10);
0686     else
0687         s5h1420_writereg(state, QPSK01, 0xac | 0x10);
0688 
0689     /* set misc registers */
0690     s5h1420_writereg(state, CON_1, 0x00);
0691     s5h1420_writereg(state, QPSK02, 0x00);
0692     s5h1420_writereg(state, Pre01, 0xb0);
0693 
0694     s5h1420_writereg(state, Loop01, 0xF0);
0695     s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
0696     s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
0697     if (p->symbol_rate > 20000000)
0698         s5h1420_writereg(state, Loop04, 0x79);
0699     else
0700         s5h1420_writereg(state, Loop04, 0x58);
0701     s5h1420_writereg(state, Loop05, 0x6b);
0702 
0703     if (p->symbol_rate >= 8000000)
0704         s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
0705     else if (p->symbol_rate >= 4000000)
0706         s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
0707     else
0708         s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
0709 
0710     s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */
0711 
0712     s5h1420_writereg(state, Sync01, 0x33);
0713     s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
0714     s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
0715     s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */
0716 
0717     s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
0718     s5h1420_writereg(state, DiS03, 0x00);
0719     s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */
0720 
0721     /* set tuner PLL */
0722     if (fe->ops.tuner_ops.set_params) {
0723         fe->ops.tuner_ops.set_params(fe);
0724         if (fe->ops.i2c_gate_ctrl)
0725             fe->ops.i2c_gate_ctrl(fe, 0);
0726         s5h1420_setfreqoffset(state, 0);
0727     }
0728 
0729     /* set the reset of the parameters */
0730     s5h1420_setsymbolrate(state, p);
0731     s5h1420_setfec_inversion(state, p);
0732 
0733     /* start QPSK */
0734     s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
0735 
0736     state->fec_inner = p->fec_inner;
0737     state->symbol_rate = p->symbol_rate;
0738     state->postlocked = 0;
0739     state->tunedfreq = p->frequency;
0740 
0741     dprintk("leave %s\n", __func__);
0742     return 0;
0743 }
0744 
0745 static int s5h1420_get_frontend(struct dvb_frontend* fe,
0746                 struct dtv_frontend_properties *p)
0747 {
0748     struct s5h1420_state* state = fe->demodulator_priv;
0749 
0750     p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state);
0751     p->inversion = s5h1420_getinversion(state);
0752     p->symbol_rate = s5h1420_getsymbolrate(state);
0753     p->fec_inner = s5h1420_getfec(state);
0754 
0755     return 0;
0756 }
0757 
0758 static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
0759                      struct dvb_frontend_tune_settings* fesettings)
0760 {
0761     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0762     if (p->symbol_rate > 20000000) {
0763         fesettings->min_delay_ms = 50;
0764         fesettings->step_size = 2000;
0765         fesettings->max_drift = 8000;
0766     } else if (p->symbol_rate > 12000000) {
0767         fesettings->min_delay_ms = 100;
0768         fesettings->step_size = 1500;
0769         fesettings->max_drift = 9000;
0770     } else if (p->symbol_rate > 8000000) {
0771         fesettings->min_delay_ms = 100;
0772         fesettings->step_size = 1000;
0773         fesettings->max_drift = 8000;
0774     } else if (p->symbol_rate > 4000000) {
0775         fesettings->min_delay_ms = 100;
0776         fesettings->step_size = 500;
0777         fesettings->max_drift = 7000;
0778     } else if (p->symbol_rate > 2000000) {
0779         fesettings->min_delay_ms = 200;
0780         fesettings->step_size = (p->symbol_rate / 8000);
0781         fesettings->max_drift = 14 * fesettings->step_size;
0782     } else {
0783         fesettings->min_delay_ms = 200;
0784         fesettings->step_size = (p->symbol_rate / 8000);
0785         fesettings->max_drift = 18 * fesettings->step_size;
0786     }
0787 
0788     return 0;
0789 }
0790 
0791 static int s5h1420_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
0792 {
0793     struct s5h1420_state* state = fe->demodulator_priv;
0794 
0795     if (enable)
0796         return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
0797     else
0798         return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
0799 }
0800 
0801 static int s5h1420_init (struct dvb_frontend* fe)
0802 {
0803     struct s5h1420_state* state = fe->demodulator_priv;
0804 
0805     /* disable power down and do reset */
0806     state->CON_1_val = state->config->serial_mpeg << 4;
0807     s5h1420_writereg(state, 0x02, state->CON_1_val);
0808     msleep(10);
0809     s5h1420_reset(state);
0810 
0811     return 0;
0812 }
0813 
0814 static int s5h1420_sleep(struct dvb_frontend* fe)
0815 {
0816     struct s5h1420_state* state = fe->demodulator_priv;
0817     state->CON_1_val = 0x12;
0818     return s5h1420_writereg(state, 0x02, state->CON_1_val);
0819 }
0820 
0821 static void s5h1420_release(struct dvb_frontend* fe)
0822 {
0823     struct s5h1420_state* state = fe->demodulator_priv;
0824     i2c_del_adapter(&state->tuner_i2c_adapter);
0825     kfree(state);
0826 }
0827 
0828 static u32 s5h1420_tuner_i2c_func(struct i2c_adapter *adapter)
0829 {
0830     return I2C_FUNC_I2C;
0831 }
0832 
0833 static int s5h1420_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
0834 {
0835     struct s5h1420_state *state = i2c_get_adapdata(i2c_adap);
0836     struct i2c_msg m[3];
0837     u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition */
0838 
0839     if (1 + num > ARRAY_SIZE(m)) {
0840         printk(KERN_WARNING
0841                "%s: i2c xfer: num=%d is too big!\n",
0842                KBUILD_MODNAME, num);
0843         return  -EOPNOTSUPP;
0844     }
0845 
0846     memset(m, 0, sizeof(struct i2c_msg) * (1 + num));
0847 
0848     m[0].addr = state->config->demod_address;
0849     m[0].buf  = tx_open;
0850     m[0].len  = 2;
0851 
0852     memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);
0853 
0854     return i2c_transfer(state->i2c, m, 1 + num) == 1 + num ? num : -EIO;
0855 }
0856 
0857 static const struct i2c_algorithm s5h1420_tuner_i2c_algo = {
0858     .master_xfer   = s5h1420_tuner_i2c_tuner_xfer,
0859     .functionality = s5h1420_tuner_i2c_func,
0860 };
0861 
0862 struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe)
0863 {
0864     struct s5h1420_state *state = fe->demodulator_priv;
0865     return &state->tuner_i2c_adapter;
0866 }
0867 EXPORT_SYMBOL(s5h1420_get_tuner_i2c_adapter);
0868 
0869 static const struct dvb_frontend_ops s5h1420_ops;
0870 
0871 struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
0872                     struct i2c_adapter *i2c)
0873 {
0874     /* allocate memory for the internal state */
0875     struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
0876     u8 i;
0877 
0878     if (state == NULL)
0879         goto error;
0880 
0881     /* setup the state */
0882     state->config = config;
0883     state->i2c = i2c;
0884     state->postlocked = 0;
0885     state->fclk = 88000000;
0886     state->tunedfreq = 0;
0887     state->fec_inner = FEC_NONE;
0888     state->symbol_rate = 0;
0889 
0890     /* check if the demod is there + identify it */
0891     i = s5h1420_readreg(state, ID01);
0892     if (i != 0x03)
0893         goto error;
0894 
0895     memset(state->shadow, 0xff, sizeof(state->shadow));
0896 
0897     for (i = 0; i < 0x50; i++)
0898         state->shadow[i] = s5h1420_readreg(state, i);
0899 
0900     /* create dvb_frontend */
0901     memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
0902     state->frontend.demodulator_priv = state;
0903 
0904     /* create tuner i2c adapter */
0905     strscpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus",
0906         sizeof(state->tuner_i2c_adapter.name));
0907     state->tuner_i2c_adapter.algo      = &s5h1420_tuner_i2c_algo;
0908     state->tuner_i2c_adapter.algo_data = NULL;
0909     i2c_set_adapdata(&state->tuner_i2c_adapter, state);
0910     if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
0911         printk(KERN_ERR "S5H1420/PN1010: tuner i2c bus could not be initialized\n");
0912         goto error;
0913     }
0914 
0915     return &state->frontend;
0916 
0917 error:
0918     kfree(state);
0919     return NULL;
0920 }
0921 EXPORT_SYMBOL(s5h1420_attach);
0922 
0923 static const struct dvb_frontend_ops s5h1420_ops = {
0924     .delsys = { SYS_DVBS },
0925     .info = {
0926         .name     = "Samsung S5H1420/PnpNetwork PN1010 DVB-S",
0927         .frequency_min_hz    =  950 * MHz,
0928         .frequency_max_hz    = 2150 * MHz,
0929         .frequency_stepsize_hz = 125 * kHz,
0930         .frequency_tolerance_hz  = 29500 * kHz,
0931         .symbol_rate_min  = 1000000,
0932         .symbol_rate_max  = 45000000,
0933         /*  .symbol_rate_tolerance  = ???,*/
0934         .caps = FE_CAN_INVERSION_AUTO |
0935         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
0936         FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
0937         FE_CAN_QPSK
0938     },
0939 
0940     .release = s5h1420_release,
0941 
0942     .init = s5h1420_init,
0943     .sleep = s5h1420_sleep,
0944     .i2c_gate_ctrl = s5h1420_i2c_gate_ctrl,
0945 
0946     .set_frontend = s5h1420_set_frontend,
0947     .get_frontend = s5h1420_get_frontend,
0948     .get_tune_settings = s5h1420_get_tune_settings,
0949 
0950     .read_status = s5h1420_read_status,
0951     .read_ber = s5h1420_read_ber,
0952     .read_signal_strength = s5h1420_read_signal_strength,
0953     .read_ucblocks = s5h1420_read_ucblocks,
0954 
0955     .diseqc_send_master_cmd = s5h1420_send_master_cmd,
0956     .diseqc_recv_slave_reply = s5h1420_recv_slave_reply,
0957     .diseqc_send_burst = s5h1420_send_burst,
0958     .set_tone = s5h1420_set_tone,
0959     .set_voltage = s5h1420_set_voltage,
0960 };
0961 
0962 MODULE_DESCRIPTION("Samsung S5H1420/PnpNetwork PN1010 DVB-S Demodulator driver");
0963 MODULE_AUTHOR("Andrew de Quincey, Patrick Boettcher");
0964 MODULE_LICENSE("GPL");
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