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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003     Samsung S5H1411 VSB/QAM demodulator driver
0004 
0005     Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
0006 
0007 
0008 */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/init.h>
0012 #include <linux/module.h>
0013 #include <linux/string.h>
0014 #include <linux/slab.h>
0015 #include <linux/delay.h>
0016 #include <media/dvb_frontend.h>
0017 #include "s5h1411.h"
0018 
0019 struct s5h1411_state {
0020 
0021     struct i2c_adapter *i2c;
0022 
0023     /* configuration settings */
0024     const struct s5h1411_config *config;
0025 
0026     struct dvb_frontend frontend;
0027 
0028     enum fe_modulation current_modulation;
0029     unsigned int first_tune:1;
0030 
0031     u32 current_frequency;
0032     int if_freq;
0033 
0034     u8 inversion;
0035 };
0036 
0037 static int debug;
0038 
0039 #define dprintk(arg...) do {    \
0040     if (debug)      \
0041         printk(arg);    \
0042 } while (0)
0043 
0044 /* Register values to initialise the demod, defaults to VSB */
0045 static struct init_tab {
0046     u8  addr;
0047     u8  reg;
0048     u16 data;
0049 } init_tab[] = {
0050     { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
0051     { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
0052     { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
0053     { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
0054     { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
0055     { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
0056     { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
0057     { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
0058     { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
0059     { S5H1411_I2C_TOP_ADDR, 0x28, 0x070f, },
0060     { S5H1411_I2C_TOP_ADDR, 0x29, 0x2820, },
0061     { S5H1411_I2C_TOP_ADDR, 0x2a, 0x102e, },
0062     { S5H1411_I2C_TOP_ADDR, 0x2b, 0x0220, },
0063     { S5H1411_I2C_TOP_ADDR, 0x2e, 0x0d0e, },
0064     { S5H1411_I2C_TOP_ADDR, 0x2f, 0x1013, },
0065     { S5H1411_I2C_TOP_ADDR, 0x31, 0x171b, },
0066     { S5H1411_I2C_TOP_ADDR, 0x32, 0x0e0f, },
0067     { S5H1411_I2C_TOP_ADDR, 0x33, 0x0f10, },
0068     { S5H1411_I2C_TOP_ADDR, 0x34, 0x170e, },
0069     { S5H1411_I2C_TOP_ADDR, 0x35, 0x4b10, },
0070     { S5H1411_I2C_TOP_ADDR, 0x36, 0x0f17, },
0071     { S5H1411_I2C_TOP_ADDR, 0x3c, 0x1577, },
0072     { S5H1411_I2C_TOP_ADDR, 0x3d, 0x081a, },
0073     { S5H1411_I2C_TOP_ADDR, 0x3e, 0x77ee, },
0074     { S5H1411_I2C_TOP_ADDR, 0x40, 0x1e09, },
0075     { S5H1411_I2C_TOP_ADDR, 0x41, 0x0f0c, },
0076     { S5H1411_I2C_TOP_ADDR, 0x42, 0x1f10, },
0077     { S5H1411_I2C_TOP_ADDR, 0x4d, 0x0509, },
0078     { S5H1411_I2C_TOP_ADDR, 0x4e, 0x0a00, },
0079     { S5H1411_I2C_TOP_ADDR, 0x50, 0x0000, },
0080     { S5H1411_I2C_TOP_ADDR, 0x5b, 0x0000, },
0081     { S5H1411_I2C_TOP_ADDR, 0x5c, 0x0008, },
0082     { S5H1411_I2C_TOP_ADDR, 0x57, 0x1101, },
0083     { S5H1411_I2C_TOP_ADDR, 0x65, 0x007c, },
0084     { S5H1411_I2C_TOP_ADDR, 0x68, 0x0512, },
0085     { S5H1411_I2C_TOP_ADDR, 0x69, 0x0258, },
0086     { S5H1411_I2C_TOP_ADDR, 0x70, 0x0004, },
0087     { S5H1411_I2C_TOP_ADDR, 0x71, 0x0007, },
0088     { S5H1411_I2C_TOP_ADDR, 0x76, 0x00a9, },
0089     { S5H1411_I2C_TOP_ADDR, 0x78, 0x3141, },
0090     { S5H1411_I2C_TOP_ADDR, 0x7a, 0x3141, },
0091     { S5H1411_I2C_TOP_ADDR, 0xb3, 0x8003, },
0092     { S5H1411_I2C_TOP_ADDR, 0xb5, 0xa6bb, },
0093     { S5H1411_I2C_TOP_ADDR, 0xb6, 0x0609, },
0094     { S5H1411_I2C_TOP_ADDR, 0xb7, 0x2f06, },
0095     { S5H1411_I2C_TOP_ADDR, 0xb8, 0x003f, },
0096     { S5H1411_I2C_TOP_ADDR, 0xb9, 0x2700, },
0097     { S5H1411_I2C_TOP_ADDR, 0xba, 0xfac8, },
0098     { S5H1411_I2C_TOP_ADDR, 0xbe, 0x1003, },
0099     { S5H1411_I2C_TOP_ADDR, 0xbf, 0x103f, },
0100     { S5H1411_I2C_TOP_ADDR, 0xce, 0x2000, },
0101     { S5H1411_I2C_TOP_ADDR, 0xcf, 0x0800, },
0102     { S5H1411_I2C_TOP_ADDR, 0xd0, 0x0800, },
0103     { S5H1411_I2C_TOP_ADDR, 0xd1, 0x0400, },
0104     { S5H1411_I2C_TOP_ADDR, 0xd2, 0x0800, },
0105     { S5H1411_I2C_TOP_ADDR, 0xd3, 0x2000, },
0106     { S5H1411_I2C_TOP_ADDR, 0xd4, 0x3000, },
0107     { S5H1411_I2C_TOP_ADDR, 0xdb, 0x4a9b, },
0108     { S5H1411_I2C_TOP_ADDR, 0xdc, 0x1000, },
0109     { S5H1411_I2C_TOP_ADDR, 0xde, 0x0001, },
0110     { S5H1411_I2C_TOP_ADDR, 0xdf, 0x0000, },
0111     { S5H1411_I2C_TOP_ADDR, 0xe3, 0x0301, },
0112     { S5H1411_I2C_QAM_ADDR, 0xf3, 0x0000, },
0113     { S5H1411_I2C_QAM_ADDR, 0xf3, 0x0001, },
0114     { S5H1411_I2C_QAM_ADDR, 0x08, 0x0600, },
0115     { S5H1411_I2C_QAM_ADDR, 0x18, 0x4201, },
0116     { S5H1411_I2C_QAM_ADDR, 0x1e, 0x6476, },
0117     { S5H1411_I2C_QAM_ADDR, 0x21, 0x0830, },
0118     { S5H1411_I2C_QAM_ADDR, 0x0c, 0x5679, },
0119     { S5H1411_I2C_QAM_ADDR, 0x0d, 0x579b, },
0120     { S5H1411_I2C_QAM_ADDR, 0x24, 0x0102, },
0121     { S5H1411_I2C_QAM_ADDR, 0x31, 0x7488, },
0122     { S5H1411_I2C_QAM_ADDR, 0x32, 0x0a08, },
0123     { S5H1411_I2C_QAM_ADDR, 0x3d, 0x8689, },
0124     { S5H1411_I2C_QAM_ADDR, 0x49, 0x0048, },
0125     { S5H1411_I2C_QAM_ADDR, 0x57, 0x2012, },
0126     { S5H1411_I2C_QAM_ADDR, 0x5d, 0x7676, },
0127     { S5H1411_I2C_QAM_ADDR, 0x04, 0x0400, },
0128     { S5H1411_I2C_QAM_ADDR, 0x58, 0x00c0, },
0129     { S5H1411_I2C_QAM_ADDR, 0x5b, 0x0100, },
0130 };
0131 
0132 /* VSB SNR lookup table */
0133 static struct vsb_snr_tab {
0134     u16 val;
0135     u16 data;
0136 } vsb_snr_tab[] = {
0137     {  0x39f, 300, },
0138     {  0x39b, 295, },
0139     {  0x397, 290, },
0140     {  0x394, 285, },
0141     {  0x38f, 280, },
0142     {  0x38b, 275, },
0143     {  0x387, 270, },
0144     {  0x382, 265, },
0145     {  0x37d, 260, },
0146     {  0x377, 255, },
0147     {  0x370, 250, },
0148     {  0x36a, 245, },
0149     {  0x364, 240, },
0150     {  0x35b, 235, },
0151     {  0x353, 230, },
0152     {  0x349, 225, },
0153     {  0x340, 220, },
0154     {  0x337, 215, },
0155     {  0x327, 210, },
0156     {  0x31b, 205, },
0157     {  0x310, 200, },
0158     {  0x302, 195, },
0159     {  0x2f3, 190, },
0160     {  0x2e4, 185, },
0161     {  0x2d7, 180, },
0162     {  0x2cd, 175, },
0163     {  0x2bb, 170, },
0164     {  0x2a9, 165, },
0165     {  0x29e, 160, },
0166     {  0x284, 155, },
0167     {  0x27a, 150, },
0168     {  0x260, 145, },
0169     {  0x23a, 140, },
0170     {  0x224, 135, },
0171     {  0x213, 130, },
0172     {  0x204, 125, },
0173     {  0x1fe, 120, },
0174     {      0,   0, },
0175 };
0176 
0177 /* QAM64 SNR lookup table */
0178 static struct qam64_snr_tab {
0179     u16 val;
0180     u16 data;
0181 } qam64_snr_tab[] = {
0182     {  0x0001,   0, },
0183     {  0x0af0, 300, },
0184     {  0x0d80, 290, },
0185     {  0x10a0, 280, },
0186     {  0x14b5, 270, },
0187     {  0x1590, 268, },
0188     {  0x1680, 266, },
0189     {  0x17b0, 264, },
0190     {  0x18c0, 262, },
0191     {  0x19b0, 260, },
0192     {  0x1ad0, 258, },
0193     {  0x1d00, 256, },
0194     {  0x1da0, 254, },
0195     {  0x1ef0, 252, },
0196     {  0x2050, 250, },
0197     {  0x20f0, 249, },
0198     {  0x21d0, 248, },
0199     {  0x22b0, 247, },
0200     {  0x23a0, 246, },
0201     {  0x2470, 245, },
0202     {  0x24f0, 244, },
0203     {  0x25a0, 243, },
0204     {  0x26c0, 242, },
0205     {  0x27b0, 241, },
0206     {  0x28d0, 240, },
0207     {  0x29b0, 239, },
0208     {  0x2ad0, 238, },
0209     {  0x2ba0, 237, },
0210     {  0x2c80, 236, },
0211     {  0x2d20, 235, },
0212     {  0x2e00, 234, },
0213     {  0x2f10, 233, },
0214     {  0x3050, 232, },
0215     {  0x3190, 231, },
0216     {  0x3300, 230, },
0217     {  0x3340, 229, },
0218     {  0x3200, 228, },
0219     {  0x3550, 227, },
0220     {  0x3610, 226, },
0221     {  0x3600, 225, },
0222     {  0x3700, 224, },
0223     {  0x3800, 223, },
0224     {  0x3920, 222, },
0225     {  0x3a20, 221, },
0226     {  0x3b30, 220, },
0227     {  0x3d00, 219, },
0228     {  0x3e00, 218, },
0229     {  0x4000, 217, },
0230     {  0x4100, 216, },
0231     {  0x4300, 215, },
0232     {  0x4400, 214, },
0233     {  0x4600, 213, },
0234     {  0x4700, 212, },
0235     {  0x4800, 211, },
0236     {  0x4a00, 210, },
0237     {  0x4b00, 209, },
0238     {  0x4d00, 208, },
0239     {  0x4f00, 207, },
0240     {  0x5050, 206, },
0241     {  0x5200, 205, },
0242     {  0x53c0, 204, },
0243     {  0x5450, 203, },
0244     {  0x5650, 202, },
0245     {  0x5820, 201, },
0246     {  0x6000, 200, },
0247     {  0xffff,   0, },
0248 };
0249 
0250 /* QAM256 SNR lookup table */
0251 static struct qam256_snr_tab {
0252     u16 val;
0253     u16 data;
0254 } qam256_snr_tab[] = {
0255     {  0x0001,   0, },
0256     {  0x0970, 400, },
0257     {  0x0a90, 390, },
0258     {  0x0b90, 380, },
0259     {  0x0d90, 370, },
0260     {  0x0ff0, 360, },
0261     {  0x1240, 350, },
0262     {  0x1345, 348, },
0263     {  0x13c0, 346, },
0264     {  0x14c0, 344, },
0265     {  0x1500, 342, },
0266     {  0x1610, 340, },
0267     {  0x1700, 338, },
0268     {  0x1800, 336, },
0269     {  0x18b0, 334, },
0270     {  0x1900, 332, },
0271     {  0x1ab0, 330, },
0272     {  0x1bc0, 328, },
0273     {  0x1cb0, 326, },
0274     {  0x1db0, 324, },
0275     {  0x1eb0, 322, },
0276     {  0x2030, 320, },
0277     {  0x2200, 318, },
0278     {  0x2280, 316, },
0279     {  0x2410, 314, },
0280     {  0x25b0, 312, },
0281     {  0x27a0, 310, },
0282     {  0x2840, 308, },
0283     {  0x29d0, 306, },
0284     {  0x2b10, 304, },
0285     {  0x2d30, 302, },
0286     {  0x2f20, 300, },
0287     {  0x30c0, 298, },
0288     {  0x3260, 297, },
0289     {  0x32c0, 296, },
0290     {  0x3300, 295, },
0291     {  0x33b0, 294, },
0292     {  0x34b0, 293, },
0293     {  0x35a0, 292, },
0294     {  0x3650, 291, },
0295     {  0x3800, 290, },
0296     {  0x3900, 289, },
0297     {  0x3a50, 288, },
0298     {  0x3b30, 287, },
0299     {  0x3cb0, 286, },
0300     {  0x3e20, 285, },
0301     {  0x3fa0, 284, },
0302     {  0x40a0, 283, },
0303     {  0x41c0, 282, },
0304     {  0x42f0, 281, },
0305     {  0x44a0, 280, },
0306     {  0x4600, 279, },
0307     {  0x47b0, 278, },
0308     {  0x4900, 277, },
0309     {  0x4a00, 276, },
0310     {  0x4ba0, 275, },
0311     {  0x4d00, 274, },
0312     {  0x4f00, 273, },
0313     {  0x5000, 272, },
0314     {  0x51f0, 272, },
0315     {  0x53a0, 270, },
0316     {  0x5520, 269, },
0317     {  0x5700, 268, },
0318     {  0x5800, 267, },
0319     {  0x5a00, 266, },
0320     {  0x5c00, 265, },
0321     {  0x5d00, 264, },
0322     {  0x5f00, 263, },
0323     {  0x6000, 262, },
0324     {  0x6200, 261, },
0325     {  0x6400, 260, },
0326     {  0xffff,   0, },
0327 };
0328 
0329 /* 8 bit registers, 16 bit values */
0330 static int s5h1411_writereg(struct s5h1411_state *state,
0331     u8 addr, u8 reg, u16 data)
0332 {
0333     int ret;
0334     u8 buf[] = { reg, data >> 8,  data & 0xff };
0335 
0336     struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 3 };
0337 
0338     ret = i2c_transfer(state->i2c, &msg, 1);
0339 
0340     if (ret != 1)
0341         printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, ret == %i)\n",
0342                __func__, addr, reg, data, ret);
0343 
0344     return (ret != 1) ? -1 : 0;
0345 }
0346 
0347 static u16 s5h1411_readreg(struct s5h1411_state *state, u8 addr, u8 reg)
0348 {
0349     int ret;
0350     u8 b0[] = { reg };
0351     u8 b1[] = { 0, 0 };
0352 
0353     struct i2c_msg msg[] = {
0354         { .addr = addr, .flags = 0, .buf = b0, .len = 1 },
0355         { .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 2 } };
0356 
0357     ret = i2c_transfer(state->i2c, msg, 2);
0358 
0359     if (ret != 2)
0360         printk(KERN_ERR "%s: readreg error (ret == %i)\n",
0361             __func__, ret);
0362     return (b1[0] << 8) | b1[1];
0363 }
0364 
0365 static int s5h1411_softreset(struct dvb_frontend *fe)
0366 {
0367     struct s5h1411_state *state = fe->demodulator_priv;
0368 
0369     dprintk("%s()\n", __func__);
0370 
0371     s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 0);
0372     s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 1);
0373     return 0;
0374 }
0375 
0376 static int s5h1411_set_if_freq(struct dvb_frontend *fe, int KHz)
0377 {
0378     struct s5h1411_state *state = fe->demodulator_priv;
0379 
0380     dprintk("%s(%d KHz)\n", __func__, KHz);
0381 
0382     switch (KHz) {
0383     case 3250:
0384         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x10d5);
0385         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x5342);
0386         s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x10d9);
0387         break;
0388     case 3500:
0389         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1225);
0390         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x1e96);
0391         s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1225);
0392         break;
0393     case 4000:
0394         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x14bc);
0395         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0xb53e);
0396         s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x14bd);
0397         break;
0398     default:
0399         dprintk("%s(%d KHz) Invalid, defaulting to 5380\n",
0400             __func__, KHz);
0401         fallthrough;
0402     case 5380:
0403     case 44000:
0404         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1be4);
0405         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x3655);
0406         s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1be4);
0407         break;
0408     }
0409 
0410     state->if_freq = KHz;
0411 
0412     return 0;
0413 }
0414 
0415 static int s5h1411_set_mpeg_timing(struct dvb_frontend *fe, int mode)
0416 {
0417     struct s5h1411_state *state = fe->demodulator_priv;
0418     u16 val;
0419 
0420     dprintk("%s(%d)\n", __func__, mode);
0421 
0422     val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbe) & 0xcfff;
0423     switch (mode) {
0424     case S5H1411_MPEGTIMING_CONTINUOUS_INVERTING_CLOCK:
0425         val |= 0x0000;
0426         break;
0427     case S5H1411_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK:
0428         dprintk("%s(%d) Mode1 or Defaulting\n", __func__, mode);
0429         val |= 0x1000;
0430         break;
0431     case S5H1411_MPEGTIMING_NONCONTINUOUS_INVERTING_CLOCK:
0432         val |= 0x2000;
0433         break;
0434     case S5H1411_MPEGTIMING_NONCONTINUOUS_NONINVERTING_CLOCK:
0435         val |= 0x3000;
0436         break;
0437     default:
0438         return -EINVAL;
0439     }
0440 
0441     /* Configure MPEG Signal Timing charactistics */
0442     return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbe, val);
0443 }
0444 
0445 static int s5h1411_set_spectralinversion(struct dvb_frontend *fe, int inversion)
0446 {
0447     struct s5h1411_state *state = fe->demodulator_priv;
0448     u16 val;
0449 
0450     dprintk("%s(%d)\n", __func__, inversion);
0451     val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x24) & ~0x1000;
0452 
0453     if (inversion == 1)
0454         val |= 0x1000; /* Inverted */
0455 
0456     state->inversion = inversion;
0457     return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x24, val);
0458 }
0459 
0460 static int s5h1411_set_serialmode(struct dvb_frontend *fe, int serial)
0461 {
0462     struct s5h1411_state *state = fe->demodulator_priv;
0463     u16 val;
0464 
0465     dprintk("%s(%d)\n", __func__, serial);
0466     val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbd) & ~0x100;
0467 
0468     if (serial == 1)
0469         val |= 0x100;
0470 
0471     return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, val);
0472 }
0473 
0474 static int s5h1411_enable_modulation(struct dvb_frontend *fe,
0475                      enum fe_modulation m)
0476 {
0477     struct s5h1411_state *state = fe->demodulator_priv;
0478 
0479     dprintk("%s(0x%08x)\n", __func__, m);
0480 
0481     if ((state->first_tune == 0) && (m == state->current_modulation)) {
0482         dprintk("%s() Already at desired modulation.  Skipping...\n",
0483             __func__);
0484         return 0;
0485     }
0486 
0487     switch (m) {
0488     case VSB_8:
0489         dprintk("%s() VSB_8\n", __func__);
0490         s5h1411_set_if_freq(fe, state->config->vsb_if);
0491         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x71);
0492         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x00);
0493         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0xf1);
0494         break;
0495     case QAM_64:
0496     case QAM_256:
0497     case QAM_AUTO:
0498         dprintk("%s() QAM_AUTO (64/256)\n", __func__);
0499         s5h1411_set_if_freq(fe, state->config->qam_if);
0500         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x0171);
0501         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x0001);
0502         s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x16, 0x1101);
0503         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0x00f0);
0504         break;
0505     default:
0506         dprintk("%s() Invalid modulation\n", __func__);
0507         return -EINVAL;
0508     }
0509 
0510     state->current_modulation = m;
0511     state->first_tune = 0;
0512     s5h1411_softreset(fe);
0513 
0514     return 0;
0515 }
0516 
0517 static int s5h1411_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
0518 {
0519     struct s5h1411_state *state = fe->demodulator_priv;
0520 
0521     dprintk("%s(%d)\n", __func__, enable);
0522 
0523     if (enable)
0524         return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
0525     else
0526         return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 0);
0527 }
0528 
0529 static int s5h1411_set_gpio(struct dvb_frontend *fe, int enable)
0530 {
0531     struct s5h1411_state *state = fe->demodulator_priv;
0532     u16 val;
0533 
0534     dprintk("%s(%d)\n", __func__, enable);
0535 
0536     val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xe0) & ~0x02;
0537 
0538     if (enable)
0539         return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0,
0540                 val | 0x02);
0541     else
0542         return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, val);
0543 }
0544 
0545 static int s5h1411_set_powerstate(struct dvb_frontend *fe, int enable)
0546 {
0547     struct s5h1411_state *state = fe->demodulator_priv;
0548 
0549     dprintk("%s(%d)\n", __func__, enable);
0550 
0551     if (enable)
0552         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 1);
0553     else {
0554         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 0);
0555         s5h1411_softreset(fe);
0556     }
0557 
0558     return 0;
0559 }
0560 
0561 static int s5h1411_sleep(struct dvb_frontend *fe)
0562 {
0563     return s5h1411_set_powerstate(fe, 1);
0564 }
0565 
0566 static int s5h1411_register_reset(struct dvb_frontend *fe)
0567 {
0568     struct s5h1411_state *state = fe->demodulator_priv;
0569 
0570     dprintk("%s()\n", __func__);
0571 
0572     return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf3, 0);
0573 }
0574 
0575 /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
0576 static int s5h1411_set_frontend(struct dvb_frontend *fe)
0577 {
0578     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0579     struct s5h1411_state *state = fe->demodulator_priv;
0580 
0581     dprintk("%s(frequency=%d)\n", __func__, p->frequency);
0582 
0583     s5h1411_softreset(fe);
0584 
0585     state->current_frequency = p->frequency;
0586 
0587     s5h1411_enable_modulation(fe, p->modulation);
0588 
0589     if (fe->ops.tuner_ops.set_params) {
0590         if (fe->ops.i2c_gate_ctrl)
0591             fe->ops.i2c_gate_ctrl(fe, 1);
0592 
0593         fe->ops.tuner_ops.set_params(fe);
0594 
0595         if (fe->ops.i2c_gate_ctrl)
0596             fe->ops.i2c_gate_ctrl(fe, 0);
0597     }
0598 
0599     /* Issue a reset to the demod so it knows to resync against the
0600        newly tuned frequency */
0601     s5h1411_softreset(fe);
0602 
0603     return 0;
0604 }
0605 
0606 /* Reset the demod hardware and reset all of the configuration registers
0607    to a default state. */
0608 static int s5h1411_init(struct dvb_frontend *fe)
0609 {
0610     struct s5h1411_state *state = fe->demodulator_priv;
0611     int i;
0612 
0613     dprintk("%s()\n", __func__);
0614 
0615     s5h1411_set_powerstate(fe, 0);
0616     s5h1411_register_reset(fe);
0617 
0618     for (i = 0; i < ARRAY_SIZE(init_tab); i++)
0619         s5h1411_writereg(state, init_tab[i].addr,
0620             init_tab[i].reg,
0621             init_tab[i].data);
0622 
0623     /* The datasheet says that after initialisation, VSB is default */
0624     state->current_modulation = VSB_8;
0625 
0626     /* Although the datasheet says it's in VSB, empirical evidence
0627        shows problems getting lock on the first tuning request.  Make
0628        sure we call enable_modulation the first time around */
0629     state->first_tune = 1;
0630 
0631     if (state->config->output_mode == S5H1411_SERIAL_OUTPUT)
0632         /* Serial */
0633         s5h1411_set_serialmode(fe, 1);
0634     else
0635         /* Parallel */
0636         s5h1411_set_serialmode(fe, 0);
0637 
0638     s5h1411_set_spectralinversion(fe, state->config->inversion);
0639     s5h1411_set_if_freq(fe, state->config->vsb_if);
0640     s5h1411_set_gpio(fe, state->config->gpio);
0641     s5h1411_set_mpeg_timing(fe, state->config->mpeg_timing);
0642     s5h1411_softreset(fe);
0643 
0644     /* Note: Leaving the I2C gate closed. */
0645     s5h1411_i2c_gate_ctrl(fe, 0);
0646 
0647     return 0;
0648 }
0649 
0650 static int s5h1411_read_status(struct dvb_frontend *fe, enum fe_status *status)
0651 {
0652     struct s5h1411_state *state = fe->demodulator_priv;
0653     u16 reg;
0654     u32 tuner_status = 0;
0655 
0656     *status = 0;
0657 
0658     /* Register F2 bit 15 = Master Lock, removed */
0659 
0660     switch (state->current_modulation) {
0661     case QAM_64:
0662     case QAM_256:
0663         reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf0);
0664         if (reg & 0x10) /* QAM FEC Lock */
0665             *status |= FE_HAS_SYNC | FE_HAS_LOCK;
0666         if (reg & 0x100) /* QAM EQ Lock */
0667             *status |= FE_HAS_VITERBI | FE_HAS_CARRIER | FE_HAS_SIGNAL;
0668 
0669         break;
0670     case VSB_8:
0671         reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf2);
0672         if (reg & 0x1000) /* FEC Lock */
0673             *status |= FE_HAS_SYNC | FE_HAS_LOCK;
0674         if (reg & 0x2000) /* EQ Lock */
0675             *status |= FE_HAS_VITERBI | FE_HAS_CARRIER | FE_HAS_SIGNAL;
0676 
0677         reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x53);
0678         if (reg & 0x1) /* AFC Lock */
0679             *status |= FE_HAS_SIGNAL;
0680 
0681         break;
0682     default:
0683         return -EINVAL;
0684     }
0685 
0686     switch (state->config->status_mode) {
0687     case S5H1411_DEMODLOCKING:
0688         if (*status & FE_HAS_VITERBI)
0689             *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
0690         break;
0691     case S5H1411_TUNERLOCKING:
0692         /* Get the tuner status */
0693         if (fe->ops.tuner_ops.get_status) {
0694             if (fe->ops.i2c_gate_ctrl)
0695                 fe->ops.i2c_gate_ctrl(fe, 1);
0696 
0697             fe->ops.tuner_ops.get_status(fe, &tuner_status);
0698 
0699             if (fe->ops.i2c_gate_ctrl)
0700                 fe->ops.i2c_gate_ctrl(fe, 0);
0701         }
0702         if (tuner_status)
0703             *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
0704         break;
0705     }
0706 
0707     dprintk("%s() status 0x%08x\n", __func__, *status);
0708 
0709     return 0;
0710 }
0711 
0712 static int s5h1411_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
0713 {
0714     int i, ret = -EINVAL;
0715     dprintk("%s()\n", __func__);
0716 
0717     for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) {
0718         if (v < qam256_snr_tab[i].val) {
0719             *snr = qam256_snr_tab[i].data;
0720             ret = 0;
0721             break;
0722         }
0723     }
0724     return ret;
0725 }
0726 
0727 static int s5h1411_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
0728 {
0729     int i, ret = -EINVAL;
0730     dprintk("%s()\n", __func__);
0731 
0732     for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) {
0733         if (v < qam64_snr_tab[i].val) {
0734             *snr = qam64_snr_tab[i].data;
0735             ret = 0;
0736             break;
0737         }
0738     }
0739     return ret;
0740 }
0741 
0742 static int s5h1411_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
0743 {
0744     int i, ret = -EINVAL;
0745     dprintk("%s()\n", __func__);
0746 
0747     for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) {
0748         if (v > vsb_snr_tab[i].val) {
0749             *snr = vsb_snr_tab[i].data;
0750             ret = 0;
0751             break;
0752         }
0753     }
0754     dprintk("%s() snr=%d\n", __func__, *snr);
0755     return ret;
0756 }
0757 
0758 static int s5h1411_read_snr(struct dvb_frontend *fe, u16 *snr)
0759 {
0760     struct s5h1411_state *state = fe->demodulator_priv;
0761     u16 reg;
0762     dprintk("%s()\n", __func__);
0763 
0764     switch (state->current_modulation) {
0765     case QAM_64:
0766         reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
0767         return s5h1411_qam64_lookup_snr(fe, snr, reg);
0768     case QAM_256:
0769         reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
0770         return s5h1411_qam256_lookup_snr(fe, snr, reg);
0771     case VSB_8:
0772         reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR,
0773             0xf2) & 0x3ff;
0774         return s5h1411_vsb_lookup_snr(fe, snr, reg);
0775     default:
0776         break;
0777     }
0778 
0779     return -EINVAL;
0780 }
0781 
0782 static int s5h1411_read_signal_strength(struct dvb_frontend *fe,
0783     u16 *signal_strength)
0784 {
0785     /* borrowed from lgdt330x.c
0786      *
0787      * Calculate strength from SNR up to 35dB
0788      * Even though the SNR can go higher than 35dB,
0789      * there is some comfort factor in having a range of
0790      * strong signals that can show at 100%
0791      */
0792     u16 snr;
0793     u32 tmp;
0794     int ret = s5h1411_read_snr(fe, &snr);
0795 
0796     *signal_strength = 0;
0797 
0798     if (0 == ret) {
0799         /* The following calculation method was chosen
0800          * purely for the sake of code re-use from the
0801          * other demod drivers that use this method */
0802 
0803         /* Convert from SNR in dB * 10 to 8.24 fixed-point */
0804         tmp = (snr * ((1 << 24) / 10));
0805 
0806         /* Convert from 8.24 fixed-point to
0807          * scale the range 0 - 35*2^24 into 0 - 65535*/
0808         if (tmp >= 8960 * 0x10000)
0809             *signal_strength = 0xffff;
0810         else
0811             *signal_strength = tmp / 8960;
0812     }
0813 
0814     return ret;
0815 }
0816 
0817 static int s5h1411_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
0818 {
0819     struct s5h1411_state *state = fe->demodulator_priv;
0820 
0821     *ucblocks = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xc9);
0822 
0823     return 0;
0824 }
0825 
0826 static int s5h1411_read_ber(struct dvb_frontend *fe, u32 *ber)
0827 {
0828     return s5h1411_read_ucblocks(fe, ber);
0829 }
0830 
0831 static int s5h1411_get_frontend(struct dvb_frontend *fe,
0832                 struct dtv_frontend_properties *p)
0833 {
0834     struct s5h1411_state *state = fe->demodulator_priv;
0835 
0836     p->frequency = state->current_frequency;
0837     p->modulation = state->current_modulation;
0838 
0839     return 0;
0840 }
0841 
0842 static int s5h1411_get_tune_settings(struct dvb_frontend *fe,
0843                      struct dvb_frontend_tune_settings *tune)
0844 {
0845     tune->min_delay_ms = 1000;
0846     return 0;
0847 }
0848 
0849 static void s5h1411_release(struct dvb_frontend *fe)
0850 {
0851     struct s5h1411_state *state = fe->demodulator_priv;
0852     kfree(state);
0853 }
0854 
0855 static const struct dvb_frontend_ops s5h1411_ops;
0856 
0857 struct dvb_frontend *s5h1411_attach(const struct s5h1411_config *config,
0858                     struct i2c_adapter *i2c)
0859 {
0860     struct s5h1411_state *state = NULL;
0861     u16 reg;
0862 
0863     /* allocate memory for the internal state */
0864     state = kzalloc(sizeof(struct s5h1411_state), GFP_KERNEL);
0865     if (state == NULL)
0866         goto error;
0867 
0868     /* setup the state */
0869     state->config = config;
0870     state->i2c = i2c;
0871     state->current_modulation = VSB_8;
0872     state->inversion = state->config->inversion;
0873 
0874     /* check if the demod exists */
0875     reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x05);
0876     if (reg != 0x0066)
0877         goto error;
0878 
0879     /* create dvb_frontend */
0880     memcpy(&state->frontend.ops, &s5h1411_ops,
0881            sizeof(struct dvb_frontend_ops));
0882 
0883     state->frontend.demodulator_priv = state;
0884 
0885     if (s5h1411_init(&state->frontend) != 0) {
0886         printk(KERN_ERR "%s: Failed to initialize correctly\n",
0887             __func__);
0888         goto error;
0889     }
0890 
0891     /* Note: Leaving the I2C gate open here. */
0892     s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
0893 
0894     /* Put the device into low-power mode until first use */
0895     s5h1411_set_powerstate(&state->frontend, 1);
0896 
0897     return &state->frontend;
0898 
0899 error:
0900     kfree(state);
0901     return NULL;
0902 }
0903 EXPORT_SYMBOL(s5h1411_attach);
0904 
0905 static const struct dvb_frontend_ops s5h1411_ops = {
0906     .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
0907     .info = {
0908         .name           = "Samsung S5H1411 QAM/8VSB Frontend",
0909         .frequency_min_hz   =  54 * MHz,
0910         .frequency_max_hz   = 858 * MHz,
0911         .frequency_stepsize_hz  = 62500,
0912         .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
0913     },
0914 
0915     .init                 = s5h1411_init,
0916     .sleep                = s5h1411_sleep,
0917     .i2c_gate_ctrl        = s5h1411_i2c_gate_ctrl,
0918     .set_frontend         = s5h1411_set_frontend,
0919     .get_frontend         = s5h1411_get_frontend,
0920     .get_tune_settings    = s5h1411_get_tune_settings,
0921     .read_status          = s5h1411_read_status,
0922     .read_ber             = s5h1411_read_ber,
0923     .read_signal_strength = s5h1411_read_signal_strength,
0924     .read_snr             = s5h1411_read_snr,
0925     .read_ucblocks        = s5h1411_read_ucblocks,
0926     .release              = s5h1411_release,
0927 };
0928 
0929 module_param(debug, int, 0644);
0930 MODULE_PARM_DESC(debug, "Enable verbose debug messages");
0931 
0932 MODULE_DESCRIPTION("Samsung S5H1411 QAM-B/ATSC Demodulator driver");
0933 MODULE_AUTHOR("Steven Toth");
0934 MODULE_LICENSE("GPL");
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