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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Realtek RTL2832 DVB-T demodulator driver
0004  *
0005  * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
0006  * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
0007  */
0008 
0009 #include "rtl2832_priv.h"
0010 
0011 #define REG_MASK(b) (BIT(b + 1) - 1)
0012 
0013 static const struct rtl2832_reg_entry registers[] = {
0014     [DVBT_SOFT_RST]     = {0x101,  2, 2},
0015     [DVBT_IIC_REPEAT]   = {0x101,  3, 3},
0016     [DVBT_TR_WAIT_MIN_8K]   = {0x188, 11, 2},
0017     [DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
0018     [DVBT_EN_BK_TRK]    = {0x1a6,  7, 7},
0019     [DVBT_AD_EN_REG]    = {0x008,  7, 7},
0020     [DVBT_AD_EN_REG1]   = {0x008,  6, 6},
0021     [DVBT_EN_BBIN]      = {0x1b1,  0, 0},
0022     [DVBT_MGD_THD0]     = {0x195,  7, 0},
0023     [DVBT_MGD_THD1]     = {0x196,  7, 0},
0024     [DVBT_MGD_THD2]     = {0x197,  7, 0},
0025     [DVBT_MGD_THD3]     = {0x198,  7, 0},
0026     [DVBT_MGD_THD4]     = {0x199,  7, 0},
0027     [DVBT_MGD_THD5]     = {0x19a,  7, 0},
0028     [DVBT_MGD_THD6]     = {0x19b,  7, 0},
0029     [DVBT_MGD_THD7]     = {0x19c,  7, 0},
0030     [DVBT_EN_CACQ_NOTCH]    = {0x161,  4, 4},
0031     [DVBT_AD_AV_REF]    = {0x009,  6, 0},
0032     [DVBT_REG_PI]       = {0x00a,  2, 0},
0033     [DVBT_PIP_ON]       = {0x021,  3, 3},
0034     [DVBT_SCALE1_B92]   = {0x292,  7, 0},
0035     [DVBT_SCALE1_B93]   = {0x293,  7, 0},
0036     [DVBT_SCALE1_BA7]   = {0x2a7,  7, 0},
0037     [DVBT_SCALE1_BA9]   = {0x2a9,  7, 0},
0038     [DVBT_SCALE1_BAA]   = {0x2aa,  7, 0},
0039     [DVBT_SCALE1_BAB]   = {0x2ab,  7, 0},
0040     [DVBT_SCALE1_BAC]   = {0x2ac,  7, 0},
0041     [DVBT_SCALE1_BB0]   = {0x2b0,  7, 0},
0042     [DVBT_SCALE1_BB1]   = {0x2b1,  7, 0},
0043     [DVBT_KB_P1]        = {0x164,  3, 1},
0044     [DVBT_KB_P2]        = {0x164,  6, 4},
0045     [DVBT_KB_P3]        = {0x165,  2, 0},
0046     [DVBT_OPT_ADC_IQ]   = {0x006,  5, 4},
0047     [DVBT_AD_AVI]       = {0x009,  1, 0},
0048     [DVBT_AD_AVQ]       = {0x009,  3, 2},
0049     [DVBT_K1_CR_STEP12] = {0x2ad,  9, 4},
0050     [DVBT_TRK_KS_P2]    = {0x16f,  2, 0},
0051     [DVBT_TRK_KS_I2]    = {0x170,  5, 3},
0052     [DVBT_TR_THD_SET2]  = {0x172,  3, 0},
0053     [DVBT_TRK_KC_P2]    = {0x173,  5, 3},
0054     [DVBT_TRK_KC_I2]    = {0x175,  2, 0},
0055     [DVBT_CR_THD_SET2]  = {0x176,  7, 6},
0056     [DVBT_PSET_IFFREQ]  = {0x119, 21, 0},
0057     [DVBT_SPEC_INV]     = {0x115,  0, 0},
0058     [DVBT_RSAMP_RATIO]  = {0x19f, 27, 2},
0059     [DVBT_CFREQ_OFF_RATIO]  = {0x19d, 23, 4},
0060     [DVBT_FSM_STAGE]    = {0x351,  6, 3},
0061     [DVBT_RX_CONSTEL]   = {0x33c,  3, 2},
0062     [DVBT_RX_HIER]      = {0x33c,  6, 4},
0063     [DVBT_RX_C_RATE_LP] = {0x33d,  2, 0},
0064     [DVBT_RX_C_RATE_HP] = {0x33d,  5, 3},
0065     [DVBT_GI_IDX]       = {0x351,  1, 0},
0066     [DVBT_FFT_MODE_IDX] = {0x351,  2, 2},
0067     [DVBT_RSD_BER_EST]  = {0x34e, 15, 0},
0068     [DVBT_CE_EST_EVM]   = {0x40c, 15, 0},
0069     [DVBT_RF_AGC_VAL]   = {0x35b, 13, 0},
0070     [DVBT_IF_AGC_VAL]   = {0x359, 13, 0},
0071     [DVBT_DAGC_VAL]     = {0x305,  7, 0},
0072     [DVBT_SFREQ_OFF]    = {0x318, 13, 0},
0073     [DVBT_CFREQ_OFF]    = {0x35f, 17, 0},
0074     [DVBT_POLAR_RF_AGC] = {0x00e,  1, 1},
0075     [DVBT_POLAR_IF_AGC] = {0x00e,  0, 0},
0076     [DVBT_AAGC_HOLD]    = {0x104,  5, 5},
0077     [DVBT_EN_RF_AGC]    = {0x104,  6, 6},
0078     [DVBT_EN_IF_AGC]    = {0x104,  7, 7},
0079     [DVBT_IF_AGC_MIN]   = {0x108,  7, 0},
0080     [DVBT_IF_AGC_MAX]   = {0x109,  7, 0},
0081     [DVBT_RF_AGC_MIN]   = {0x10a,  7, 0},
0082     [DVBT_RF_AGC_MAX]   = {0x10b,  7, 0},
0083     [DVBT_IF_AGC_MAN]   = {0x10c,  6, 6},
0084     [DVBT_IF_AGC_MAN_VAL]   = {0x10c, 13, 0},
0085     [DVBT_RF_AGC_MAN]   = {0x10e,  6, 6},
0086     [DVBT_RF_AGC_MAN_VAL]   = {0x10e, 13, 0},
0087     [DVBT_DAGC_TRG_VAL] = {0x112,  7, 0},
0088     [DVBT_AGC_TARG_VAL_0]   = {0x102,  0, 0},
0089     [DVBT_AGC_TARG_VAL_8_1] = {0x103,  7, 0},
0090     [DVBT_AAGC_LOOP_GAIN]   = {0x1c7,  5, 1},
0091     [DVBT_LOOP_GAIN2_3_0]   = {0x104,  4, 1},
0092     [DVBT_LOOP_GAIN2_4] = {0x105,  7, 7},
0093     [DVBT_LOOP_GAIN3]   = {0x1c8,  4, 0},
0094     [DVBT_VTOP1]        = {0x106,  5, 0},
0095     [DVBT_VTOP2]        = {0x1c9,  5, 0},
0096     [DVBT_VTOP3]        = {0x1ca,  5, 0},
0097     [DVBT_KRF1]     = {0x1cb,  7, 0},
0098     [DVBT_KRF2]     = {0x107,  7, 0},
0099     [DVBT_KRF3]     = {0x1cd,  7, 0},
0100     [DVBT_KRF4]     = {0x1ce,  7, 0},
0101     [DVBT_EN_GI_PGA]    = {0x1e5,  0, 0},
0102     [DVBT_THD_LOCK_UP]  = {0x1d9,  8, 0},
0103     [DVBT_THD_LOCK_DW]  = {0x1db,  8, 0},
0104     [DVBT_THD_UP1]      = {0x1dd,  7, 0},
0105     [DVBT_THD_DW1]      = {0x1de,  7, 0},
0106     [DVBT_INTER_CNT_LEN]    = {0x1d8,  3, 0},
0107     [DVBT_GI_PGA_STATE] = {0x1e6,  3, 3},
0108     [DVBT_EN_AGC_PGA]   = {0x1d7,  0, 0},
0109     [DVBT_CKOUTPAR]     = {0x17b,  5, 5},
0110     [DVBT_CKOUT_PWR]    = {0x17b,  6, 6},
0111     [DVBT_SYNC_DUR]     = {0x17b,  7, 7},
0112     [DVBT_ERR_DUR]      = {0x17c,  0, 0},
0113     [DVBT_SYNC_LVL]     = {0x17c,  1, 1},
0114     [DVBT_ERR_LVL]      = {0x17c,  2, 2},
0115     [DVBT_VAL_LVL]      = {0x17c,  3, 3},
0116     [DVBT_SERIAL]       = {0x17c,  4, 4},
0117     [DVBT_SER_LSB]      = {0x17c,  5, 5},
0118     [DVBT_CDIV_PH0]     = {0x17d,  3, 0},
0119     [DVBT_CDIV_PH1]     = {0x17d,  7, 4},
0120     [DVBT_MPEG_IO_OPT_2_2]  = {0x006,  7, 7},
0121     [DVBT_MPEG_IO_OPT_1_0]  = {0x007,  7, 6},
0122     [DVBT_CKOUTPAR_PIP] = {0x0b7,  4, 4},
0123     [DVBT_CKOUT_PWR_PIP]    = {0x0b7,  3, 3},
0124     [DVBT_SYNC_LVL_PIP] = {0x0b7,  2, 2},
0125     [DVBT_ERR_LVL_PIP]  = {0x0b7,  1, 1},
0126     [DVBT_VAL_LVL_PIP]  = {0x0b7,  0, 0},
0127     [DVBT_CKOUTPAR_PID] = {0x0b9,  4, 4},
0128     [DVBT_CKOUT_PWR_PID]    = {0x0b9,  3, 3},
0129     [DVBT_SYNC_LVL_PID] = {0x0b9,  2, 2},
0130     [DVBT_ERR_LVL_PID]  = {0x0b9,  1, 1},
0131     [DVBT_VAL_LVL_PID]  = {0x0b9,  0, 0},
0132     [DVBT_SM_PASS]      = {0x193, 11, 0},
0133     [DVBT_AD7_SETTING]  = {0x011, 15, 0},
0134     [DVBT_RSSI_R]       = {0x301,  6, 0},
0135     [DVBT_ACI_DET_IND]  = {0x312,  0, 0},
0136     [DVBT_REG_MON]      = {0x00d,  1, 0},
0137     [DVBT_REG_MONSEL]   = {0x00d,  2, 2},
0138     [DVBT_REG_GPE]      = {0x00d,  7, 7},
0139     [DVBT_REG_GPO]      = {0x010,  0, 0},
0140     [DVBT_REG_4MSEL]    = {0x013,  0, 0},
0141 };
0142 
0143 static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
0144 {
0145     struct i2c_client *client = dev->client;
0146     int ret, i;
0147     u16 reg_start_addr;
0148     u8 msb, lsb, reading[4], len;
0149     u32 reading_tmp, mask;
0150 
0151     reg_start_addr = registers[reg].start_address;
0152     msb = registers[reg].msb;
0153     lsb = registers[reg].lsb;
0154     len = (msb >> 3) + 1;
0155     mask = REG_MASK(msb - lsb);
0156 
0157     ret = regmap_bulk_read(dev->regmap, reg_start_addr, reading, len);
0158     if (ret)
0159         goto err;
0160 
0161     reading_tmp = 0;
0162     for (i = 0; i < len; i++)
0163         reading_tmp |= reading[i] << ((len - 1 - i) * 8);
0164 
0165     *val = (reading_tmp >> lsb) & mask;
0166 
0167     return 0;
0168 err:
0169     dev_dbg(&client->dev, "failed=%d\n", ret);
0170     return ret;
0171 }
0172 
0173 static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
0174 {
0175     struct i2c_client *client = dev->client;
0176     int ret, i;
0177     u16 reg_start_addr;
0178     u8 msb, lsb, reading[4], writing[4], len;
0179     u32 reading_tmp, writing_tmp, mask;
0180 
0181     reg_start_addr = registers[reg].start_address;
0182     msb = registers[reg].msb;
0183     lsb = registers[reg].lsb;
0184     len = (msb >> 3) + 1;
0185     mask = REG_MASK(msb - lsb);
0186 
0187     ret = regmap_bulk_read(dev->regmap, reg_start_addr, reading, len);
0188     if (ret)
0189         goto err;
0190 
0191     reading_tmp = 0;
0192     for (i = 0; i < len; i++)
0193         reading_tmp |= reading[i] << ((len - 1 - i) * 8);
0194 
0195     writing_tmp = reading_tmp & ~(mask << lsb);
0196     writing_tmp |= ((val & mask) << lsb);
0197 
0198     for (i = 0; i < len; i++)
0199         writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
0200 
0201     ret = regmap_bulk_write(dev->regmap, reg_start_addr, writing, len);
0202     if (ret)
0203         goto err;
0204 
0205     return 0;
0206 err:
0207     dev_dbg(&client->dev, "failed=%d\n", ret);
0208     return ret;
0209 }
0210 
0211 static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
0212 {
0213     struct rtl2832_dev *dev = fe->demodulator_priv;
0214     struct i2c_client *client = dev->client;
0215     int ret;
0216     u64 pset_iffreq;
0217     u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
0218 
0219     /*
0220     * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
0221     *       / CrystalFreqHz)
0222     */
0223     pset_iffreq = if_freq % dev->pdata->clk;
0224     pset_iffreq *= 0x400000;
0225     pset_iffreq = div_u64(pset_iffreq, dev->pdata->clk);
0226     pset_iffreq = -pset_iffreq;
0227     pset_iffreq = pset_iffreq & 0x3fffff;
0228     dev_dbg(&client->dev, "if_frequency=%d pset_iffreq=%08x\n",
0229         if_freq, (unsigned)pset_iffreq);
0230 
0231     ret = rtl2832_wr_demod_reg(dev, DVBT_EN_BBIN, en_bbin);
0232     if (ret)
0233         goto err;
0234 
0235     ret = rtl2832_wr_demod_reg(dev, DVBT_PSET_IFFREQ, pset_iffreq);
0236     if (ret)
0237         goto err;
0238 
0239     return 0;
0240 err:
0241     dev_dbg(&client->dev, "failed=%d\n", ret);
0242     return ret;
0243 }
0244 
0245 static int rtl2832_init(struct dvb_frontend *fe)
0246 {
0247     struct rtl2832_dev *dev = fe->demodulator_priv;
0248     struct i2c_client *client = dev->client;
0249     struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
0250     const struct rtl2832_reg_value *init;
0251     int i, ret, len;
0252     /* initialization values for the demodulator registers */
0253     struct rtl2832_reg_value rtl2832_initial_regs[] = {
0254         {DVBT_AD_EN_REG,        0x1},
0255         {DVBT_AD_EN_REG1,       0x1},
0256         {DVBT_RSD_BER_FAIL_VAL,     0x2800},
0257         {DVBT_MGD_THD0,         0x10},
0258         {DVBT_MGD_THD1,         0x20},
0259         {DVBT_MGD_THD2,         0x20},
0260         {DVBT_MGD_THD3,         0x40},
0261         {DVBT_MGD_THD4,         0x22},
0262         {DVBT_MGD_THD5,         0x32},
0263         {DVBT_MGD_THD6,         0x37},
0264         {DVBT_MGD_THD7,         0x39},
0265         {DVBT_EN_BK_TRK,        0x0},
0266         {DVBT_EN_CACQ_NOTCH,        0x0},
0267         {DVBT_AD_AV_REF,        0x2a},
0268         {DVBT_REG_PI,           0x6},
0269         {DVBT_PIP_ON,           0x0},
0270         {DVBT_CDIV_PH0,         0x8},
0271         {DVBT_CDIV_PH1,         0x8},
0272         {DVBT_SCALE1_B92,       0x4},
0273         {DVBT_SCALE1_B93,       0xb0},
0274         {DVBT_SCALE1_BA7,       0x78},
0275         {DVBT_SCALE1_BA9,       0x28},
0276         {DVBT_SCALE1_BAA,       0x59},
0277         {DVBT_SCALE1_BAB,       0x83},
0278         {DVBT_SCALE1_BAC,       0xd4},
0279         {DVBT_SCALE1_BB0,       0x65},
0280         {DVBT_SCALE1_BB1,       0x43},
0281         {DVBT_KB_P1,            0x1},
0282         {DVBT_KB_P2,            0x4},
0283         {DVBT_KB_P3,            0x7},
0284         {DVBT_K1_CR_STEP12,     0xa},
0285         {DVBT_REG_GPE,          0x1},
0286         {DVBT_SERIAL,           0x0},
0287         {DVBT_CDIV_PH0,         0x9},
0288         {DVBT_CDIV_PH1,         0x9},
0289         {DVBT_MPEG_IO_OPT_2_2,      0x0},
0290         {DVBT_MPEG_IO_OPT_1_0,      0x0},
0291         {DVBT_TRK_KS_P2,        0x4},
0292         {DVBT_TRK_KS_I2,        0x7},
0293         {DVBT_TR_THD_SET2,      0x6},
0294         {DVBT_TRK_KC_I2,        0x5},
0295         {DVBT_CR_THD_SET2,      0x1},
0296     };
0297 
0298     dev_dbg(&client->dev, "\n");
0299 
0300     ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
0301     if (ret)
0302         goto err;
0303 
0304     for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
0305         ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg,
0306             rtl2832_initial_regs[i].value);
0307         if (ret)
0308             goto err;
0309     }
0310 
0311     /* load tuner specific settings */
0312     dev_dbg(&client->dev, "load settings for tuner=%02x\n",
0313         dev->pdata->tuner);
0314     switch (dev->pdata->tuner) {
0315     case RTL2832_TUNER_FC2580:
0316         len = ARRAY_SIZE(rtl2832_tuner_init_fc2580);
0317         init = rtl2832_tuner_init_fc2580;
0318         break;
0319     case RTL2832_TUNER_FC0012:
0320     case RTL2832_TUNER_FC0013:
0321         len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
0322         init = rtl2832_tuner_init_fc0012;
0323         break;
0324     case RTL2832_TUNER_TUA9001:
0325         len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
0326         init = rtl2832_tuner_init_tua9001;
0327         break;
0328     case RTL2832_TUNER_E4000:
0329         len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
0330         init = rtl2832_tuner_init_e4000;
0331         break;
0332     case RTL2832_TUNER_R820T:
0333     case RTL2832_TUNER_R828D:
0334         len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
0335         init = rtl2832_tuner_init_r820t;
0336         break;
0337     case RTL2832_TUNER_SI2157:
0338         len = ARRAY_SIZE(rtl2832_tuner_init_si2157);
0339         init = rtl2832_tuner_init_si2157;
0340         break;
0341     default:
0342         ret = -EINVAL;
0343         goto err;
0344     }
0345 
0346     for (i = 0; i < len; i++) {
0347         ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value);
0348         if (ret)
0349             goto err;
0350     }
0351 
0352     /* init stats here in order signal app which stats are supported */
0353     c->strength.len = 1;
0354     c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0355     c->cnr.len = 1;
0356     c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0357     c->post_bit_error.len = 1;
0358     c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0359     c->post_bit_count.len = 1;
0360     c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0361     dev->sleeping = false;
0362 
0363     return 0;
0364 err:
0365     dev_dbg(&client->dev, "failed=%d\n", ret);
0366     return ret;
0367 }
0368 
0369 static int rtl2832_sleep(struct dvb_frontend *fe)
0370 {
0371     struct rtl2832_dev *dev = fe->demodulator_priv;
0372     struct i2c_client *client = dev->client;
0373     int ret;
0374 
0375     dev_dbg(&client->dev, "\n");
0376 
0377     dev->sleeping = true;
0378     dev->fe_status = 0;
0379 
0380     ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
0381     if (ret)
0382         goto err;
0383 
0384     return 0;
0385 err:
0386     dev_dbg(&client->dev, "failed=%d\n", ret);
0387     return ret;
0388 }
0389 
0390 static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
0391     struct dvb_frontend_tune_settings *s)
0392 {
0393     struct rtl2832_dev *dev = fe->demodulator_priv;
0394     struct i2c_client *client = dev->client;
0395 
0396     dev_dbg(&client->dev, "\n");
0397     s->min_delay_ms = 1000;
0398     s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
0399     s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;
0400     return 0;
0401 }
0402 
0403 static int rtl2832_set_frontend(struct dvb_frontend *fe)
0404 {
0405     struct rtl2832_dev *dev = fe->demodulator_priv;
0406     struct i2c_client *client = dev->client;
0407     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0408     int ret, i, j;
0409     u64 bw_mode, num, num2;
0410     u32 resamp_ratio, cfreq_off_ratio;
0411     static u8 bw_params[3][32] = {
0412     /* 6 MHz bandwidth */
0413         {
0414         0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
0415         0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
0416         0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
0417         0x19, 0xe0,
0418         },
0419 
0420     /*  7 MHz bandwidth */
0421         {
0422         0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
0423         0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
0424         0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
0425         0x19, 0x10,
0426         },
0427 
0428     /*  8 MHz bandwidth */
0429         {
0430         0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
0431         0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
0432         0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
0433         0x19, 0xe0,
0434         },
0435     };
0436 
0437     dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
0438         c->frequency, c->bandwidth_hz, c->inversion);
0439 
0440     /* program tuner */
0441     if (fe->ops.tuner_ops.set_params)
0442         fe->ops.tuner_ops.set_params(fe);
0443 
0444     /* If the frontend has get_if_frequency(), use it */
0445     if (fe->ops.tuner_ops.get_if_frequency) {
0446         u32 if_freq;
0447 
0448         ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
0449         if (ret)
0450             goto err;
0451 
0452         ret = rtl2832_set_if(fe, if_freq);
0453         if (ret)
0454             goto err;
0455     }
0456 
0457     switch (c->bandwidth_hz) {
0458     case 6000000:
0459         i = 0;
0460         bw_mode = 48000000;
0461         break;
0462     case 7000000:
0463         i = 1;
0464         bw_mode = 56000000;
0465         break;
0466     case 8000000:
0467         i = 2;
0468         bw_mode = 64000000;
0469         break;
0470     default:
0471         dev_err(&client->dev, "invalid bandwidth_hz %u\n",
0472             c->bandwidth_hz);
0473         ret = -EINVAL;
0474         goto err;
0475     }
0476 
0477     for (j = 0; j < sizeof(bw_params[0]); j++) {
0478         ret = regmap_bulk_write(dev->regmap,
0479                     0x11c + j, &bw_params[i][j], 1);
0480         if (ret)
0481             goto err;
0482     }
0483 
0484     /* calculate and set resample ratio
0485     * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
0486     *   / ConstWithBandwidthMode)
0487     */
0488     num = dev->pdata->clk * 7ULL;
0489     num *= 0x400000;
0490     num = div_u64(num, bw_mode);
0491     resamp_ratio =  num & 0x3ffffff;
0492     ret = rtl2832_wr_demod_reg(dev, DVBT_RSAMP_RATIO, resamp_ratio);
0493     if (ret)
0494         goto err;
0495 
0496     /* calculate and set cfreq off ratio
0497     * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
0498     *   / (CrystalFreqHz * 7))
0499     */
0500     num = bw_mode << 20;
0501     num2 = dev->pdata->clk * 7ULL;
0502     num = div_u64(num, num2);
0503     num = -num;
0504     cfreq_off_ratio = num & 0xfffff;
0505     ret = rtl2832_wr_demod_reg(dev, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
0506     if (ret)
0507         goto err;
0508 
0509     /* soft reset */
0510     ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
0511     if (ret)
0512         goto err;
0513 
0514     ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
0515     if (ret)
0516         goto err;
0517 
0518     return 0;
0519 err:
0520     dev_dbg(&client->dev, "failed=%d\n", ret);
0521     return ret;
0522 }
0523 
0524 static int rtl2832_get_frontend(struct dvb_frontend *fe,
0525                 struct dtv_frontend_properties *c)
0526 {
0527     struct rtl2832_dev *dev = fe->demodulator_priv;
0528     struct i2c_client *client = dev->client;
0529     int ret;
0530     u8 buf[3];
0531 
0532     if (dev->sleeping)
0533         return 0;
0534 
0535     ret = regmap_bulk_read(dev->regmap, 0x33c, buf, 2);
0536     if (ret)
0537         goto err;
0538 
0539     ret = regmap_bulk_read(dev->regmap, 0x351, &buf[2], 1);
0540     if (ret)
0541         goto err;
0542 
0543     dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
0544 
0545     switch ((buf[0] >> 2) & 3) {
0546     case 0:
0547         c->modulation = QPSK;
0548         break;
0549     case 1:
0550         c->modulation = QAM_16;
0551         break;
0552     case 2:
0553         c->modulation = QAM_64;
0554         break;
0555     }
0556 
0557     switch ((buf[2] >> 2) & 1) {
0558     case 0:
0559         c->transmission_mode = TRANSMISSION_MODE_2K;
0560         break;
0561     case 1:
0562         c->transmission_mode = TRANSMISSION_MODE_8K;
0563     }
0564 
0565     switch ((buf[2] >> 0) & 3) {
0566     case 0:
0567         c->guard_interval = GUARD_INTERVAL_1_32;
0568         break;
0569     case 1:
0570         c->guard_interval = GUARD_INTERVAL_1_16;
0571         break;
0572     case 2:
0573         c->guard_interval = GUARD_INTERVAL_1_8;
0574         break;
0575     case 3:
0576         c->guard_interval = GUARD_INTERVAL_1_4;
0577         break;
0578     }
0579 
0580     switch ((buf[0] >> 4) & 7) {
0581     case 0:
0582         c->hierarchy = HIERARCHY_NONE;
0583         break;
0584     case 1:
0585         c->hierarchy = HIERARCHY_1;
0586         break;
0587     case 2:
0588         c->hierarchy = HIERARCHY_2;
0589         break;
0590     case 3:
0591         c->hierarchy = HIERARCHY_4;
0592         break;
0593     }
0594 
0595     switch ((buf[1] >> 3) & 7) {
0596     case 0:
0597         c->code_rate_HP = FEC_1_2;
0598         break;
0599     case 1:
0600         c->code_rate_HP = FEC_2_3;
0601         break;
0602     case 2:
0603         c->code_rate_HP = FEC_3_4;
0604         break;
0605     case 3:
0606         c->code_rate_HP = FEC_5_6;
0607         break;
0608     case 4:
0609         c->code_rate_HP = FEC_7_8;
0610         break;
0611     }
0612 
0613     switch ((buf[1] >> 0) & 7) {
0614     case 0:
0615         c->code_rate_LP = FEC_1_2;
0616         break;
0617     case 1:
0618         c->code_rate_LP = FEC_2_3;
0619         break;
0620     case 2:
0621         c->code_rate_LP = FEC_3_4;
0622         break;
0623     case 3:
0624         c->code_rate_LP = FEC_5_6;
0625         break;
0626     case 4:
0627         c->code_rate_LP = FEC_7_8;
0628         break;
0629     }
0630 
0631     return 0;
0632 err:
0633     dev_dbg(&client->dev, "failed=%d\n", ret);
0634     return ret;
0635 }
0636 
0637 static int rtl2832_read_status(struct dvb_frontend *fe, enum fe_status *status)
0638 {
0639     struct rtl2832_dev *dev = fe->demodulator_priv;
0640     struct i2c_client *client = dev->client;
0641     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0642     int ret;
0643     u32 tmp;
0644     u8 u8tmp, buf[2];
0645     u16 u16tmp;
0646 
0647     dev_dbg(&client->dev, "\n");
0648 
0649     *status = 0;
0650     if (dev->sleeping)
0651         return 0;
0652 
0653     ret = rtl2832_rd_demod_reg(dev, DVBT_FSM_STAGE, &tmp);
0654     if (ret)
0655         goto err;
0656 
0657     if (tmp == 11) {
0658         *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
0659                 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
0660     } else if (tmp == 10) {
0661         *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
0662                 FE_HAS_VITERBI;
0663     }
0664 
0665     dev->fe_status = *status;
0666 
0667     /* signal strength */
0668     if (dev->fe_status & FE_HAS_SIGNAL) {
0669         /* read digital AGC */
0670         ret = regmap_bulk_read(dev->regmap, 0x305, &u8tmp, 1);
0671         if (ret)
0672             goto err;
0673 
0674         dev_dbg(&client->dev, "digital agc=%02x", u8tmp);
0675 
0676         u8tmp = ~u8tmp;
0677         u16tmp = u8tmp << 8 | u8tmp << 0;
0678 
0679         c->strength.stat[0].scale = FE_SCALE_RELATIVE;
0680         c->strength.stat[0].uvalue = u16tmp;
0681     } else {
0682         c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0683     }
0684 
0685     /* CNR */
0686     if (dev->fe_status & FE_HAS_VITERBI) {
0687         unsigned hierarchy, constellation;
0688         #define CONSTELLATION_NUM 3
0689         #define HIERARCHY_NUM 4
0690         static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
0691             {85387325, 85387325, 85387325, 85387325},
0692             {86676178, 86676178, 87167949, 87795660},
0693             {87659938, 87659938, 87885178, 88241743},
0694         };
0695 
0696         ret = regmap_bulk_read(dev->regmap, 0x33c, &u8tmp, 1);
0697         if (ret)
0698             goto err;
0699 
0700         constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
0701         ret = -EINVAL;
0702         if (constellation > CONSTELLATION_NUM - 1)
0703             goto err;
0704 
0705         hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
0706         if (hierarchy > HIERARCHY_NUM - 1)
0707             goto err;
0708 
0709         ret = regmap_bulk_read(dev->regmap, 0x40c, buf, 2);
0710         if (ret)
0711             goto err;
0712 
0713         u16tmp = buf[0] << 8 | buf[1] << 0;
0714         if (u16tmp)
0715             tmp = (constant[constellation][hierarchy] -
0716                    intlog10(u16tmp)) / ((1 << 24) / 10000);
0717         else
0718             tmp = 0;
0719 
0720         dev_dbg(&client->dev, "cnr raw=%u\n", u16tmp);
0721 
0722         c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
0723         c->cnr.stat[0].svalue = tmp;
0724     } else {
0725         c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0726     }
0727 
0728     /* BER */
0729     if (dev->fe_status & FE_HAS_LOCK) {
0730         ret = regmap_bulk_read(dev->regmap, 0x34e, buf, 2);
0731         if (ret)
0732             goto err;
0733 
0734         u16tmp = buf[0] << 8 | buf[1] << 0;
0735         dev->post_bit_error += u16tmp;
0736         dev->post_bit_count += 1000000;
0737 
0738         dev_dbg(&client->dev, "ber errors=%u total=1000000\n", u16tmp);
0739 
0740         c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
0741         c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
0742         c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
0743         c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
0744     } else {
0745         c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0746         c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0747     }
0748 
0749     return 0;
0750 err:
0751     dev_dbg(&client->dev, "failed=%d\n", ret);
0752     return ret;
0753 }
0754 
0755 static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
0756 {
0757     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0758 
0759     /* report SNR in resolution of 0.1 dB */
0760     if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
0761         *snr = div_s64(c->cnr.stat[0].svalue, 100);
0762     else
0763         *snr = 0;
0764 
0765     return 0;
0766 }
0767 
0768 static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
0769 {
0770     struct rtl2832_dev *dev = fe->demodulator_priv;
0771 
0772     *ber = (dev->post_bit_error - dev->post_bit_error_prev);
0773     dev->post_bit_error_prev = dev->post_bit_error;
0774 
0775     return 0;
0776 }
0777 
0778 /*
0779  * I2C gate/mux/repeater logic
0780  * There is delay mechanism to avoid unneeded I2C gate open / close. Gate close
0781  * is delayed here a little bit in order to see if there is sequence of I2C
0782  * messages sent to same I2C bus.
0783  */
0784 static void rtl2832_i2c_gate_work(struct work_struct *work)
0785 {
0786     struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, i2c_gate_work.work);
0787     struct i2c_client *client = dev->client;
0788     int ret;
0789 
0790     /* close gate */
0791     ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x00);
0792     if (ret)
0793         goto err;
0794 
0795     return;
0796 err:
0797     dev_dbg(&client->dev, "failed=%d\n", ret);
0798 }
0799 
0800 static int rtl2832_select(struct i2c_mux_core *muxc, u32 chan_id)
0801 {
0802     struct rtl2832_dev *dev = i2c_mux_priv(muxc);
0803     struct i2c_client *client = dev->client;
0804     int ret;
0805 
0806     /* terminate possible gate closing */
0807     cancel_delayed_work(&dev->i2c_gate_work);
0808 
0809     /* open gate */
0810     ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
0811     if (ret)
0812         goto err;
0813 
0814     return 0;
0815 err:
0816     dev_dbg(&client->dev, "failed=%d\n", ret);
0817     return ret;
0818 }
0819 
0820 static int rtl2832_deselect(struct i2c_mux_core *muxc, u32 chan_id)
0821 {
0822     struct rtl2832_dev *dev = i2c_mux_priv(muxc);
0823 
0824     schedule_delayed_work(&dev->i2c_gate_work, usecs_to_jiffies(100));
0825     return 0;
0826 }
0827 
0828 static const struct dvb_frontend_ops rtl2832_ops = {
0829     .delsys = { SYS_DVBT },
0830     .info = {
0831         .name = "Realtek RTL2832 (DVB-T)",
0832         .frequency_min_hz   = 174 * MHz,
0833         .frequency_max_hz   = 862 * MHz,
0834         .frequency_stepsize_hz  = 166667,
0835         .caps = FE_CAN_FEC_1_2 |
0836             FE_CAN_FEC_2_3 |
0837             FE_CAN_FEC_3_4 |
0838             FE_CAN_FEC_5_6 |
0839             FE_CAN_FEC_7_8 |
0840             FE_CAN_FEC_AUTO |
0841             FE_CAN_QPSK |
0842             FE_CAN_QAM_16 |
0843             FE_CAN_QAM_64 |
0844             FE_CAN_QAM_AUTO |
0845             FE_CAN_TRANSMISSION_MODE_AUTO |
0846             FE_CAN_GUARD_INTERVAL_AUTO |
0847             FE_CAN_HIERARCHY_AUTO |
0848             FE_CAN_RECOVER |
0849             FE_CAN_MUTE_TS
0850      },
0851 
0852     .init = rtl2832_init,
0853     .sleep = rtl2832_sleep,
0854 
0855     .get_tune_settings = rtl2832_get_tune_settings,
0856 
0857     .set_frontend = rtl2832_set_frontend,
0858     .get_frontend = rtl2832_get_frontend,
0859 
0860     .read_status = rtl2832_read_status,
0861     .read_snr = rtl2832_read_snr,
0862     .read_ber = rtl2832_read_ber,
0863 };
0864 
0865 static bool rtl2832_volatile_reg(struct device *dev, unsigned int reg)
0866 {
0867     switch (reg) {
0868     case 0x305:
0869     case 0x33c:
0870     case 0x34e:
0871     case 0x351:
0872     case 0x40c ... 0x40d:
0873         return true;
0874     default:
0875         break;
0876     }
0877 
0878     return false;
0879 }
0880 
0881 static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
0882 {
0883     struct rtl2832_dev *dev = i2c_get_clientdata(client);
0884 
0885     dev_dbg(&client->dev, "\n");
0886     return &dev->fe;
0887 }
0888 
0889 static struct i2c_adapter *rtl2832_get_i2c_adapter(struct i2c_client *client)
0890 {
0891     struct rtl2832_dev *dev = i2c_get_clientdata(client);
0892 
0893     dev_dbg(&client->dev, "\n");
0894     return dev->muxc->adapter[0];
0895 }
0896 
0897 static int rtl2832_slave_ts_ctrl(struct i2c_client *client, bool enable)
0898 {
0899     struct rtl2832_dev *dev = i2c_get_clientdata(client);
0900     int ret;
0901 
0902     dev_dbg(&client->dev, "enable=%d\n", enable);
0903 
0904     if (enable) {
0905         ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
0906         if (ret)
0907             goto err;
0908         ret = regmap_bulk_write(dev->regmap, 0x10c, "\x5f\xff", 2);
0909         if (ret)
0910             goto err;
0911         ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
0912         if (ret)
0913             goto err;
0914         ret = regmap_bulk_write(dev->regmap, 0x0bc, "\x18", 1);
0915         if (ret)
0916             goto err;
0917         ret = regmap_bulk_write(dev->regmap, 0x192, "\x7f\xf7\xff", 3);
0918         if (ret)
0919             goto err;
0920     } else {
0921         ret = regmap_bulk_write(dev->regmap, 0x192, "\x00\x0f\xff", 3);
0922         if (ret)
0923             goto err;
0924         ret = regmap_bulk_write(dev->regmap, 0x0bc, "\x08", 1);
0925         if (ret)
0926             goto err;
0927         ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x0);
0928         if (ret)
0929             goto err;
0930         ret = regmap_bulk_write(dev->regmap, 0x10c, "\x00\x00", 2);
0931         if (ret)
0932             goto err;
0933         ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
0934         if (ret)
0935             goto err;
0936     }
0937 
0938     dev->slave_ts = enable;
0939 
0940     return 0;
0941 err:
0942     dev_dbg(&client->dev, "failed=%d\n", ret);
0943     return ret;
0944 }
0945 
0946 static int rtl2832_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
0947 {
0948     struct rtl2832_dev *dev = fe->demodulator_priv;
0949     struct i2c_client *client = dev->client;
0950     int ret;
0951     u8 u8tmp;
0952 
0953     dev_dbg(&client->dev, "onoff=%d, slave_ts=%d\n", onoff, dev->slave_ts);
0954 
0955     /* enable / disable PID filter */
0956     if (onoff)
0957         u8tmp = 0x80;
0958     else
0959         u8tmp = 0x00;
0960 
0961     if (dev->slave_ts)
0962         ret = regmap_update_bits(dev->regmap, 0x021, 0xc0, u8tmp);
0963     else
0964         ret = regmap_update_bits(dev->regmap, 0x061, 0xc0, u8tmp);
0965     if (ret)
0966         goto err;
0967 
0968     return 0;
0969 err:
0970     dev_dbg(&client->dev, "failed=%d\n", ret);
0971     return ret;
0972 }
0973 
0974 static int rtl2832_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid,
0975                   int onoff)
0976 {
0977     struct rtl2832_dev *dev = fe->demodulator_priv;
0978     struct i2c_client *client = dev->client;
0979     int ret;
0980     u8 buf[4];
0981 
0982     dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d slave_ts=%d\n",
0983         index, pid, onoff, dev->slave_ts);
0984 
0985     /* skip invalid PIDs (0x2000) */
0986     if (pid > 0x1fff || index > 32)
0987         return 0;
0988 
0989     if (onoff)
0990         set_bit(index, &dev->filters);
0991     else
0992         clear_bit(index, &dev->filters);
0993 
0994     /* enable / disable PIDs */
0995     buf[0] = (dev->filters >>  0) & 0xff;
0996     buf[1] = (dev->filters >>  8) & 0xff;
0997     buf[2] = (dev->filters >> 16) & 0xff;
0998     buf[3] = (dev->filters >> 24) & 0xff;
0999 
1000     if (dev->slave_ts)
1001         ret = regmap_bulk_write(dev->regmap, 0x022, buf, 4);
1002     else
1003         ret = regmap_bulk_write(dev->regmap, 0x062, buf, 4);
1004     if (ret)
1005         goto err;
1006 
1007     /* add PID */
1008     buf[0] = (pid >> 8) & 0xff;
1009     buf[1] = (pid >> 0) & 0xff;
1010 
1011     if (dev->slave_ts)
1012         ret = regmap_bulk_write(dev->regmap, 0x026 + 2 * index, buf, 2);
1013     else
1014         ret = regmap_bulk_write(dev->regmap, 0x066 + 2 * index, buf, 2);
1015     if (ret)
1016         goto err;
1017 
1018     return 0;
1019 err:
1020     dev_dbg(&client->dev, "failed=%d\n", ret);
1021     return ret;
1022 }
1023 
1024 static int rtl2832_probe(struct i2c_client *client,
1025         const struct i2c_device_id *id)
1026 {
1027     struct rtl2832_platform_data *pdata = client->dev.platform_data;
1028     struct i2c_adapter *i2c = client->adapter;
1029     struct rtl2832_dev *dev;
1030     int ret;
1031     u8 tmp;
1032     static const struct regmap_range_cfg regmap_range_cfg[] = {
1033         {
1034             .selector_reg     = 0x00,
1035             .selector_mask    = 0xff,
1036             .selector_shift   = 0,
1037             .window_start     = 0,
1038             .window_len       = 0x100,
1039             .range_min        = 0 * 0x100,
1040             .range_max        = 5 * 0x100,
1041         },
1042     };
1043 
1044     dev_dbg(&client->dev, "\n");
1045 
1046     /* allocate memory for the internal state */
1047     dev = kzalloc(sizeof(struct rtl2832_dev), GFP_KERNEL);
1048     if (dev == NULL) {
1049         ret = -ENOMEM;
1050         goto err;
1051     }
1052 
1053     /* setup the state */
1054     i2c_set_clientdata(client, dev);
1055     dev->client = client;
1056     dev->pdata = client->dev.platform_data;
1057     dev->sleeping = true;
1058     INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
1059     /* create regmap */
1060     dev->regmap_config.reg_bits =  8;
1061     dev->regmap_config.val_bits =  8;
1062     dev->regmap_config.volatile_reg = rtl2832_volatile_reg;
1063     dev->regmap_config.max_register = 5 * 0x100;
1064     dev->regmap_config.ranges = regmap_range_cfg;
1065     dev->regmap_config.num_ranges = ARRAY_SIZE(regmap_range_cfg);
1066     dev->regmap_config.cache_type = REGCACHE_NONE;
1067     dev->regmap = regmap_init_i2c(client, &dev->regmap_config);
1068     if (IS_ERR(dev->regmap)) {
1069         ret = PTR_ERR(dev->regmap);
1070         goto err_kfree;
1071     }
1072 
1073     /* check if the demod is there */
1074     ret = regmap_bulk_read(dev->regmap, 0x000, &tmp, 1);
1075     if (ret)
1076         goto err_regmap_exit;
1077 
1078     /* create muxed i2c adapter for demod tuner bus */
1079     dev->muxc = i2c_mux_alloc(i2c, &i2c->dev, 1, 0, I2C_MUX_LOCKED,
1080                   rtl2832_select, rtl2832_deselect);
1081     if (!dev->muxc) {
1082         ret = -ENOMEM;
1083         goto err_regmap_exit;
1084     }
1085     dev->muxc->priv = dev;
1086     ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);
1087     if (ret)
1088         goto err_regmap_exit;
1089 
1090     /* create dvb_frontend */
1091     memcpy(&dev->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
1092     dev->fe.demodulator_priv = dev;
1093 
1094     /* setup callbacks */
1095     pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
1096     pdata->get_i2c_adapter = rtl2832_get_i2c_adapter;
1097     pdata->slave_ts_ctrl = rtl2832_slave_ts_ctrl;
1098     pdata->pid_filter = rtl2832_pid_filter;
1099     pdata->pid_filter_ctrl = rtl2832_pid_filter_ctrl;
1100     pdata->regmap = dev->regmap;
1101 
1102     dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
1103     return 0;
1104 err_regmap_exit:
1105     regmap_exit(dev->regmap);
1106 err_kfree:
1107     kfree(dev);
1108 err:
1109     dev_dbg(&client->dev, "failed=%d\n", ret);
1110     return ret;
1111 }
1112 
1113 static int rtl2832_remove(struct i2c_client *client)
1114 {
1115     struct rtl2832_dev *dev = i2c_get_clientdata(client);
1116 
1117     dev_dbg(&client->dev, "\n");
1118 
1119     cancel_delayed_work_sync(&dev->i2c_gate_work);
1120 
1121     i2c_mux_del_adapters(dev->muxc);
1122 
1123     regmap_exit(dev->regmap);
1124 
1125     kfree(dev);
1126 
1127     return 0;
1128 }
1129 
1130 static const struct i2c_device_id rtl2832_id_table[] = {
1131     {"rtl2832", 0},
1132     {}
1133 };
1134 MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
1135 
1136 static struct i2c_driver rtl2832_driver = {
1137     .driver = {
1138         .name   = "rtl2832",
1139         .suppress_bind_attrs    = true,
1140     },
1141     .probe      = rtl2832_probe,
1142     .remove     = rtl2832_remove,
1143     .id_table   = rtl2832_id_table,
1144 };
1145 
1146 module_i2c_driver(rtl2832_driver);
1147 
1148 MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
1149 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1150 MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1151 MODULE_LICENSE("GPL");
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