media/dvb-frontends/nxt6000.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003     NxtWave Communications - NXT6000 demodulator driver
0004
0005     Copyright (C) 2002-2003 Florian Schirmer <jolt@tuxbox.org>
0006     Copyright (C) 2003 Paul Andreassen <paul@andreassen.com.au>
0007
0008 */
0009
0010 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0011
0012 #include <linux/init.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/string.h>
0016 #include <linux/slab.h>
0017
0018 #include <media/dvb_frontend.h>
0019 #include "nxt6000_priv.h"
0020 #include "nxt6000.h"
0021
0022
0023
0024 struct nxt6000_state {
0025     struct i2c_adapter* i2c;
0026     /* configuration settings */
0027     const struct nxt6000_config* config;
0028     struct dvb_frontend frontend;
0029 };
0030
0031 static int debug;
0032 #define dprintk(fmt, arg...) do {                   \
0033     if (debug)                          \
0034         printk(KERN_DEBUG pr_fmt("%s: " fmt),           \
0035                __func__, ##arg);                \
0036 } while (0)
0037
0038 static int nxt6000_writereg(struct nxt6000_state* state, u8 reg, u8 data)
0039 {
0040     u8 buf[] = { reg, data };
0041     struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
0042     int ret;
0043
0044     if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1)
0045         dprintk("nxt6000: nxt6000_write error (reg: 0x%02X, data: 0x%02X, ret: %d)\n", reg, data, ret);
0046
0047     return (ret != 1) ? -EIO : 0;
0048 }
0049
0050 static u8 nxt6000_readreg(struct nxt6000_state* state, u8 reg)
0051 {
0052     int ret;
0053     u8 b0[] = { reg };
0054     u8 b1[] = { 0 };
0055     struct i2c_msg msgs[] = {
0056         {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1},
0057         {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
0058     };
0059
0060     ret = i2c_transfer(state->i2c, msgs, 2);
0061
0062     if (ret != 2)
0063         dprintk("nxt6000: nxt6000_read error (reg: 0x%02X, ret: %d)\n", reg, ret);
0064
0065     return b1[0];
0066 }
0067
0068 static void nxt6000_reset(struct nxt6000_state* state)
0069 {
0070     u8 val;
0071
0072     val = nxt6000_readreg(state, OFDM_COR_CTL);
0073
0074     nxt6000_writereg(state, OFDM_COR_CTL, val & ~COREACT);
0075     nxt6000_writereg(state, OFDM_COR_CTL, val | COREACT);
0076 }
0077
0078 static int nxt6000_set_bandwidth(struct nxt6000_state *state, u32 bandwidth)
0079 {
0080     u16 nominal_rate;
0081     int result;
0082
0083     switch (bandwidth) {
0084     case 6000000:
0085         nominal_rate = 0x55B7;
0086         break;
0087
0088     case 7000000:
0089         nominal_rate = 0x6400;
0090         break;
0091
0092     case 8000000:
0093         nominal_rate = 0x7249;
0094         break;
0095
0096     default:
0097         return -EINVAL;
0098     }
0099
0100     if ((result = nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_1, nominal_rate & 0xFF)) < 0)
0101         return result;
0102
0103     return nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_2, (nominal_rate >> 8) & 0xFF);
0104 }
0105
0106 static int nxt6000_set_guard_interval(struct nxt6000_state *state,
0107                       enum fe_guard_interval guard_interval)
0108 {
0109     switch (guard_interval) {
0110
0111     case GUARD_INTERVAL_1_32:
0112         return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x00 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03));
0113
0114     case GUARD_INTERVAL_1_16:
0115         return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x01 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03));
0116
0117     case GUARD_INTERVAL_AUTO:
0118     case GUARD_INTERVAL_1_8:
0119         return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x02 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03));
0120
0121     case GUARD_INTERVAL_1_4:
0122         return nxt6000_writereg(state, OFDM_COR_MODEGUARD, 0x03 | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x03));
0123
0124     default:
0125         return -EINVAL;
0126     }
0127 }
0128
0129 static int nxt6000_set_inversion(struct nxt6000_state *state,
0130                  enum fe_spectral_inversion inversion)
0131 {
0132     switch (inversion) {
0133
0134     case INVERSION_OFF:
0135         return nxt6000_writereg(state, OFDM_ITB_CTL, 0x00);
0136
0137     case INVERSION_ON:
0138         return nxt6000_writereg(state, OFDM_ITB_CTL, ITBINV);
0139
0140     default:
0141         return -EINVAL;
0142
0143     }
0144 }
0145
0146 static int
0147 nxt6000_set_transmission_mode(struct nxt6000_state *state,
0148                   enum fe_transmit_mode transmission_mode)
0149 {
0150     int result;
0151
0152     switch (transmission_mode) {
0153
0154     case TRANSMISSION_MODE_2K:
0155         if ((result = nxt6000_writereg(state, EN_DMD_RACQ, 0x00 | (nxt6000_readreg(state, EN_DMD_RACQ) & ~0x03))) < 0)
0156             return result;
0157
0158         return nxt6000_writereg(state, OFDM_COR_MODEGUARD, (0x00 << 2) | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x04));
0159
0160     case TRANSMISSION_MODE_8K:
0161     case TRANSMISSION_MODE_AUTO:
0162         if ((result = nxt6000_writereg(state, EN_DMD_RACQ, 0x02 | (nxt6000_readreg(state, EN_DMD_RACQ) & ~0x03))) < 0)
0163             return result;
0164
0165         return nxt6000_writereg(state, OFDM_COR_MODEGUARD, (0x01 << 2) | (nxt6000_readreg(state, OFDM_COR_MODEGUARD) & ~0x04));
0166
0167     default:
0168         return -EINVAL;
0169
0170     }
0171 }
0172
0173 static void nxt6000_setup(struct dvb_frontend* fe)
0174 {
0175     struct nxt6000_state* state = fe->demodulator_priv;
0176
0177     nxt6000_writereg(state, RS_COR_SYNC_PARAM, SYNC_PARAM);
0178     nxt6000_writereg(state, BER_CTRL, /*(1 << 2) | */ (0x01 << 1) | 0x01);
0179     nxt6000_writereg(state, VIT_BERTIME_2, 0x00);  // BER Timer = 0x000200 * 256 = 131072 bits
0180     nxt6000_writereg(state, VIT_BERTIME_1, 0x02);  //
0181     nxt6000_writereg(state, VIT_BERTIME_0, 0x00);  //
0182     nxt6000_writereg(state, VIT_COR_INTEN, 0x98); // Enable BER interrupts
0183     nxt6000_writereg(state, VIT_COR_CTL, 0x82);   // Enable BER measurement
0184     nxt6000_writereg(state, VIT_COR_CTL, VIT_COR_RESYNC | 0x02 );
0185     nxt6000_writereg(state, OFDM_COR_CTL, (0x01 << 5) | (nxt6000_readreg(state, OFDM_COR_CTL) & 0x0F));
0186     nxt6000_writereg(state, OFDM_COR_MODEGUARD, FORCEMODE8K | 0x02);
0187     nxt6000_writereg(state, OFDM_AGC_CTL, AGCLAST | INITIAL_AGC_BW);
0188     nxt6000_writereg(state, OFDM_ITB_FREQ_1, 0x06);
0189     nxt6000_writereg(state, OFDM_ITB_FREQ_2, 0x31);
0190     nxt6000_writereg(state, OFDM_CAS_CTL, (0x01 << 7) | (0x02 << 3) | 0x04);
0191     nxt6000_writereg(state, CAS_FREQ, 0xBB);    /* CHECKME */
0192     nxt6000_writereg(state, OFDM_SYR_CTL, 1 << 2);
0193     nxt6000_writereg(state, OFDM_PPM_CTL_1, PPM256);
0194     nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_1, 0x49);
0195     nxt6000_writereg(state, OFDM_TRL_NOMINALRATE_2, 0x72);
0196     nxt6000_writereg(state, ANALOG_CONTROL_0, 1 << 5);
0197     nxt6000_writereg(state, EN_DMD_RACQ, (1 << 7) | (3 << 4) | 2);
0198     nxt6000_writereg(state, DIAG_CONFIG, TB_SET);
0199
0200     if (state->config->clock_inversion)
0201         nxt6000_writereg(state, SUB_DIAG_MODE_SEL, CLKINVERSION);
0202     else
0203         nxt6000_writereg(state, SUB_DIAG_MODE_SEL, 0);
0204
0205     nxt6000_writereg(state, TS_FORMAT, 0);
0206 }
0207
0208 static void nxt6000_dump_status(struct nxt6000_state *state)
0209 {
0210     u8 val;
0211
0212 #if 0
0213     pr_info("RS_COR_STAT: 0x%02X\n",
0214         nxt6000_readreg(fe, RS_COR_STAT));
0215     pr_info("VIT_SYNC_STATUS: 0x%02X\n",
0216         nxt6000_readreg(fe, VIT_SYNC_STATUS));
0217     pr_info("OFDM_COR_STAT: 0x%02X\n",
0218         nxt6000_readreg(fe, OFDM_COR_STAT));
0219     pr_info("OFDM_SYR_STAT: 0x%02X\n",
0220         nxt6000_readreg(fe, OFDM_SYR_STAT));
0221     pr_info("OFDM_TPS_RCVD_1: 0x%02X\n",
0222         nxt6000_readreg(fe, OFDM_TPS_RCVD_1));
0223     pr_info("OFDM_TPS_RCVD_2: 0x%02X\n",
0224         nxt6000_readreg(fe, OFDM_TPS_RCVD_2));
0225     pr_info("OFDM_TPS_RCVD_3: 0x%02X\n",
0226         nxt6000_readreg(fe, OFDM_TPS_RCVD_3));
0227     pr_info("OFDM_TPS_RCVD_4: 0x%02X\n",
0228         nxt6000_readreg(fe, OFDM_TPS_RCVD_4));
0229     pr_info("OFDM_TPS_RESERVED_1: 0x%02X\n",
0230         nxt6000_readreg(fe, OFDM_TPS_RESERVED_1));
0231     pr_info("OFDM_TPS_RESERVED_2: 0x%02X\n",
0232         nxt6000_readreg(fe, OFDM_TPS_RESERVED_2));
0233 #endif
0234     pr_info("NXT6000 status:");
0235
0236     val = nxt6000_readreg(state, RS_COR_STAT);
0237
0238     pr_cont(" DATA DESCR LOCK: %d,", val & 0x01);
0239     pr_cont(" DATA SYNC LOCK: %d,", (val >> 1) & 0x01);
0240
0241     val = nxt6000_readreg(state, VIT_SYNC_STATUS);
0242
0243     pr_cont(" VITERBI LOCK: %d,", (val >> 7) & 0x01);
0244
0245     switch ((val >> 4) & 0x07) {
0246
0247     case 0x00:
0248         pr_cont(" VITERBI CODERATE: 1/2,");
0249         break;
0250
0251     case 0x01:
0252         pr_cont(" VITERBI CODERATE: 2/3,");
0253         break;
0254
0255     case 0x02:
0256         pr_cont(" VITERBI CODERATE: 3/4,");
0257         break;
0258
0259     case 0x03:
0260         pr_cont(" VITERBI CODERATE: 5/6,");
0261         break;
0262
0263     case 0x04:
0264         pr_cont(" VITERBI CODERATE: 7/8,");
0265         break;
0266
0267     default:
0268         pr_cont(" VITERBI CODERATE: Reserved,");
0269
0270     }
0271
0272     val = nxt6000_readreg(state, OFDM_COR_STAT);
0273
0274     pr_cont(" CHCTrack: %d,", (val >> 7) & 0x01);
0275     pr_cont(" TPSLock: %d,", (val >> 6) & 0x01);
0276     pr_cont(" SYRLock: %d,", (val >> 5) & 0x01);
0277     pr_cont(" AGCLock: %d,", (val >> 4) & 0x01);
0278
0279     switch (val & 0x0F) {
0280
0281     case 0x00:
0282         pr_cont(" CoreState: IDLE,");
0283         break;
0284
0285     case 0x02:
0286         pr_cont(" CoreState: WAIT_AGC,");
0287         break;
0288
0289     case 0x03:
0290         pr_cont(" CoreState: WAIT_SYR,");
0291         break;
0292
0293     case 0x04:
0294         pr_cont(" CoreState: WAIT_PPM,");
0295         break;
0296
0297     case 0x01:
0298         pr_cont(" CoreState: WAIT_TRL,");
0299         break;
0300
0301     case 0x05:
0302         pr_cont(" CoreState: WAIT_TPS,");
0303         break;
0304
0305     case 0x06:
0306         pr_cont(" CoreState: MONITOR_TPS,");
0307         break;
0308
0309     default:
0310         pr_cont(" CoreState: Reserved,");
0311
0312     }
0313
0314     val = nxt6000_readreg(state, OFDM_SYR_STAT);
0315
0316     pr_cont(" SYRLock: %d,", (val >> 4) & 0x01);
0317     pr_cont(" SYRMode: %s,", (val >> 2) & 0x01 ? "8K" : "2K");
0318
0319     switch ((val >> 4) & 0x03) {
0320
0321     case 0x00:
0322         pr_cont(" SYRGuard: 1/32,");
0323         break;
0324
0325     case 0x01:
0326         pr_cont(" SYRGuard: 1/16,");
0327         break;
0328
0329     case 0x02:
0330         pr_cont(" SYRGuard: 1/8,");
0331         break;
0332
0333     case 0x03:
0334         pr_cont(" SYRGuard: 1/4,");
0335         break;
0336     }
0337
0338     val = nxt6000_readreg(state, OFDM_TPS_RCVD_3);
0339
0340     switch ((val >> 4) & 0x07) {
0341
0342     case 0x00:
0343         pr_cont(" TPSLP: 1/2,");
0344         break;
0345
0346     case 0x01:
0347         pr_cont(" TPSLP: 2/3,");
0348         break;
0349
0350     case 0x02:
0351         pr_cont(" TPSLP: 3/4,");
0352         break;
0353
0354     case 0x03:
0355         pr_cont(" TPSLP: 5/6,");
0356         break;
0357
0358     case 0x04:
0359         pr_cont(" TPSLP: 7/8,");
0360         break;
0361
0362     default:
0363         pr_cont(" TPSLP: Reserved,");
0364
0365     }
0366
0367     switch (val & 0x07) {
0368
0369     case 0x00:
0370         pr_cont(" TPSHP: 1/2,");
0371         break;
0372
0373     case 0x01:
0374         pr_cont(" TPSHP: 2/3,");
0375         break;
0376
0377     case 0x02:
0378         pr_cont(" TPSHP: 3/4,");
0379         break;
0380
0381     case 0x03:
0382         pr_cont(" TPSHP: 5/6,");
0383         break;
0384
0385     case 0x04:
0386         pr_cont(" TPSHP: 7/8,");
0387         break;
0388
0389     default:
0390         pr_cont(" TPSHP: Reserved,");
0391
0392     }
0393
0394     val = nxt6000_readreg(state, OFDM_TPS_RCVD_4);
0395
0396     pr_cont(" TPSMode: %s,", val & 0x01 ? "8K" : "2K");
0397
0398     switch ((val >> 4) & 0x03) {
0399
0400     case 0x00:
0401         pr_cont(" TPSGuard: 1/32,");
0402         break;
0403
0404     case 0x01:
0405         pr_cont(" TPSGuard: 1/16,");
0406         break;
0407
0408     case 0x02:
0409         pr_cont(" TPSGuard: 1/8,");
0410         break;
0411
0412     case 0x03:
0413         pr_cont(" TPSGuard: 1/4,");
0414         break;
0415
0416     }
0417
0418     /* Strange magic required to gain access to RF_AGC_STATUS */
0419     nxt6000_readreg(state, RF_AGC_VAL_1);
0420     val = nxt6000_readreg(state, RF_AGC_STATUS);
0421     val = nxt6000_readreg(state, RF_AGC_STATUS);
0422
0423     pr_cont(" RF AGC LOCK: %d,", (val >> 4) & 0x01);
0424     pr_cont("\n");
0425 }
0426
0427 static int nxt6000_read_status(struct dvb_frontend *fe, enum fe_status *status)
0428 {
0429     u8 core_status;
0430     struct nxt6000_state* state = fe->demodulator_priv;
0431
0432     *status = 0;
0433
0434     core_status = nxt6000_readreg(state, OFDM_COR_STAT);
0435
0436     if (core_status & AGCLOCKED)
0437         *status |= FE_HAS_SIGNAL;
0438
0439     if (nxt6000_readreg(state, OFDM_SYR_STAT) & GI14_SYR_LOCK)
0440         *status |= FE_HAS_CARRIER;
0441
0442     if (nxt6000_readreg(state, VIT_SYNC_STATUS) & VITINSYNC)
0443         *status |= FE_HAS_VITERBI;
0444
0445     if (nxt6000_readreg(state, RS_COR_STAT) & RSCORESTATUS)
0446         *status |= FE_HAS_SYNC;
0447
0448     if ((core_status & TPSLOCKED) && (*status == (FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)))
0449         *status |= FE_HAS_LOCK;
0450
0451     if (debug)
0452         nxt6000_dump_status(state);
0453
0454     return 0;
0455 }
0456
0457 static int nxt6000_init(struct dvb_frontend* fe)
0458 {
0459     struct nxt6000_state* state = fe->demodulator_priv;
0460
0461     nxt6000_reset(state);
0462     nxt6000_setup(fe);
0463
0464     return 0;
0465 }
0466
0467 static int nxt6000_set_frontend(struct dvb_frontend *fe)
0468 {
0469     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0470     struct nxt6000_state* state = fe->demodulator_priv;
0471     int result;
0472
0473     if (fe->ops.tuner_ops.set_params) {
0474         fe->ops.tuner_ops.set_params(fe);
0475         if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
0476     }
0477
0478     result = nxt6000_set_bandwidth(state, p->bandwidth_hz);
0479     if (result < 0)
0480         return result;
0481
0482     result = nxt6000_set_guard_interval(state, p->guard_interval);
0483     if (result < 0)
0484         return result;
0485
0486     result = nxt6000_set_transmission_mode(state, p->transmission_mode);
0487     if (result < 0)
0488         return result;
0489
0490     result = nxt6000_set_inversion(state, p->inversion);
0491     if (result < 0)
0492         return result;
0493
0494     msleep(500);
0495     return 0;
0496 }
0497
0498 static void nxt6000_release(struct dvb_frontend* fe)
0499 {
0500     struct nxt6000_state* state = fe->demodulator_priv;
0501     kfree(state);
0502 }
0503
0504 static int nxt6000_read_snr(struct dvb_frontend* fe, u16* snr)
0505 {
0506     struct nxt6000_state* state = fe->demodulator_priv;
0507
0508     *snr = nxt6000_readreg( state, OFDM_CHC_SNR) / 8;
0509
0510     return 0;
0511 }
0512
0513 static int nxt6000_read_ber(struct dvb_frontend* fe, u32* ber)
0514 {
0515     struct nxt6000_state* state = fe->demodulator_priv;
0516
0517     nxt6000_writereg( state, VIT_COR_INTSTAT, 0x18 );
0518
0519     *ber = (nxt6000_readreg( state, VIT_BER_1 ) << 8 ) |
0520         nxt6000_readreg( state, VIT_BER_0 );
0521
0522     nxt6000_writereg( state, VIT_COR_INTSTAT, 0x18); // Clear BER Done interrupts
0523
0524     return 0;
0525 }
0526
0527 static int nxt6000_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
0528 {
0529     struct nxt6000_state* state = fe->demodulator_priv;
0530
0531     *signal_strength = (short) (511 -
0532         (nxt6000_readreg(state, AGC_GAIN_1) +
0533         ((nxt6000_readreg(state, AGC_GAIN_2) & 0x03) << 8)));
0534
0535     return 0;
0536 }
0537
0538 static int nxt6000_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
0539 {
0540     tune->min_delay_ms = 500;
0541     return 0;
0542 }
0543
0544 static int nxt6000_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
0545 {
0546     struct nxt6000_state* state = fe->demodulator_priv;
0547
0548     if (enable) {
0549         return nxt6000_writereg(state, ENABLE_TUNER_IIC, 0x01);
0550     } else {
0551         return nxt6000_writereg(state, ENABLE_TUNER_IIC, 0x00);
0552     }
0553 }
0554
0555 static const struct dvb_frontend_ops nxt6000_ops;
0556
0557 struct dvb_frontend* nxt6000_attach(const struct nxt6000_config* config,
0558                     struct i2c_adapter* i2c)
0559 {
0560     struct nxt6000_state* state = NULL;
0561
0562     /* allocate memory for the internal state */
0563     state = kzalloc(sizeof(struct nxt6000_state), GFP_KERNEL);
0564     if (state == NULL) goto error;
0565
0566     /* setup the state */
0567     state->config = config;
0568     state->i2c = i2c;
0569
0570     /* check if the demod is there */
0571     if (nxt6000_readreg(state, OFDM_MSC_REV) != NXT6000ASICDEVICE) goto error;
0572
0573     /* create dvb_frontend */
0574     memcpy(&state->frontend.ops, &nxt6000_ops, sizeof(struct dvb_frontend_ops));
0575     state->frontend.demodulator_priv = state;
0576     return &state->frontend;
0577
0578 error:
0579     kfree(state);
0580     return NULL;
0581 }
0582
0583 static const struct dvb_frontend_ops nxt6000_ops = {
0584     .delsys = { SYS_DVBT },
0585     .info = {
0586         .name = "NxtWave NXT6000 DVB-T",
0587         .frequency_min_hz = 0,
0588         .frequency_max_hz = 863250 * kHz,
0589         .frequency_stepsize_hz = 62500,
0590         /*.frequency_tolerance = *//* FIXME: 12% of SR */
0591         .symbol_rate_min = 0,   /* FIXME */
0592         .symbol_rate_max = 9360000, /* FIXME */
0593         .symbol_rate_tolerance = 4000,
0594         .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
0595             FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
0596             FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO |
0597             FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
0598             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
0599             FE_CAN_HIERARCHY_AUTO,
0600     },
0601
0602     .release = nxt6000_release,
0603
0604     .init = nxt6000_init,
0605     .i2c_gate_ctrl = nxt6000_i2c_gate_ctrl,
0606
0607     .get_tune_settings = nxt6000_fe_get_tune_settings,
0608
0609     .set_frontend = nxt6000_set_frontend,
0610
0611     .read_status = nxt6000_read_status,
0612     .read_ber = nxt6000_read_ber,
0613     .read_signal_strength = nxt6000_read_signal_strength,
0614     .read_snr = nxt6000_read_snr,
0615 };
0616
0617 module_param(debug, int, 0644);
0618 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
0619
0620 MODULE_DESCRIPTION("NxtWave NXT6000 DVB-T demodulator driver");
0621 MODULE_AUTHOR("Florian Schirmer");
0622 MODULE_LICENSE("GPL");
0623
0624 EXPORT_SYMBOL(nxt6000_attach);