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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *    Support for NXT2002 and NXT2004 - VSB/QAM
0004  *
0005  *    Copyright (C) 2005 Kirk Lapray <kirk.lapray@gmail.com>
0006  *    Copyright (C) 2006-2014 Michael Krufky <mkrufky@linuxtv.org>
0007  *    based on nxt2002 by Taylor Jacob <rtjacob@earthlink.net>
0008  *    and nxt2004 by Jean-Francois Thibert <jeanfrancois@sagetv.com>
0009 */
0010 
0011 /*
0012  *                      NOTES ABOUT THIS DRIVER
0013  *
0014  * This Linux driver supports:
0015  *   B2C2/BBTI Technisat Air2PC - ATSC (NXT2002)
0016  *   AverTVHD MCE A180 (NXT2004)
0017  *   ATI HDTV Wonder (NXT2004)
0018  *
0019  * This driver needs external firmware. Please use the command
0020  * "<kerneldir>/scripts/get_dvb_firmware nxt2002" or
0021  * "<kerneldir>/scripts/get_dvb_firmware nxt2004" to
0022  * download/extract the appropriate firmware, and then copy it to
0023  * /usr/lib/hotplug/firmware/ or /lib/firmware/
0024  * (depending on configuration of firmware hotplug).
0025  */
0026 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0027 
0028 /* Max transfer size done by I2C transfer functions */
0029 #define MAX_XFER_SIZE  256
0030 
0031 #define NXT2002_DEFAULT_FIRMWARE "dvb-fe-nxt2002.fw"
0032 #define NXT2004_DEFAULT_FIRMWARE "dvb-fe-nxt2004.fw"
0033 #define CRC_CCIT_MASK 0x1021
0034 
0035 #include <linux/kernel.h>
0036 #include <linux/init.h>
0037 #include <linux/module.h>
0038 #include <linux/slab.h>
0039 #include <linux/string.h>
0040 
0041 #include <media/dvb_frontend.h>
0042 #include "nxt200x.h"
0043 
0044 struct nxt200x_state {
0045 
0046     struct i2c_adapter* i2c;
0047     const struct nxt200x_config* config;
0048     struct dvb_frontend frontend;
0049 
0050     /* demodulator private data */
0051     nxt_chip_type demod_chip;
0052     u8 initialised:1;
0053 };
0054 
0055 static int debug;
0056 #define dprintk(args...)    do { if (debug) pr_debug(args); } while (0)
0057 
0058 static int i2c_writebytes (struct nxt200x_state* state, u8 addr, u8 *buf, u8 len)
0059 {
0060     int err;
0061     struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = len };
0062 
0063     if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
0064         pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n",
0065             __func__, addr, err);
0066         return -EREMOTEIO;
0067     }
0068     return 0;
0069 }
0070 
0071 static int i2c_readbytes(struct nxt200x_state *state, u8 addr, u8 *buf, u8 len)
0072 {
0073     int err;
0074     struct i2c_msg msg = { .addr = addr, .flags = I2C_M_RD, .buf = buf, .len = len };
0075 
0076     if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
0077         pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n",
0078             __func__, addr, err);
0079         return -EREMOTEIO;
0080     }
0081     return 0;
0082 }
0083 
0084 static int nxt200x_writebytes (struct nxt200x_state* state, u8 reg,
0085                    const u8 *buf, u8 len)
0086 {
0087     u8 buf2[MAX_XFER_SIZE];
0088     int err;
0089     struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf2, .len = len + 1 };
0090 
0091     if (1 + len > sizeof(buf2)) {
0092         pr_warn("%s: i2c wr reg=%04x: len=%d is too big!\n",
0093              __func__, reg, len);
0094         return -EINVAL;
0095     }
0096 
0097     buf2[0] = reg;
0098     memcpy(&buf2[1], buf, len);
0099 
0100     if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
0101         pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n",
0102             __func__, state->config->demod_address, err);
0103         return -EREMOTEIO;
0104     }
0105     return 0;
0106 }
0107 
0108 static int nxt200x_readbytes(struct nxt200x_state *state, u8 reg, u8 *buf, u8 len)
0109 {
0110     u8 reg2 [] = { reg };
0111 
0112     struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = reg2, .len = 1 },
0113             { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = buf, .len = len } };
0114 
0115     int err;
0116 
0117     if ((err = i2c_transfer (state->i2c, msg, 2)) != 2) {
0118         pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n",
0119             __func__, state->config->demod_address, err);
0120         return -EREMOTEIO;
0121     }
0122     return 0;
0123 }
0124 
0125 static u16 nxt200x_crc(u16 crc, u8 c)
0126 {
0127     u8 i;
0128     u16 input = (u16) c & 0xFF;
0129 
0130     input<<=8;
0131     for(i=0; i<8; i++) {
0132         if((crc^input) & 0x8000)
0133             crc=(crc<<1)^CRC_CCIT_MASK;
0134         else
0135             crc<<=1;
0136         input<<=1;
0137     }
0138     return crc;
0139 }
0140 
0141 static int nxt200x_writereg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len)
0142 {
0143     u8 attr, len2, buf;
0144     dprintk("%s\n", __func__);
0145 
0146     /* set multi register register */
0147     nxt200x_writebytes(state, 0x35, &reg, 1);
0148 
0149     /* send the actual data */
0150     nxt200x_writebytes(state, 0x36, data, len);
0151 
0152     switch (state->demod_chip) {
0153         case NXT2002:
0154             len2 = len;
0155             buf = 0x02;
0156             break;
0157         case NXT2004:
0158             /* probably not right, but gives correct values */
0159             attr = 0x02;
0160             if (reg & 0x80) {
0161                 attr = attr << 1;
0162                 if (reg & 0x04)
0163                     attr = attr >> 1;
0164             }
0165             /* set write bit */
0166             len2 = ((attr << 4) | 0x10) | len;
0167             buf = 0x80;
0168             break;
0169         default:
0170             return -EINVAL;
0171     }
0172 
0173     /* set multi register length */
0174     nxt200x_writebytes(state, 0x34, &len2, 1);
0175 
0176     /* toggle the multireg write bit */
0177     nxt200x_writebytes(state, 0x21, &buf, 1);
0178 
0179     nxt200x_readbytes(state, 0x21, &buf, 1);
0180 
0181     switch (state->demod_chip) {
0182         case NXT2002:
0183             if ((buf & 0x02) == 0)
0184                 return 0;
0185             break;
0186         case NXT2004:
0187             if (buf == 0)
0188                 return 0;
0189             break;
0190         default:
0191             return -EINVAL;
0192     }
0193 
0194     pr_warn("Error writing multireg register 0x%02X\n", reg);
0195 
0196     return 0;
0197 }
0198 
0199 static int nxt200x_readreg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len)
0200 {
0201     int i;
0202     u8 buf, len2, attr;
0203     dprintk("%s\n", __func__);
0204 
0205     /* set multi register register */
0206     nxt200x_writebytes(state, 0x35, &reg, 1);
0207 
0208     switch (state->demod_chip) {
0209         case NXT2002:
0210             /* set multi register length */
0211             len2 = len & 0x80;
0212             nxt200x_writebytes(state, 0x34, &len2, 1);
0213 
0214             /* read the actual data */
0215             nxt200x_readbytes(state, reg, data, len);
0216             return 0;
0217         case NXT2004:
0218             /* probably not right, but gives correct values */
0219             attr = 0x02;
0220             if (reg & 0x80) {
0221                 attr = attr << 1;
0222                 if (reg & 0x04)
0223                     attr = attr >> 1;
0224             }
0225 
0226             /* set multi register length */
0227             len2 = (attr << 4) | len;
0228             nxt200x_writebytes(state, 0x34, &len2, 1);
0229 
0230             /* toggle the multireg bit*/
0231             buf = 0x80;
0232             nxt200x_writebytes(state, 0x21, &buf, 1);
0233 
0234             /* read the actual data */
0235             for(i = 0; i < len; i++) {
0236                 nxt200x_readbytes(state, 0x36 + i, &data[i], 1);
0237             }
0238             return 0;
0239         default:
0240             return -EINVAL;
0241     }
0242 }
0243 
0244 static void nxt200x_microcontroller_stop (struct nxt200x_state* state)
0245 {
0246     u8 buf, stopval, counter = 0;
0247     dprintk("%s\n", __func__);
0248 
0249     /* set correct stop value */
0250     switch (state->demod_chip) {
0251         case NXT2002:
0252             stopval = 0x40;
0253             break;
0254         case NXT2004:
0255             stopval = 0x10;
0256             break;
0257         default:
0258             stopval = 0;
0259             break;
0260     }
0261 
0262     buf = 0x80;
0263     nxt200x_writebytes(state, 0x22, &buf, 1);
0264 
0265     while (counter < 20) {
0266         nxt200x_readbytes(state, 0x31, &buf, 1);
0267         if (buf & stopval)
0268             return;
0269         msleep(10);
0270         counter++;
0271     }
0272 
0273     pr_warn("Timeout waiting for nxt200x to stop. This is ok after firmware upload.\n");
0274     return;
0275 }
0276 
0277 static void nxt200x_microcontroller_start (struct nxt200x_state* state)
0278 {
0279     u8 buf;
0280     dprintk("%s\n", __func__);
0281 
0282     buf = 0x00;
0283     nxt200x_writebytes(state, 0x22, &buf, 1);
0284 }
0285 
0286 static void nxt2004_microcontroller_init (struct nxt200x_state* state)
0287 {
0288     u8 buf[9];
0289     u8 counter = 0;
0290     dprintk("%s\n", __func__);
0291 
0292     buf[0] = 0x00;
0293     nxt200x_writebytes(state, 0x2b, buf, 1);
0294     buf[0] = 0x70;
0295     nxt200x_writebytes(state, 0x34, buf, 1);
0296     buf[0] = 0x04;
0297     nxt200x_writebytes(state, 0x35, buf, 1);
0298     buf[0] = 0x01; buf[1] = 0x23; buf[2] = 0x45; buf[3] = 0x67; buf[4] = 0x89;
0299     buf[5] = 0xAB; buf[6] = 0xCD; buf[7] = 0xEF; buf[8] = 0xC0;
0300     nxt200x_writebytes(state, 0x36, buf, 9);
0301     buf[0] = 0x80;
0302     nxt200x_writebytes(state, 0x21, buf, 1);
0303 
0304     while (counter < 20) {
0305         nxt200x_readbytes(state, 0x21, buf, 1);
0306         if (buf[0] == 0)
0307             return;
0308         msleep(10);
0309         counter++;
0310     }
0311 
0312     pr_warn("Timeout waiting for nxt2004 to init.\n");
0313 
0314     return;
0315 }
0316 
0317 static int nxt200x_writetuner (struct nxt200x_state* state, u8* data)
0318 {
0319     u8 buf, count = 0;
0320 
0321     dprintk("%s\n", __func__);
0322 
0323     dprintk("Tuner Bytes: %*ph\n", 4, data + 1);
0324 
0325     /* if NXT2004, write directly to tuner. if NXT2002, write through NXT chip.
0326      * direct write is required for Philips TUV1236D and ALPS TDHU2 */
0327     switch (state->demod_chip) {
0328         case NXT2004:
0329             if (i2c_writebytes(state, data[0], data+1, 4))
0330                 pr_warn("error writing to tuner\n");
0331             /* wait until we have a lock */
0332             while (count < 20) {
0333                 i2c_readbytes(state, data[0], &buf, 1);
0334                 if (buf & 0x40)
0335                     return 0;
0336                 msleep(100);
0337                 count++;
0338             }
0339             pr_warn("timeout waiting for tuner lock\n");
0340             break;
0341         case NXT2002:
0342             /* set the i2c transfer speed to the tuner */
0343             buf = 0x03;
0344             nxt200x_writebytes(state, 0x20, &buf, 1);
0345 
0346             /* setup to transfer 4 bytes via i2c */
0347             buf = 0x04;
0348             nxt200x_writebytes(state, 0x34, &buf, 1);
0349 
0350             /* write actual tuner bytes */
0351             nxt200x_writebytes(state, 0x36, data+1, 4);
0352 
0353             /* set tuner i2c address */
0354             buf = data[0] << 1;
0355             nxt200x_writebytes(state, 0x35, &buf, 1);
0356 
0357             /* write UC Opmode to begin transfer */
0358             buf = 0x80;
0359             nxt200x_writebytes(state, 0x21, &buf, 1);
0360 
0361             while (count < 20) {
0362                 nxt200x_readbytes(state, 0x21, &buf, 1);
0363                 if ((buf & 0x80)== 0x00)
0364                     return 0;
0365                 msleep(100);
0366                 count++;
0367             }
0368             pr_warn("timeout error writing to tuner\n");
0369             break;
0370         default:
0371             return -EINVAL;
0372     }
0373     return 0;
0374 }
0375 
0376 static void nxt200x_agc_reset(struct nxt200x_state* state)
0377 {
0378     u8 buf;
0379     dprintk("%s\n", __func__);
0380 
0381     switch (state->demod_chip) {
0382         case NXT2002:
0383             buf = 0x08;
0384             nxt200x_writebytes(state, 0x08, &buf, 1);
0385             buf = 0x00;
0386             nxt200x_writebytes(state, 0x08, &buf, 1);
0387             break;
0388         case NXT2004:
0389             nxt200x_readreg_multibyte(state, 0x08, &buf, 1);
0390             buf = 0x08;
0391             nxt200x_writereg_multibyte(state, 0x08, &buf, 1);
0392             buf = 0x00;
0393             nxt200x_writereg_multibyte(state, 0x08, &buf, 1);
0394             break;
0395         default:
0396             break;
0397     }
0398     return;
0399 }
0400 
0401 static int nxt2002_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
0402 {
0403 
0404     struct nxt200x_state* state = fe->demodulator_priv;
0405     u8 buf[3], written = 0, chunkpos = 0;
0406     u16 rambase, position, crc = 0;
0407 
0408     dprintk("%s\n", __func__);
0409     dprintk("Firmware is %zu bytes\n", fw->size);
0410 
0411     /* Get the RAM base for this nxt2002 */
0412     nxt200x_readbytes(state, 0x10, buf, 1);
0413 
0414     if (buf[0] & 0x10)
0415         rambase = 0x1000;
0416     else
0417         rambase = 0x0000;
0418 
0419     dprintk("rambase on this nxt2002 is %04X\n", rambase);
0420 
0421     /* Hold the micro in reset while loading firmware */
0422     buf[0] = 0x80;
0423     nxt200x_writebytes(state, 0x2B, buf, 1);
0424 
0425     for (position = 0; position < fw->size; position++) {
0426         if (written == 0) {
0427             crc = 0;
0428             chunkpos = 0x28;
0429             buf[0] = ((rambase + position) >> 8);
0430             buf[1] = (rambase + position) & 0xFF;
0431             buf[2] = 0x81;
0432             /* write starting address */
0433             nxt200x_writebytes(state, 0x29, buf, 3);
0434         }
0435         written++;
0436         chunkpos++;
0437 
0438         if ((written % 4) == 0)
0439             nxt200x_writebytes(state, chunkpos, &fw->data[position-3], 4);
0440 
0441         crc = nxt200x_crc(crc, fw->data[position]);
0442 
0443         if ((written == 255) || (position+1 == fw->size)) {
0444             /* write remaining bytes of firmware */
0445             nxt200x_writebytes(state, chunkpos+4-(written %4),
0446                 &fw->data[position-(written %4) + 1],
0447                 written %4);
0448             buf[0] = crc << 8;
0449             buf[1] = crc & 0xFF;
0450 
0451             /* write crc */
0452             nxt200x_writebytes(state, 0x2C, buf, 2);
0453 
0454             /* do a read to stop things */
0455             nxt200x_readbytes(state, 0x2A, buf, 1);
0456 
0457             /* set transfer mode to complete */
0458             buf[0] = 0x80;
0459             nxt200x_writebytes(state, 0x2B, buf, 1);
0460 
0461             written = 0;
0462         }
0463     }
0464 
0465     return 0;
0466 };
0467 
0468 static int nxt2004_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
0469 {
0470 
0471     struct nxt200x_state* state = fe->demodulator_priv;
0472     u8 buf[3];
0473     u16 rambase, position, crc=0;
0474 
0475     dprintk("%s\n", __func__);
0476     dprintk("Firmware is %zu bytes\n", fw->size);
0477 
0478     /* set rambase */
0479     rambase = 0x1000;
0480 
0481     /* hold the micro in reset while loading firmware */
0482     buf[0] = 0x80;
0483     nxt200x_writebytes(state, 0x2B, buf,1);
0484 
0485     /* calculate firmware CRC */
0486     for (position = 0; position < fw->size; position++) {
0487         crc = nxt200x_crc(crc, fw->data[position]);
0488     }
0489 
0490     buf[0] = rambase >> 8;
0491     buf[1] = rambase & 0xFF;
0492     buf[2] = 0x81;
0493     /* write starting address */
0494     nxt200x_writebytes(state,0x29,buf,3);
0495 
0496     for (position = 0; position < fw->size;) {
0497         nxt200x_writebytes(state, 0x2C, &fw->data[position],
0498             fw->size-position > 255 ? 255 : fw->size-position);
0499         position += (fw->size-position > 255 ? 255 : fw->size-position);
0500     }
0501     buf[0] = crc >> 8;
0502     buf[1] = crc & 0xFF;
0503 
0504     dprintk("firmware crc is 0x%02X 0x%02X\n", buf[0], buf[1]);
0505 
0506     /* write crc */
0507     nxt200x_writebytes(state, 0x2C, buf,2);
0508 
0509     /* do a read to stop things */
0510     nxt200x_readbytes(state, 0x2C, buf, 1);
0511 
0512     /* set transfer mode to complete */
0513     buf[0] = 0x80;
0514     nxt200x_writebytes(state, 0x2B, buf,1);
0515 
0516     return 0;
0517 };
0518 
0519 static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe)
0520 {
0521     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0522     struct nxt200x_state* state = fe->demodulator_priv;
0523     u8 buf[5];
0524 
0525     /* stop the micro first */
0526     nxt200x_microcontroller_stop(state);
0527 
0528     if (state->demod_chip == NXT2004) {
0529         /* make sure demod is set to digital */
0530         buf[0] = 0x04;
0531         nxt200x_writebytes(state, 0x14, buf, 1);
0532         buf[0] = 0x00;
0533         nxt200x_writebytes(state, 0x17, buf, 1);
0534     }
0535 
0536     /* set additional params */
0537     switch (p->modulation) {
0538         case QAM_64:
0539         case QAM_256:
0540             /* Set punctured clock for QAM */
0541             /* This is just a guess since I am unable to test it */
0542             if (state->config->set_ts_params)
0543                 state->config->set_ts_params(fe, 1);
0544             break;
0545         case VSB_8:
0546             /* Set non-punctured clock for VSB */
0547             if (state->config->set_ts_params)
0548                 state->config->set_ts_params(fe, 0);
0549             break;
0550         default:
0551             return -EINVAL;
0552     }
0553 
0554     if (fe->ops.tuner_ops.calc_regs) {
0555         /* get tuning information */
0556         fe->ops.tuner_ops.calc_regs(fe, buf, 5);
0557 
0558         /* write frequency information */
0559         nxt200x_writetuner(state, buf);
0560     }
0561 
0562     /* reset the agc now that tuning has been completed */
0563     nxt200x_agc_reset(state);
0564 
0565     /* set target power level */
0566     switch (p->modulation) {
0567         case QAM_64:
0568         case QAM_256:
0569             buf[0] = 0x74;
0570             break;
0571         case VSB_8:
0572             buf[0] = 0x70;
0573             break;
0574         default:
0575             return -EINVAL;
0576     }
0577     nxt200x_writebytes(state, 0x42, buf, 1);
0578 
0579     /* configure sdm */
0580     switch (state->demod_chip) {
0581         case NXT2002:
0582             buf[0] = 0x87;
0583             break;
0584         case NXT2004:
0585             buf[0] = 0x07;
0586             break;
0587         default:
0588             return -EINVAL;
0589     }
0590     nxt200x_writebytes(state, 0x57, buf, 1);
0591 
0592     /* write sdm1 input */
0593     buf[0] = 0x10;
0594     buf[1] = 0x00;
0595     switch (state->demod_chip) {
0596         case NXT2002:
0597             nxt200x_writereg_multibyte(state, 0x58, buf, 2);
0598             break;
0599         case NXT2004:
0600             nxt200x_writebytes(state, 0x58, buf, 2);
0601             break;
0602         default:
0603             return -EINVAL;
0604     }
0605 
0606     /* write sdmx input */
0607     switch (p->modulation) {
0608         case QAM_64:
0609                 buf[0] = 0x68;
0610                 break;
0611         case QAM_256:
0612                 buf[0] = 0x64;
0613                 break;
0614         case VSB_8:
0615                 buf[0] = 0x60;
0616                 break;
0617         default:
0618                 return -EINVAL;
0619     }
0620     buf[1] = 0x00;
0621     switch (state->demod_chip) {
0622         case NXT2002:
0623             nxt200x_writereg_multibyte(state, 0x5C, buf, 2);
0624             break;
0625         case NXT2004:
0626             nxt200x_writebytes(state, 0x5C, buf, 2);
0627             break;
0628         default:
0629             return -EINVAL;
0630     }
0631 
0632     /* write adc power lpf fc */
0633     buf[0] = 0x05;
0634     nxt200x_writebytes(state, 0x43, buf, 1);
0635 
0636     if (state->demod_chip == NXT2004) {
0637         /* write ??? */
0638         buf[0] = 0x00;
0639         buf[1] = 0x00;
0640         nxt200x_writebytes(state, 0x46, buf, 2);
0641     }
0642 
0643     /* write accumulator2 input */
0644     buf[0] = 0x80;
0645     buf[1] = 0x00;
0646     switch (state->demod_chip) {
0647         case NXT2002:
0648             nxt200x_writereg_multibyte(state, 0x4B, buf, 2);
0649             break;
0650         case NXT2004:
0651             nxt200x_writebytes(state, 0x4B, buf, 2);
0652             break;
0653         default:
0654             return -EINVAL;
0655     }
0656 
0657     /* write kg1 */
0658     buf[0] = 0x00;
0659     nxt200x_writebytes(state, 0x4D, buf, 1);
0660 
0661     /* write sdm12 lpf fc */
0662     buf[0] = 0x44;
0663     nxt200x_writebytes(state, 0x55, buf, 1);
0664 
0665     /* write agc control reg */
0666     buf[0] = 0x04;
0667     nxt200x_writebytes(state, 0x41, buf, 1);
0668 
0669     if (state->demod_chip == NXT2004) {
0670         nxt200x_readreg_multibyte(state, 0x80, buf, 1);
0671         buf[0] = 0x24;
0672         nxt200x_writereg_multibyte(state, 0x80, buf, 1);
0673 
0674         /* soft reset? */
0675         nxt200x_readreg_multibyte(state, 0x08, buf, 1);
0676         buf[0] = 0x10;
0677         nxt200x_writereg_multibyte(state, 0x08, buf, 1);
0678         nxt200x_readreg_multibyte(state, 0x08, buf, 1);
0679         buf[0] = 0x00;
0680         nxt200x_writereg_multibyte(state, 0x08, buf, 1);
0681 
0682         nxt200x_readreg_multibyte(state, 0x80, buf, 1);
0683         buf[0] = 0x04;
0684         nxt200x_writereg_multibyte(state, 0x80, buf, 1);
0685         buf[0] = 0x00;
0686         nxt200x_writereg_multibyte(state, 0x81, buf, 1);
0687         buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00;
0688         nxt200x_writereg_multibyte(state, 0x82, buf, 3);
0689         nxt200x_readreg_multibyte(state, 0x88, buf, 1);
0690         buf[0] = 0x11;
0691         nxt200x_writereg_multibyte(state, 0x88, buf, 1);
0692         nxt200x_readreg_multibyte(state, 0x80, buf, 1);
0693         buf[0] = 0x44;
0694         nxt200x_writereg_multibyte(state, 0x80, buf, 1);
0695     }
0696 
0697     /* write agc ucgp0 */
0698     switch (p->modulation) {
0699         case QAM_64:
0700                 buf[0] = 0x02;
0701                 break;
0702         case QAM_256:
0703                 buf[0] = 0x03;
0704                 break;
0705         case VSB_8:
0706                 buf[0] = 0x00;
0707                 break;
0708         default:
0709                 return -EINVAL;
0710     }
0711     nxt200x_writebytes(state, 0x30, buf, 1);
0712 
0713     /* write agc control reg */
0714     buf[0] = 0x00;
0715     nxt200x_writebytes(state, 0x41, buf, 1);
0716 
0717     /* write accumulator2 input */
0718     buf[0] = 0x80;
0719     buf[1] = 0x00;
0720     switch (state->demod_chip) {
0721         case NXT2002:
0722             nxt200x_writereg_multibyte(state, 0x49, buf, 2);
0723             nxt200x_writereg_multibyte(state, 0x4B, buf, 2);
0724             break;
0725         case NXT2004:
0726             nxt200x_writebytes(state, 0x49, buf, 2);
0727             nxt200x_writebytes(state, 0x4B, buf, 2);
0728             break;
0729         default:
0730             return -EINVAL;
0731     }
0732 
0733     /* write agc control reg */
0734     buf[0] = 0x04;
0735     nxt200x_writebytes(state, 0x41, buf, 1);
0736 
0737     nxt200x_microcontroller_start(state);
0738 
0739     if (state->demod_chip == NXT2004) {
0740         nxt2004_microcontroller_init(state);
0741 
0742         /* ???? */
0743         buf[0] = 0xF0;
0744         buf[1] = 0x00;
0745         nxt200x_writebytes(state, 0x5C, buf, 2);
0746     }
0747 
0748     /* adjacent channel detection should be done here, but I don't
0749     have any stations with this need so I cannot test it */
0750 
0751     return 0;
0752 }
0753 
0754 static int nxt200x_read_status(struct dvb_frontend *fe, enum fe_status *status)
0755 {
0756     struct nxt200x_state* state = fe->demodulator_priv;
0757     u8 lock;
0758     nxt200x_readbytes(state, 0x31, &lock, 1);
0759 
0760     *status = 0;
0761     if (lock & 0x20) {
0762         *status |= FE_HAS_SIGNAL;
0763         *status |= FE_HAS_CARRIER;
0764         *status |= FE_HAS_VITERBI;
0765         *status |= FE_HAS_SYNC;
0766         *status |= FE_HAS_LOCK;
0767     }
0768     return 0;
0769 }
0770 
0771 static int nxt200x_read_ber(struct dvb_frontend* fe, u32* ber)
0772 {
0773     struct nxt200x_state* state = fe->demodulator_priv;
0774     u8 b[3];
0775 
0776     nxt200x_readreg_multibyte(state, 0xE6, b, 3);
0777 
0778     *ber = ((b[0] << 8) + b[1]) * 8;
0779 
0780     return 0;
0781 }
0782 
0783 static int nxt200x_read_signal_strength(struct dvb_frontend* fe, u16* strength)
0784 {
0785     struct nxt200x_state* state = fe->demodulator_priv;
0786     u8 b[2];
0787     u16 temp = 0;
0788 
0789     /* setup to read cluster variance */
0790     b[0] = 0x00;
0791     nxt200x_writebytes(state, 0xA1, b, 1);
0792 
0793     /* get multreg val */
0794     nxt200x_readreg_multibyte(state, 0xA6, b, 2);
0795 
0796     temp = (b[0] << 8) | b[1];
0797     *strength = ((0x7FFF - temp) & 0x0FFF) * 16;
0798 
0799     return 0;
0800 }
0801 
0802 static int nxt200x_read_snr(struct dvb_frontend* fe, u16* snr)
0803 {
0804 
0805     struct nxt200x_state* state = fe->demodulator_priv;
0806     u8 b[2];
0807     u16 temp = 0, temp2;
0808     u32 snrdb = 0;
0809 
0810     /* setup to read cluster variance */
0811     b[0] = 0x00;
0812     nxt200x_writebytes(state, 0xA1, b, 1);
0813 
0814     /* get multreg val from 0xA6 */
0815     nxt200x_readreg_multibyte(state, 0xA6, b, 2);
0816 
0817     temp = (b[0] << 8) | b[1];
0818     temp2 = 0x7FFF - temp;
0819 
0820     /* snr will be in db */
0821     if (temp2 > 0x7F00)
0822         snrdb = 1000*24 + ( 1000*(30-24) * ( temp2 - 0x7F00 ) / ( 0x7FFF - 0x7F00 ) );
0823     else if (temp2 > 0x7EC0)
0824         snrdb = 1000*18 + ( 1000*(24-18) * ( temp2 - 0x7EC0 ) / ( 0x7F00 - 0x7EC0 ) );
0825     else if (temp2 > 0x7C00)
0826         snrdb = 1000*12 + ( 1000*(18-12) * ( temp2 - 0x7C00 ) / ( 0x7EC0 - 0x7C00 ) );
0827     else
0828         snrdb = 1000*0 + ( 1000*(12-0) * ( temp2 - 0 ) / ( 0x7C00 - 0 ) );
0829 
0830     /* the value reported back from the frontend will be FFFF=32db 0000=0db */
0831     *snr = snrdb * (0xFFFF/32000);
0832 
0833     return 0;
0834 }
0835 
0836 static int nxt200x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
0837 {
0838     struct nxt200x_state* state = fe->demodulator_priv;
0839     u8 b[3];
0840 
0841     nxt200x_readreg_multibyte(state, 0xE6, b, 3);
0842     *ucblocks = b[2];
0843 
0844     return 0;
0845 }
0846 
0847 static int nxt200x_sleep(struct dvb_frontend* fe)
0848 {
0849     return 0;
0850 }
0851 
0852 static int nxt2002_init(struct dvb_frontend* fe)
0853 {
0854     struct nxt200x_state* state = fe->demodulator_priv;
0855     const struct firmware *fw;
0856     int ret;
0857     u8 buf[2];
0858 
0859     /* request the firmware, this will block until someone uploads it */
0860     pr_debug("%s: Waiting for firmware upload (%s)...\n",
0861          __func__, NXT2002_DEFAULT_FIRMWARE);
0862     ret = request_firmware(&fw, NXT2002_DEFAULT_FIRMWARE,
0863                    state->i2c->dev.parent);
0864     pr_debug("%s: Waiting for firmware upload(2)...\n", __func__);
0865     if (ret) {
0866         pr_err("%s: No firmware uploaded (timeout or file not found?)\n",
0867                __func__);
0868         return ret;
0869     }
0870 
0871     ret = nxt2002_load_firmware(fe, fw);
0872     release_firmware(fw);
0873     if (ret) {
0874         pr_err("%s: Writing firmware to device failed\n", __func__);
0875         return ret;
0876     }
0877     pr_info("%s: Firmware upload complete\n", __func__);
0878 
0879     /* Put the micro into reset */
0880     nxt200x_microcontroller_stop(state);
0881 
0882     /* ensure transfer is complete */
0883     buf[0]=0x00;
0884     nxt200x_writebytes(state, 0x2B, buf, 1);
0885 
0886     /* Put the micro into reset for real this time */
0887     nxt200x_microcontroller_stop(state);
0888 
0889     /* soft reset everything (agc,frontend,eq,fec)*/
0890     buf[0] = 0x0F;
0891     nxt200x_writebytes(state, 0x08, buf, 1);
0892     buf[0] = 0x00;
0893     nxt200x_writebytes(state, 0x08, buf, 1);
0894 
0895     /* write agc sdm configure */
0896     buf[0] = 0xF1;
0897     nxt200x_writebytes(state, 0x57, buf, 1);
0898 
0899     /* write mod output format */
0900     buf[0] = 0x20;
0901     nxt200x_writebytes(state, 0x09, buf, 1);
0902 
0903     /* write fec mpeg mode */
0904     buf[0] = 0x7E;
0905     buf[1] = 0x00;
0906     nxt200x_writebytes(state, 0xE9, buf, 2);
0907 
0908     /* write mux selection */
0909     buf[0] = 0x00;
0910     nxt200x_writebytes(state, 0xCC, buf, 1);
0911 
0912     return 0;
0913 }
0914 
0915 static int nxt2004_init(struct dvb_frontend* fe)
0916 {
0917     struct nxt200x_state* state = fe->demodulator_priv;
0918     const struct firmware *fw;
0919     int ret;
0920     u8 buf[3];
0921 
0922     /* ??? */
0923     buf[0]=0x00;
0924     nxt200x_writebytes(state, 0x1E, buf, 1);
0925 
0926     /* request the firmware, this will block until someone uploads it */
0927     pr_debug("%s: Waiting for firmware upload (%s)...\n",
0928          __func__, NXT2004_DEFAULT_FIRMWARE);
0929     ret = request_firmware(&fw, NXT2004_DEFAULT_FIRMWARE,
0930                    state->i2c->dev.parent);
0931     pr_debug("%s: Waiting for firmware upload(2)...\n", __func__);
0932     if (ret) {
0933         pr_err("%s: No firmware uploaded (timeout or file not found?)\n",
0934                __func__);
0935         return ret;
0936     }
0937 
0938     ret = nxt2004_load_firmware(fe, fw);
0939     release_firmware(fw);
0940     if (ret) {
0941         pr_err("%s: Writing firmware to device failed\n", __func__);
0942         return ret;
0943     }
0944     pr_info("%s: Firmware upload complete\n", __func__);
0945 
0946     /* ensure transfer is complete */
0947     buf[0] = 0x01;
0948     nxt200x_writebytes(state, 0x19, buf, 1);
0949 
0950     nxt2004_microcontroller_init(state);
0951     nxt200x_microcontroller_stop(state);
0952     nxt200x_microcontroller_stop(state);
0953     nxt2004_microcontroller_init(state);
0954     nxt200x_microcontroller_stop(state);
0955 
0956     /* soft reset everything (agc,frontend,eq,fec)*/
0957     buf[0] = 0xFF;
0958     nxt200x_writereg_multibyte(state, 0x08, buf, 1);
0959     buf[0] = 0x00;
0960     nxt200x_writereg_multibyte(state, 0x08, buf, 1);
0961 
0962     /* write agc sdm configure */
0963     buf[0] = 0xD7;
0964     nxt200x_writebytes(state, 0x57, buf, 1);
0965 
0966     /* ???*/
0967     buf[0] = 0x07;
0968     buf[1] = 0xfe;
0969     nxt200x_writebytes(state, 0x35, buf, 2);
0970     buf[0] = 0x12;
0971     nxt200x_writebytes(state, 0x34, buf, 1);
0972     buf[0] = 0x80;
0973     nxt200x_writebytes(state, 0x21, buf, 1);
0974 
0975     /* ???*/
0976     buf[0] = 0x21;
0977     nxt200x_writebytes(state, 0x0A, buf, 1);
0978 
0979     /* ???*/
0980     buf[0] = 0x01;
0981     nxt200x_writereg_multibyte(state, 0x80, buf, 1);
0982 
0983     /* write fec mpeg mode */
0984     buf[0] = 0x7E;
0985     buf[1] = 0x00;
0986     nxt200x_writebytes(state, 0xE9, buf, 2);
0987 
0988     /* write mux selection */
0989     buf[0] = 0x00;
0990     nxt200x_writebytes(state, 0xCC, buf, 1);
0991 
0992     /* ???*/
0993     nxt200x_readreg_multibyte(state, 0x80, buf, 1);
0994     buf[0] = 0x00;
0995     nxt200x_writereg_multibyte(state, 0x80, buf, 1);
0996 
0997     /* soft reset? */
0998     nxt200x_readreg_multibyte(state, 0x08, buf, 1);
0999     buf[0] = 0x10;
1000     nxt200x_writereg_multibyte(state, 0x08, buf, 1);
1001     nxt200x_readreg_multibyte(state, 0x08, buf, 1);
1002     buf[0] = 0x00;
1003     nxt200x_writereg_multibyte(state, 0x08, buf, 1);
1004 
1005     /* ???*/
1006     nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1007     buf[0] = 0x01;
1008     nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1009     buf[0] = 0x70;
1010     nxt200x_writereg_multibyte(state, 0x81, buf, 1);
1011     buf[0] = 0x31; buf[1] = 0x5E; buf[2] = 0x66;
1012     nxt200x_writereg_multibyte(state, 0x82, buf, 3);
1013 
1014     nxt200x_readreg_multibyte(state, 0x88, buf, 1);
1015     buf[0] = 0x11;
1016     nxt200x_writereg_multibyte(state, 0x88, buf, 1);
1017     nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1018     buf[0] = 0x40;
1019     nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1020 
1021     nxt200x_readbytes(state, 0x10, buf, 1);
1022     buf[0] = 0x10;
1023     nxt200x_writebytes(state, 0x10, buf, 1);
1024     nxt200x_readbytes(state, 0x0A, buf, 1);
1025     buf[0] = 0x21;
1026     nxt200x_writebytes(state, 0x0A, buf, 1);
1027 
1028     nxt2004_microcontroller_init(state);
1029 
1030     buf[0] = 0x21;
1031     nxt200x_writebytes(state, 0x0A, buf, 1);
1032     buf[0] = 0x7E;
1033     nxt200x_writebytes(state, 0xE9, buf, 1);
1034     buf[0] = 0x00;
1035     nxt200x_writebytes(state, 0xEA, buf, 1);
1036 
1037     nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1038     buf[0] = 0x00;
1039     nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1040     nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1041     buf[0] = 0x00;
1042     nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1043 
1044     /* soft reset? */
1045     nxt200x_readreg_multibyte(state, 0x08, buf, 1);
1046     buf[0] = 0x10;
1047     nxt200x_writereg_multibyte(state, 0x08, buf, 1);
1048     nxt200x_readreg_multibyte(state, 0x08, buf, 1);
1049     buf[0] = 0x00;
1050     nxt200x_writereg_multibyte(state, 0x08, buf, 1);
1051 
1052     nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1053     buf[0] = 0x04;
1054     nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1055     buf[0] = 0x00;
1056     nxt200x_writereg_multibyte(state, 0x81, buf, 1);
1057     buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00;
1058     nxt200x_writereg_multibyte(state, 0x82, buf, 3);
1059 
1060     nxt200x_readreg_multibyte(state, 0x88, buf, 1);
1061     buf[0] = 0x11;
1062     nxt200x_writereg_multibyte(state, 0x88, buf, 1);
1063 
1064     nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1065     buf[0] = 0x44;
1066     nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1067 
1068     /* initialize tuner */
1069     nxt200x_readbytes(state, 0x10, buf, 1);
1070     buf[0] = 0x12;
1071     nxt200x_writebytes(state, 0x10, buf, 1);
1072     buf[0] = 0x04;
1073     nxt200x_writebytes(state, 0x13, buf, 1);
1074     buf[0] = 0x00;
1075     nxt200x_writebytes(state, 0x16, buf, 1);
1076     buf[0] = 0x04;
1077     nxt200x_writebytes(state, 0x14, buf, 1);
1078     buf[0] = 0x00;
1079     nxt200x_writebytes(state, 0x14, buf, 1);
1080     nxt200x_writebytes(state, 0x17, buf, 1);
1081     nxt200x_writebytes(state, 0x14, buf, 1);
1082     nxt200x_writebytes(state, 0x17, buf, 1);
1083 
1084     return 0;
1085 }
1086 
1087 static int nxt200x_init(struct dvb_frontend* fe)
1088 {
1089     struct nxt200x_state* state = fe->demodulator_priv;
1090     int ret = 0;
1091 
1092     if (!state->initialised) {
1093         switch (state->demod_chip) {
1094             case NXT2002:
1095                 ret = nxt2002_init(fe);
1096                 break;
1097             case NXT2004:
1098                 ret = nxt2004_init(fe);
1099                 break;
1100             default:
1101                 return -EINVAL;
1102         }
1103         state->initialised = 1;
1104     }
1105     return ret;
1106 }
1107 
1108 static int nxt200x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1109 {
1110     fesettings->min_delay_ms = 500;
1111     fesettings->step_size = 0;
1112     fesettings->max_drift = 0;
1113     return 0;
1114 }
1115 
1116 static void nxt200x_release(struct dvb_frontend* fe)
1117 {
1118     struct nxt200x_state* state = fe->demodulator_priv;
1119     kfree(state);
1120 }
1121 
1122 static const struct dvb_frontend_ops nxt200x_ops;
1123 
1124 struct dvb_frontend* nxt200x_attach(const struct nxt200x_config* config,
1125                    struct i2c_adapter* i2c)
1126 {
1127     struct nxt200x_state* state = NULL;
1128     u8 buf [] = {0,0,0,0,0};
1129 
1130     /* allocate memory for the internal state */
1131     state = kzalloc(sizeof(struct nxt200x_state), GFP_KERNEL);
1132     if (state == NULL)
1133         goto error;
1134 
1135     /* setup the state */
1136     state->config = config;
1137     state->i2c = i2c;
1138     state->initialised = 0;
1139 
1140     /* read card id */
1141     nxt200x_readbytes(state, 0x00, buf, 5);
1142     dprintk("NXT info: %*ph\n", 5, buf);
1143 
1144     /* set demod chip */
1145     switch (buf[0]) {
1146         case 0x04:
1147             state->demod_chip = NXT2002;
1148             pr_info("NXT2002 Detected\n");
1149             break;
1150         case 0x05:
1151             state->demod_chip = NXT2004;
1152             pr_info("NXT2004 Detected\n");
1153             break;
1154         default:
1155             goto error;
1156     }
1157 
1158     /* make sure demod chip is supported */
1159     switch (state->demod_chip) {
1160         case NXT2002:
1161             if (buf[0] != 0x04) goto error;     /* device id */
1162             if (buf[1] != 0x02) goto error;     /* fab id */
1163             if (buf[2] != 0x11) goto error;     /* month */
1164             if (buf[3] != 0x20) goto error;     /* year msb */
1165             if (buf[4] != 0x00) goto error;     /* year lsb */
1166             break;
1167         case NXT2004:
1168             if (buf[0] != 0x05) goto error;     /* device id */
1169             break;
1170         default:
1171             goto error;
1172     }
1173 
1174     /* create dvb_frontend */
1175     memcpy(&state->frontend.ops, &nxt200x_ops, sizeof(struct dvb_frontend_ops));
1176     state->frontend.demodulator_priv = state;
1177     return &state->frontend;
1178 
1179 error:
1180     kfree(state);
1181     pr_err("Unknown/Unsupported NXT chip: %*ph\n", 5, buf);
1182     return NULL;
1183 }
1184 
1185 static const struct dvb_frontend_ops nxt200x_ops = {
1186     .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1187     .info = {
1188         .name = "Nextwave NXT200X VSB/QAM frontend",
1189         .frequency_min_hz =  54 * MHz,
1190         .frequency_max_hz = 860 * MHz,
1191         .frequency_stepsize_hz = 166666,    /* stepsize is just a guess */
1192         .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1193             FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1194             FE_CAN_8VSB | FE_CAN_QAM_64 | FE_CAN_QAM_256
1195     },
1196 
1197     .release = nxt200x_release,
1198 
1199     .init = nxt200x_init,
1200     .sleep = nxt200x_sleep,
1201 
1202     .set_frontend = nxt200x_setup_frontend_parameters,
1203     .get_tune_settings = nxt200x_get_tune_settings,
1204 
1205     .read_status = nxt200x_read_status,
1206     .read_ber = nxt200x_read_ber,
1207     .read_signal_strength = nxt200x_read_signal_strength,
1208     .read_snr = nxt200x_read_snr,
1209     .read_ucblocks = nxt200x_read_ucblocks,
1210 };
1211 
1212 module_param(debug, int, 0644);
1213 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1214 
1215 MODULE_DESCRIPTION("NXT200X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver");
1216 MODULE_AUTHOR("Kirk Lapray, Michael Krufky, Jean-Francois Thibert, and Taylor Jacob");
1217 MODULE_LICENSE("GPL");
1218 
1219 EXPORT_SYMBOL(nxt200x_attach);
1220
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