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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for the MaxLinear MxL5xx family of tuners/demods
0004  *
0005  * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>
0006  *                         Marcus Metzler <mocm@metzlerbros.de>
0007  *                         developed for Digital Devices GmbH
0008  *
0009  * based on code:
0010  * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
0011  * which was released under GPL V2
0012  */
0013 
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/moduleparam.h>
0017 #include <linux/init.h>
0018 #include <linux/delay.h>
0019 #include <linux/firmware.h>
0020 #include <linux/i2c.h>
0021 #include <linux/mutex.h>
0022 #include <linux/vmalloc.h>
0023 #include <asm/div64.h>
0024 #include <asm/unaligned.h>
0025 
0026 #include <media/dvb_frontend.h>
0027 #include "mxl5xx.h"
0028 #include "mxl5xx_regs.h"
0029 #include "mxl5xx_defs.h"
0030 
0031 #define BYTE0(v) ((v >>  0) & 0xff)
0032 #define BYTE1(v) ((v >>  8) & 0xff)
0033 #define BYTE2(v) ((v >> 16) & 0xff)
0034 #define BYTE3(v) ((v >> 24) & 0xff)
0035 
0036 static LIST_HEAD(mxllist);
0037 
0038 struct mxl_base {
0039     struct list_head     mxllist;
0040     struct list_head     mxls;
0041 
0042     u8                   adr;
0043     struct i2c_adapter  *i2c;
0044 
0045     u32                  count;
0046     u32                  type;
0047     u32                  sku_type;
0048     u32                  chipversion;
0049     u32                  clock;
0050     u32                  fwversion;
0051 
0052     u8                  *ts_map;
0053     u8                   can_clkout;
0054     u8                   chan_bond;
0055     u8                   demod_num;
0056     u8                   tuner_num;
0057 
0058     unsigned long        next_tune;
0059 
0060     struct mutex         i2c_lock;
0061     struct mutex         status_lock;
0062     struct mutex         tune_lock;
0063 
0064     u8                   buf[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
0065 
0066     u32                  cmd_size;
0067     u8                   cmd_data[MAX_CMD_DATA];
0068 };
0069 
0070 struct mxl {
0071     struct list_head     mxl;
0072 
0073     struct mxl_base     *base;
0074     struct dvb_frontend  fe;
0075     struct device       *i2cdev;
0076     u32                  demod;
0077     u32                  tuner;
0078     u32                  tuner_in_use;
0079     u8                   xbar[3];
0080 
0081     unsigned long        tune_time;
0082 };
0083 
0084 static void convert_endian(u8 flag, u32 size, u8 *d)
0085 {
0086     u32 i;
0087 
0088     if (!flag)
0089         return;
0090     for (i = 0; i < (size & ~3); i += 4) {
0091         d[i + 0] ^= d[i + 3];
0092         d[i + 3] ^= d[i + 0];
0093         d[i + 0] ^= d[i + 3];
0094 
0095         d[i + 1] ^= d[i + 2];
0096         d[i + 2] ^= d[i + 1];
0097         d[i + 1] ^= d[i + 2];
0098     }
0099 
0100     switch (size & 3) {
0101     case 0:
0102     case 1:
0103         /* do nothing */
0104         break;
0105     case 2:
0106         d[i + 0] ^= d[i + 1];
0107         d[i + 1] ^= d[i + 0];
0108         d[i + 0] ^= d[i + 1];
0109         break;
0110 
0111     case 3:
0112         d[i + 0] ^= d[i + 2];
0113         d[i + 2] ^= d[i + 0];
0114         d[i + 0] ^= d[i + 2];
0115         break;
0116     }
0117 
0118 }
0119 
0120 static int i2c_write(struct i2c_adapter *adap, u8 adr,
0121                 u8 *data, u32 len)
0122 {
0123     struct i2c_msg msg = {.addr = adr, .flags = 0,
0124                   .buf = data, .len = len};
0125 
0126     return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1;
0127 }
0128 
0129 static int i2c_read(struct i2c_adapter *adap, u8 adr,
0130                u8 *data, u32 len)
0131 {
0132     struct i2c_msg msg = {.addr = adr, .flags = I2C_M_RD,
0133                   .buf = data, .len = len};
0134 
0135     return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1;
0136 }
0137 
0138 static int i2cread(struct mxl *state, u8 *data, int len)
0139 {
0140     return i2c_read(state->base->i2c, state->base->adr, data, len);
0141 }
0142 
0143 static int i2cwrite(struct mxl *state, u8 *data, int len)
0144 {
0145     return i2c_write(state->base->i2c, state->base->adr, data, len);
0146 }
0147 
0148 static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val)
0149 {
0150     int stat;
0151     u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = {
0152         MXL_HYDRA_PLID_REG_READ, 0x04,
0153         GET_BYTE(reg, 0), GET_BYTE(reg, 1),
0154         GET_BYTE(reg, 2), GET_BYTE(reg, 3),
0155     };
0156 
0157     stat = i2cwrite(state, data,
0158             MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE);
0159     if (stat)
0160         dev_err(state->i2cdev, "i2c read error 1\n");
0161     if (!stat)
0162         stat = i2cread(state, (u8 *) val,
0163                    MXL_HYDRA_REG_SIZE_IN_BYTES);
0164     le32_to_cpus(val);
0165     if (stat)
0166         dev_err(state->i2cdev, "i2c read error 2\n");
0167     return stat;
0168 }
0169 
0170 #define DMA_I2C_INTERRUPT_ADDR 0x8000011C
0171 #define DMA_INTR_PROT_WR_CMP 0x08
0172 
0173 static int send_command(struct mxl *state, u32 size, u8 *buf)
0174 {
0175     int stat;
0176     u32 val, count = 10;
0177 
0178     mutex_lock(&state->base->i2c_lock);
0179     if (state->base->fwversion > 0x02010109)  {
0180         read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val);
0181         if (DMA_INTR_PROT_WR_CMP & val)
0182             dev_info(state->i2cdev, "%s busy\n", __func__);
0183         while ((DMA_INTR_PROT_WR_CMP & val) && --count) {
0184             mutex_unlock(&state->base->i2c_lock);
0185             usleep_range(1000, 2000);
0186             mutex_lock(&state->base->i2c_lock);
0187             read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR,
0188                            &val);
0189         }
0190         if (!count) {
0191             dev_info(state->i2cdev, "%s busy\n", __func__);
0192             mutex_unlock(&state->base->i2c_lock);
0193             return -EBUSY;
0194         }
0195     }
0196     stat = i2cwrite(state, buf, size);
0197     mutex_unlock(&state->base->i2c_lock);
0198     return stat;
0199 }
0200 
0201 static int write_register(struct mxl *state, u32 reg, u32 val)
0202 {
0203     int stat;
0204     u8 data[MXL_HYDRA_REG_WRITE_LEN] = {
0205         MXL_HYDRA_PLID_REG_WRITE, 0x08,
0206         BYTE0(reg), BYTE1(reg), BYTE2(reg), BYTE3(reg),
0207         BYTE0(val), BYTE1(val), BYTE2(val), BYTE3(val),
0208     };
0209     mutex_lock(&state->base->i2c_lock);
0210     stat = i2cwrite(state, data, sizeof(data));
0211     mutex_unlock(&state->base->i2c_lock);
0212     if (stat)
0213         dev_err(state->i2cdev, "i2c write error\n");
0214     return stat;
0215 }
0216 
0217 static int write_firmware_block(struct mxl *state,
0218                 u32 reg, u32 size, u8 *reg_data_ptr)
0219 {
0220     int stat;
0221     u8 *buf = state->base->buf;
0222 
0223     mutex_lock(&state->base->i2c_lock);
0224     buf[0] = MXL_HYDRA_PLID_REG_WRITE;
0225     buf[1] = size + 4;
0226     buf[2] = GET_BYTE(reg, 0);
0227     buf[3] = GET_BYTE(reg, 1);
0228     buf[4] = GET_BYTE(reg, 2);
0229     buf[5] = GET_BYTE(reg, 3);
0230     memcpy(&buf[6], reg_data_ptr, size);
0231     stat = i2cwrite(state, buf,
0232             MXL_HYDRA_I2C_HDR_SIZE +
0233             MXL_HYDRA_REG_SIZE_IN_BYTES + size);
0234     mutex_unlock(&state->base->i2c_lock);
0235     if (stat)
0236         dev_err(state->i2cdev, "fw block write failed\n");
0237     return stat;
0238 }
0239 
0240 static int read_register(struct mxl *state, u32 reg, u32 *val)
0241 {
0242     int stat;
0243     u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = {
0244         MXL_HYDRA_PLID_REG_READ, 0x04,
0245         GET_BYTE(reg, 0), GET_BYTE(reg, 1),
0246         GET_BYTE(reg, 2), GET_BYTE(reg, 3),
0247     };
0248 
0249     mutex_lock(&state->base->i2c_lock);
0250     stat = i2cwrite(state, data,
0251             MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE);
0252     if (stat)
0253         dev_err(state->i2cdev, "i2c read error 1\n");
0254     if (!stat)
0255         stat = i2cread(state, (u8 *) val,
0256                    MXL_HYDRA_REG_SIZE_IN_BYTES);
0257     mutex_unlock(&state->base->i2c_lock);
0258     le32_to_cpus(val);
0259     if (stat)
0260         dev_err(state->i2cdev, "i2c read error 2\n");
0261     return stat;
0262 }
0263 
0264 static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data)
0265 {
0266     int stat;
0267     u8 *buf = state->base->buf;
0268 
0269     mutex_lock(&state->base->i2c_lock);
0270 
0271     buf[0] = MXL_HYDRA_PLID_REG_READ;
0272     buf[1] = size + 4;
0273     buf[2] = GET_BYTE(reg, 0);
0274     buf[3] = GET_BYTE(reg, 1);
0275     buf[4] = GET_BYTE(reg, 2);
0276     buf[5] = GET_BYTE(reg, 3);
0277     stat = i2cwrite(state, buf,
0278             MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES);
0279     if (!stat) {
0280         stat = i2cread(state, data, size);
0281         convert_endian(MXL_ENABLE_BIG_ENDIAN, size, data);
0282     }
0283     mutex_unlock(&state->base->i2c_lock);
0284     return stat;
0285 }
0286 
0287 static int read_by_mnemonic(struct mxl *state,
0288                 u32 reg, u8 lsbloc, u8 numofbits, u32 *val)
0289 {
0290     u32 data = 0, mask = 0;
0291     int stat;
0292 
0293     stat = read_register(state, reg, &data);
0294     if (stat)
0295         return stat;
0296     mask = MXL_GET_REG_MASK_32(lsbloc, numofbits);
0297     data &= mask;
0298     data >>= lsbloc;
0299     *val = data;
0300     return 0;
0301 }
0302 
0303 
0304 static int update_by_mnemonic(struct mxl *state,
0305                   u32 reg, u8 lsbloc, u8 numofbits, u32 val)
0306 {
0307     u32 data, mask;
0308     int stat;
0309 
0310     stat = read_register(state, reg, &data);
0311     if (stat)
0312         return stat;
0313     mask = MXL_GET_REG_MASK_32(lsbloc, numofbits);
0314     data = (data & ~mask) | ((val << lsbloc) & mask);
0315     stat = write_register(state, reg, data);
0316     return stat;
0317 }
0318 
0319 static int firmware_is_alive(struct mxl *state)
0320 {
0321     u32 hb0, hb1;
0322 
0323     if (read_register(state, HYDRA_HEAR_BEAT, &hb0))
0324         return 0;
0325     msleep(20);
0326     if (read_register(state, HYDRA_HEAR_BEAT, &hb1))
0327         return 0;
0328     if (hb1 == hb0)
0329         return 0;
0330     return 1;
0331 }
0332 
0333 static int init(struct dvb_frontend *fe)
0334 {
0335     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0336 
0337     /* init fe stats */
0338     p->strength.len = 1;
0339     p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0340     p->cnr.len = 1;
0341     p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0342     p->pre_bit_error.len = 1;
0343     p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0344     p->pre_bit_count.len = 1;
0345     p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0346     p->post_bit_error.len = 1;
0347     p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0348     p->post_bit_count.len = 1;
0349     p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0350 
0351     return 0;
0352 }
0353 
0354 static void release(struct dvb_frontend *fe)
0355 {
0356     struct mxl *state = fe->demodulator_priv;
0357 
0358     list_del(&state->mxl);
0359     /* Release one frontend, two more shall take its place! */
0360     state->base->count--;
0361     if (state->base->count == 0) {
0362         list_del(&state->base->mxllist);
0363         kfree(state->base);
0364     }
0365     kfree(state);
0366 }
0367 
0368 static enum dvbfe_algo get_algo(struct dvb_frontend *fe)
0369 {
0370     return DVBFE_ALGO_HW;
0371 }
0372 
0373 static u32 gold2root(u32 gold)
0374 {
0375     u32 x, g, tmp = gold;
0376 
0377     if (tmp >= 0x3ffff)
0378         tmp = 0;
0379     for (g = 0, x = 1; g < tmp; g++)
0380         x = (((x ^ (x >> 7)) & 1) << 17) | (x >> 1);
0381     return x;
0382 }
0383 
0384 static int cfg_scrambler(struct mxl *state, u32 gold)
0385 {
0386     u32 root;
0387     u8 buf[26] = {
0388         MXL_HYDRA_PLID_CMD_WRITE, 24,
0389         0, MXL_HYDRA_DEMOD_SCRAMBLE_CODE_CMD, 0, 0,
0390         state->demod, 0, 0, 0,
0391         0, 0, 0, 0, 0, 0, 0, 0,
0392         0, 0, 0, 0, 1, 0, 0, 0,
0393     };
0394 
0395     root = gold2root(gold);
0396 
0397     buf[25] = (root >> 24) & 0xff;
0398     buf[24] = (root >> 16) & 0xff;
0399     buf[23] = (root >> 8) & 0xff;
0400     buf[22] = root & 0xff;
0401 
0402     return send_command(state, sizeof(buf), buf);
0403 }
0404 
0405 static int cfg_demod_abort_tune(struct mxl *state)
0406 {
0407     struct MXL_HYDRA_DEMOD_ABORT_TUNE_T abort_tune_cmd;
0408     u8 cmd_size = sizeof(abort_tune_cmd);
0409     u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
0410 
0411     abort_tune_cmd.demod_id = state->demod;
0412     BUILD_HYDRA_CMD(MXL_HYDRA_ABORT_TUNE_CMD, MXL_CMD_WRITE,
0413             cmd_size, &abort_tune_cmd, cmd_buff);
0414     return send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
0415                 &cmd_buff[0]);
0416 }
0417 
0418 static int send_master_cmd(struct dvb_frontend *fe,
0419                struct dvb_diseqc_master_cmd *cmd)
0420 {
0421     /*struct mxl *state = fe->demodulator_priv;*/
0422 
0423     return 0; /*CfgDemodAbortTune(state);*/
0424 }
0425 
0426 static int set_parameters(struct dvb_frontend *fe)
0427 {
0428     struct mxl *state = fe->demodulator_priv;
0429     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0430     struct MXL_HYDRA_DEMOD_PARAM_T demod_chan_cfg;
0431     u8 cmd_size = sizeof(demod_chan_cfg);
0432     u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
0433     u32 srange = 10;
0434     int stat;
0435 
0436     if (p->frequency < 950000 || p->frequency > 2150000)
0437         return -EINVAL;
0438     if (p->symbol_rate < 1000000 || p->symbol_rate > 45000000)
0439         return -EINVAL;
0440 
0441     /* CfgDemodAbortTune(state); */
0442 
0443     switch (p->delivery_system) {
0444     case SYS_DSS:
0445         demod_chan_cfg.standard = MXL_HYDRA_DSS;
0446         demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO;
0447         break;
0448     case SYS_DVBS:
0449         srange = p->symbol_rate / 1000000;
0450         if (srange > 10)
0451             srange = 10;
0452         demod_chan_cfg.standard = MXL_HYDRA_DVBS;
0453         demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_0_35;
0454         demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_QPSK;
0455         demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_OFF;
0456         break;
0457     case SYS_DVBS2:
0458         demod_chan_cfg.standard = MXL_HYDRA_DVBS2;
0459         demod_chan_cfg.roll_off = MXL_HYDRA_ROLLOFF_AUTO;
0460         demod_chan_cfg.modulation_scheme = MXL_HYDRA_MOD_AUTO;
0461         demod_chan_cfg.pilots = MXL_HYDRA_PILOTS_AUTO;
0462         cfg_scrambler(state, p->scrambling_sequence_index);
0463         break;
0464     default:
0465         return -EINVAL;
0466     }
0467     demod_chan_cfg.tuner_index = state->tuner;
0468     demod_chan_cfg.demod_index = state->demod;
0469     demod_chan_cfg.frequency_in_hz = p->frequency * 1000;
0470     demod_chan_cfg.symbol_rate_in_hz = p->symbol_rate;
0471     demod_chan_cfg.max_carrier_offset_in_mhz = srange;
0472     demod_chan_cfg.spectrum_inversion = MXL_HYDRA_SPECTRUM_AUTO;
0473     demod_chan_cfg.fec_code_rate = MXL_HYDRA_FEC_AUTO;
0474 
0475     mutex_lock(&state->base->tune_lock);
0476     if (time_after(jiffies + msecs_to_jiffies(200),
0477                state->base->next_tune))
0478         while (time_before(jiffies, state->base->next_tune))
0479             usleep_range(10000, 11000);
0480     state->base->next_tune = jiffies + msecs_to_jiffies(100);
0481     state->tuner_in_use = state->tuner;
0482     BUILD_HYDRA_CMD(MXL_HYDRA_DEMOD_SET_PARAM_CMD, MXL_CMD_WRITE,
0483             cmd_size, &demod_chan_cfg, cmd_buff);
0484     stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
0485                 &cmd_buff[0]);
0486     mutex_unlock(&state->base->tune_lock);
0487     return stat;
0488 }
0489 
0490 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable);
0491 
0492 static int sleep(struct dvb_frontend *fe)
0493 {
0494     struct mxl *state = fe->demodulator_priv;
0495     struct mxl *p;
0496 
0497     cfg_demod_abort_tune(state);
0498     if (state->tuner_in_use != 0xffffffff) {
0499         mutex_lock(&state->base->tune_lock);
0500         state->tuner_in_use = 0xffffffff;
0501         list_for_each_entry(p, &state->base->mxls, mxl) {
0502             if (p->tuner_in_use == state->tuner)
0503                 break;
0504         }
0505         if (&p->mxl == &state->base->mxls)
0506             enable_tuner(state, state->tuner, 0);
0507         mutex_unlock(&state->base->tune_lock);
0508     }
0509     return 0;
0510 }
0511 
0512 static int read_snr(struct dvb_frontend *fe)
0513 {
0514     struct mxl *state = fe->demodulator_priv;
0515     int stat;
0516     u32 reg_data = 0;
0517     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0518 
0519     mutex_lock(&state->base->status_lock);
0520     HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
0521     stat = read_register(state, (HYDRA_DMD_SNR_ADDR_OFFSET +
0522                      HYDRA_DMD_STATUS_OFFSET(state->demod)),
0523                  &reg_data);
0524     HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
0525     mutex_unlock(&state->base->status_lock);
0526 
0527     p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
0528     p->cnr.stat[0].svalue = (s16)reg_data * 10;
0529 
0530     return stat;
0531 }
0532 
0533 static int read_ber(struct dvb_frontend *fe)
0534 {
0535     struct mxl *state = fe->demodulator_priv;
0536     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0537     u32 reg[8];
0538 
0539     mutex_lock(&state->base->status_lock);
0540     HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
0541     read_register_block(state,
0542         (HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET +
0543          HYDRA_DMD_STATUS_OFFSET(state->demod)),
0544         (4 * sizeof(u32)),
0545         (u8 *) &reg[0]);
0546     HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
0547 
0548     switch (p->delivery_system) {
0549     case SYS_DSS:
0550     case SYS_DVBS:
0551         p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
0552         p->pre_bit_error.stat[0].uvalue = reg[2];
0553         p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
0554         p->pre_bit_count.stat[0].uvalue = reg[3];
0555         break;
0556     default:
0557         break;
0558     }
0559 
0560     read_register_block(state,
0561         (HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET +
0562          HYDRA_DMD_STATUS_OFFSET(state->demod)),
0563         (7 * sizeof(u32)),
0564         (u8 *) &reg[0]);
0565 
0566     switch (p->delivery_system) {
0567     case SYS_DSS:
0568     case SYS_DVBS:
0569         p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
0570         p->post_bit_error.stat[0].uvalue = reg[5];
0571         p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
0572         p->post_bit_count.stat[0].uvalue = reg[6];
0573         break;
0574     case SYS_DVBS2:
0575         p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
0576         p->post_bit_error.stat[0].uvalue = reg[1];
0577         p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
0578         p->post_bit_count.stat[0].uvalue = reg[2];
0579         break;
0580     default:
0581         break;
0582     }
0583 
0584     mutex_unlock(&state->base->status_lock);
0585 
0586     return 0;
0587 }
0588 
0589 static int read_signal_strength(struct dvb_frontend *fe)
0590 {
0591     struct mxl *state = fe->demodulator_priv;
0592     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0593     int stat;
0594     u32 reg_data = 0;
0595 
0596     mutex_lock(&state->base->status_lock);
0597     HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
0598     stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR +
0599                      HYDRA_DMD_STATUS_OFFSET(state->demod)),
0600                  &reg_data);
0601     HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
0602     mutex_unlock(&state->base->status_lock);
0603 
0604     p->strength.stat[0].scale = FE_SCALE_DECIBEL;
0605     p->strength.stat[0].svalue = (s16) reg_data * 10; /* fix scale */
0606 
0607     return stat;
0608 }
0609 
0610 static int read_status(struct dvb_frontend *fe, enum fe_status *status)
0611 {
0612     struct mxl *state = fe->demodulator_priv;
0613     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0614     u32 reg_data = 0;
0615 
0616     mutex_lock(&state->base->status_lock);
0617     HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
0618     read_register(state, (HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET +
0619                  HYDRA_DMD_STATUS_OFFSET(state->demod)),
0620                  &reg_data);
0621     HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
0622     mutex_unlock(&state->base->status_lock);
0623 
0624     *status = (reg_data == 1) ? 0x1f : 0;
0625 
0626     /* signal statistics */
0627 
0628     /* signal strength is always available */
0629     read_signal_strength(fe);
0630 
0631     if (*status & FE_HAS_CARRIER)
0632         read_snr(fe);
0633     else
0634         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0635 
0636     if (*status & FE_HAS_SYNC)
0637         read_ber(fe);
0638     else {
0639         p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0640         p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0641         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0642         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0643     }
0644 
0645     return 0;
0646 }
0647 
0648 static int tune(struct dvb_frontend *fe, bool re_tune,
0649         unsigned int mode_flags,
0650         unsigned int *delay, enum fe_status *status)
0651 {
0652     struct mxl *state = fe->demodulator_priv;
0653     int r = 0;
0654 
0655     *delay = HZ / 2;
0656     if (re_tune) {
0657         r = set_parameters(fe);
0658         if (r)
0659             return r;
0660         state->tune_time = jiffies;
0661     }
0662 
0663     return read_status(fe, status);
0664 }
0665 
0666 static enum fe_code_rate conv_fec(enum MXL_HYDRA_FEC_E fec)
0667 {
0668     enum fe_code_rate fec2fec[11] = {
0669         FEC_NONE, FEC_1_2, FEC_3_5, FEC_2_3,
0670         FEC_3_4, FEC_4_5, FEC_5_6, FEC_6_7,
0671         FEC_7_8, FEC_8_9, FEC_9_10
0672     };
0673 
0674     if (fec > MXL_HYDRA_FEC_9_10)
0675         return FEC_NONE;
0676     return fec2fec[fec];
0677 }
0678 
0679 static int get_frontend(struct dvb_frontend *fe,
0680             struct dtv_frontend_properties *p)
0681 {
0682     struct mxl *state = fe->demodulator_priv;
0683     u32 reg_data[MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE];
0684     u32 freq;
0685 
0686     mutex_lock(&state->base->status_lock);
0687     HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
0688     read_register_block(state,
0689         (HYDRA_DMD_STANDARD_ADDR_OFFSET +
0690         HYDRA_DMD_STATUS_OFFSET(state->demod)),
0691         (MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE * 4), /* 25 * 4 bytes */
0692         (u8 *) &reg_data[0]);
0693     /* read demod channel parameters */
0694     read_register_block(state,
0695         (HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR +
0696         HYDRA_DMD_STATUS_OFFSET(state->demod)),
0697         (4), /* 4 bytes */
0698         (u8 *) &freq);
0699     HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
0700     mutex_unlock(&state->base->status_lock);
0701 
0702     dev_dbg(state->i2cdev, "freq=%u delsys=%u srate=%u\n",
0703         freq * 1000, reg_data[DMD_STANDARD_ADDR],
0704         reg_data[DMD_SYMBOL_RATE_ADDR]);
0705     p->symbol_rate = reg_data[DMD_SYMBOL_RATE_ADDR];
0706     p->frequency = freq;
0707     /*
0708      * p->delivery_system =
0709      *  (MXL_HYDRA_BCAST_STD_E) regData[DMD_STANDARD_ADDR];
0710      * p->inversion =
0711      *  (MXL_HYDRA_SPECTRUM_E) regData[DMD_SPECTRUM_INVERSION_ADDR];
0712      * freqSearchRangeKHz =
0713      *  (regData[DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR]);
0714      */
0715 
0716     p->fec_inner = conv_fec(reg_data[DMD_FEC_CODE_RATE_ADDR]);
0717     switch (p->delivery_system) {
0718     case SYS_DSS:
0719         break;
0720     case SYS_DVBS2:
0721         switch ((enum MXL_HYDRA_PILOTS_E)
0722             reg_data[DMD_DVBS2_PILOT_ON_OFF_ADDR]) {
0723         case MXL_HYDRA_PILOTS_OFF:
0724             p->pilot = PILOT_OFF;
0725             break;
0726         case MXL_HYDRA_PILOTS_ON:
0727             p->pilot = PILOT_ON;
0728             break;
0729         default:
0730             break;
0731         }
0732         fallthrough;
0733     case SYS_DVBS:
0734         switch ((enum MXL_HYDRA_MODULATION_E)
0735             reg_data[DMD_MODULATION_SCHEME_ADDR]) {
0736         case MXL_HYDRA_MOD_QPSK:
0737             p->modulation = QPSK;
0738             break;
0739         case MXL_HYDRA_MOD_8PSK:
0740             p->modulation = PSK_8;
0741             break;
0742         default:
0743             break;
0744         }
0745         switch ((enum MXL_HYDRA_ROLLOFF_E)
0746             reg_data[DMD_SPECTRUM_ROLL_OFF_ADDR]) {
0747         case MXL_HYDRA_ROLLOFF_0_20:
0748             p->rolloff = ROLLOFF_20;
0749             break;
0750         case MXL_HYDRA_ROLLOFF_0_35:
0751             p->rolloff = ROLLOFF_35;
0752             break;
0753         case MXL_HYDRA_ROLLOFF_0_25:
0754             p->rolloff = ROLLOFF_25;
0755             break;
0756         default:
0757             break;
0758         }
0759         break;
0760     default:
0761         return -EINVAL;
0762     }
0763     return 0;
0764 }
0765 
0766 static int set_input(struct dvb_frontend *fe, int input)
0767 {
0768     struct mxl *state = fe->demodulator_priv;
0769 
0770     state->tuner = input;
0771     return 0;
0772 }
0773 
0774 static const struct dvb_frontend_ops mxl_ops = {
0775     .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
0776     .info = {
0777         .name           = "MaxLinear MxL5xx DVB-S/S2 tuner-demodulator",
0778         .frequency_min_hz   =  300 * MHz,
0779         .frequency_max_hz   = 2350 * MHz,
0780         .symbol_rate_min    = 1000000,
0781         .symbol_rate_max    = 45000000,
0782         .caps           = FE_CAN_INVERSION_AUTO |
0783                       FE_CAN_FEC_AUTO       |
0784                       FE_CAN_QPSK           |
0785                       FE_CAN_2G_MODULATION
0786     },
0787     .init               = init,
0788     .release                        = release,
0789     .get_frontend_algo              = get_algo,
0790     .tune                           = tune,
0791     .read_status            = read_status,
0792     .sleep              = sleep,
0793     .get_frontend                   = get_frontend,
0794     .diseqc_send_master_cmd     = send_master_cmd,
0795 };
0796 
0797 static struct mxl_base *match_base(struct i2c_adapter  *i2c, u8 adr)
0798 {
0799     struct mxl_base *p;
0800 
0801     list_for_each_entry(p, &mxllist, mxllist)
0802         if (p->i2c == i2c && p->adr == adr)
0803             return p;
0804     return NULL;
0805 }
0806 
0807 static void cfg_dev_xtal(struct mxl *state, u32 freq, u32 cap, u32 enable)
0808 {
0809     if (state->base->can_clkout || !enable)
0810         update_by_mnemonic(state, 0x90200054, 23, 1, enable);
0811 
0812     if (freq == 24000000)
0813         write_register(state, HYDRA_CRYSTAL_SETTING, 0);
0814     else
0815         write_register(state, HYDRA_CRYSTAL_SETTING, 1);
0816 
0817     write_register(state, HYDRA_CRYSTAL_CAP, cap);
0818 }
0819 
0820 static u32 get_big_endian(u8 num_of_bits, const u8 buf[])
0821 {
0822     u32 ret_value = 0;
0823 
0824     switch (num_of_bits) {
0825     case 24:
0826         ret_value = (((u32) buf[0]) << 16) |
0827             (((u32) buf[1]) << 8) | buf[2];
0828         break;
0829     case 32:
0830         ret_value = (((u32) buf[0]) << 24) |
0831             (((u32) buf[1]) << 16) |
0832             (((u32) buf[2]) << 8) | buf[3];
0833         break;
0834     default:
0835         break;
0836     }
0837 
0838     return ret_value;
0839 }
0840 
0841 static int write_fw_segment(struct mxl *state,
0842                 u32 mem_addr, u32 total_size, u8 *data_ptr)
0843 {
0844     int status;
0845     u32 data_count = 0;
0846     u32 size = 0;
0847     u32 orig_size = 0;
0848     u8 *w_buf_ptr = NULL;
0849     u32 block_size = ((MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH -
0850              (MXL_HYDRA_I2C_HDR_SIZE +
0851               MXL_HYDRA_REG_SIZE_IN_BYTES)) / 4) * 4;
0852     u8 w_msg_buffer[MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH -
0853               (MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES)];
0854 
0855     do {
0856         size = orig_size = (((u32)(data_count + block_size)) > total_size) ?
0857             (total_size - data_count) : block_size;
0858 
0859         if (orig_size & 3)
0860             size = (orig_size + 4) & ~3;
0861         w_buf_ptr = &w_msg_buffer[0];
0862         memset((void *) w_buf_ptr, 0, size);
0863         memcpy((void *) w_buf_ptr, (void *) data_ptr, orig_size);
0864         convert_endian(1, size, w_buf_ptr);
0865         status  = write_firmware_block(state, mem_addr, size, w_buf_ptr);
0866         if (status)
0867             return status;
0868         data_count += size;
0869         mem_addr   += size;
0870         data_ptr   += size;
0871     } while (data_count < total_size);
0872 
0873     return status;
0874 }
0875 
0876 static int do_firmware_download(struct mxl *state, u8 *mbin_buffer_ptr,
0877                 u32 mbin_buffer_size)
0878 
0879 {
0880     int status;
0881     u32 index = 0;
0882     u32 seg_length = 0;
0883     u32 seg_address = 0;
0884     struct MBIN_FILE_T *mbin_ptr  = (struct MBIN_FILE_T *)mbin_buffer_ptr;
0885     struct MBIN_SEGMENT_T *segment_ptr;
0886     enum MXL_BOOL_E xcpu_fw_flag = MXL_FALSE;
0887 
0888     if (mbin_ptr->header.id != MBIN_FILE_HEADER_ID) {
0889         dev_err(state->i2cdev, "%s: Invalid file header ID (%c)\n",
0890                __func__, mbin_ptr->header.id);
0891         return -EINVAL;
0892     }
0893     status = write_register(state, FW_DL_SIGN_ADDR, 0);
0894     if (status)
0895         return status;
0896     segment_ptr = (struct MBIN_SEGMENT_T *) (&mbin_ptr->data[0]);
0897     for (index = 0; index < mbin_ptr->header.num_segments; index++) {
0898         if (segment_ptr->header.id != MBIN_SEGMENT_HEADER_ID) {
0899             dev_err(state->i2cdev, "%s: Invalid segment header ID (%c)\n",
0900                    __func__, segment_ptr->header.id);
0901             return -EINVAL;
0902         }
0903         seg_length  = get_big_endian(24,
0904                         &(segment_ptr->header.len24[0]));
0905         seg_address = get_big_endian(32,
0906                         &(segment_ptr->header.address[0]));
0907 
0908         if (state->base->type == MXL_HYDRA_DEVICE_568) {
0909             if ((((seg_address & 0x90760000) == 0x90760000) ||
0910                  ((seg_address & 0x90740000) == 0x90740000)) &&
0911                 (xcpu_fw_flag == MXL_FALSE)) {
0912                 update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
0913                 msleep(200);
0914                 write_register(state, 0x90720000, 0);
0915                 usleep_range(10000, 11000);
0916                 xcpu_fw_flag = MXL_TRUE;
0917             }
0918             status = write_fw_segment(state, seg_address,
0919                           seg_length,
0920                           (u8 *) segment_ptr->data);
0921         } else {
0922             if (((seg_address & 0x90760000) != 0x90760000) &&
0923                 ((seg_address & 0x90740000) != 0x90740000))
0924                 status = write_fw_segment(state, seg_address,
0925                     seg_length, (u8 *) segment_ptr->data);
0926         }
0927         if (status)
0928             return status;
0929         segment_ptr = (struct MBIN_SEGMENT_T *)
0930             &(segment_ptr->data[((seg_length + 3) / 4) * 4]);
0931     }
0932     return status;
0933 }
0934 
0935 static int check_fw(struct mxl *state, u8 *mbin, u32 mbin_len)
0936 {
0937     struct MBIN_FILE_HEADER_T *fh = (struct MBIN_FILE_HEADER_T *) mbin;
0938     u32 flen = (fh->image_size24[0] << 16) |
0939         (fh->image_size24[1] <<  8) | fh->image_size24[2];
0940     u8 *fw, cs = 0;
0941     u32 i;
0942 
0943     if (fh->id != 'M' || fh->fmt_version != '1' || flen > 0x3FFF0) {
0944         dev_info(state->i2cdev, "Invalid FW Header\n");
0945         return -1;
0946     }
0947     fw = mbin + sizeof(struct MBIN_FILE_HEADER_T);
0948     for (i = 0; i < flen; i += 1)
0949         cs += fw[i];
0950     if (cs != fh->image_checksum) {
0951         dev_info(state->i2cdev, "Invalid FW Checksum\n");
0952         return -1;
0953     }
0954     return 0;
0955 }
0956 
0957 static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len)
0958 {
0959     int status;
0960     u32 reg_data = 0;
0961     struct MXL_HYDRA_SKU_COMMAND_T dev_sku_cfg;
0962     u8 cmd_size = sizeof(struct MXL_HYDRA_SKU_COMMAND_T);
0963     u8 cmd_buff[sizeof(struct MXL_HYDRA_SKU_COMMAND_T) + 6];
0964 
0965     if (check_fw(state, mbin, mbin_len))
0966         return -1;
0967 
0968     /* put CPU into reset */
0969     status = update_by_mnemonic(state, 0x8003003C, 0, 1, 0);
0970     if (status)
0971         return status;
0972     usleep_range(1000, 2000);
0973 
0974     /* Reset TX FIFO's, BBAND, XBAR */
0975     status = write_register(state, HYDRA_RESET_TRANSPORT_FIFO_REG,
0976                 HYDRA_RESET_TRANSPORT_FIFO_DATA);
0977     if (status)
0978         return status;
0979     status = write_register(state, HYDRA_RESET_BBAND_REG,
0980                 HYDRA_RESET_BBAND_DATA);
0981     if (status)
0982         return status;
0983     status = write_register(state, HYDRA_RESET_XBAR_REG,
0984                 HYDRA_RESET_XBAR_DATA);
0985     if (status)
0986         return status;
0987 
0988     /* Disable clock to Baseband, Wideband, SerDes,
0989      * Alias ext & Transport modules
0990      */
0991     status = write_register(state, HYDRA_MODULES_CLK_2_REG,
0992                 HYDRA_DISABLE_CLK_2);
0993     if (status)
0994         return status;
0995     /* Clear Software & Host interrupt status - (Clear on read) */
0996     status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, &reg_data);
0997     if (status)
0998         return status;
0999     status = do_firmware_download(state, mbin, mbin_len);
1000     if (status)
1001         return status;
1002 
1003     if (state->base->type == MXL_HYDRA_DEVICE_568) {
1004         usleep_range(10000, 11000);
1005 
1006         /* bring XCPU out of reset */
1007         status = write_register(state, 0x90720000, 1);
1008         if (status)
1009             return status;
1010         msleep(500);
1011 
1012         /* Enable XCPU UART message processing in MCPU */
1013         status = write_register(state, 0x9076B510, 1);
1014         if (status)
1015             return status;
1016     } else {
1017         /* Bring CPU out of reset */
1018         status = update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
1019         if (status)
1020             return status;
1021         /* Wait until FW boots */
1022         msleep(150);
1023     }
1024 
1025     /* Initialize XPT XBAR */
1026     status = write_register(state, XPT_DMD0_BASEADDR, 0x76543210);
1027     if (status)
1028         return status;
1029 
1030     if (!firmware_is_alive(state))
1031         return -1;
1032 
1033     dev_info(state->i2cdev, "Hydra FW alive. Hail!\n");
1034 
1035     /* sometimes register values are wrong shortly
1036      * after first heart beats
1037      */
1038     msleep(50);
1039 
1040     dev_sku_cfg.sku_type = state->base->sku_type;
1041     BUILD_HYDRA_CMD(MXL_HYDRA_DEV_CFG_SKU_CMD, MXL_CMD_WRITE,
1042             cmd_size, &dev_sku_cfg, cmd_buff);
1043     status = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
1044                   &cmd_buff[0]);
1045 
1046     return status;
1047 }
1048 
1049 static int cfg_ts_pad_mux(struct mxl *state, enum MXL_BOOL_E enable_serial_ts)
1050 {
1051     int status = 0;
1052     u32 pad_mux_value = 0;
1053 
1054     if (enable_serial_ts == MXL_TRUE) {
1055         pad_mux_value = 0;
1056         if ((state->base->type == MXL_HYDRA_DEVICE_541) ||
1057             (state->base->type == MXL_HYDRA_DEVICE_541S))
1058             pad_mux_value = 2;
1059     } else {
1060         if ((state->base->type == MXL_HYDRA_DEVICE_581) ||
1061             (state->base->type == MXL_HYDRA_DEVICE_581S))
1062             pad_mux_value = 2;
1063         else
1064             pad_mux_value = 3;
1065     }
1066 
1067     switch (state->base->type) {
1068     case MXL_HYDRA_DEVICE_561:
1069     case MXL_HYDRA_DEVICE_581:
1070     case MXL_HYDRA_DEVICE_541:
1071     case MXL_HYDRA_DEVICE_541S:
1072     case MXL_HYDRA_DEVICE_561S:
1073     case MXL_HYDRA_DEVICE_581S:
1074         status |= update_by_mnemonic(state, 0x90000170, 24, 3,
1075                          pad_mux_value);
1076         status |= update_by_mnemonic(state, 0x90000170, 28, 3,
1077                          pad_mux_value);
1078         status |= update_by_mnemonic(state, 0x90000174, 0, 3,
1079                          pad_mux_value);
1080         status |= update_by_mnemonic(state, 0x90000174, 4, 3,
1081                          pad_mux_value);
1082         status |= update_by_mnemonic(state, 0x90000174, 8, 3,
1083                          pad_mux_value);
1084         status |= update_by_mnemonic(state, 0x90000174, 12, 3,
1085                          pad_mux_value);
1086         status |= update_by_mnemonic(state, 0x90000174, 16, 3,
1087                          pad_mux_value);
1088         status |= update_by_mnemonic(state, 0x90000174, 20, 3,
1089                          pad_mux_value);
1090         status |= update_by_mnemonic(state, 0x90000174, 24, 3,
1091                          pad_mux_value);
1092         status |= update_by_mnemonic(state, 0x90000174, 28, 3,
1093                          pad_mux_value);
1094         status |= update_by_mnemonic(state, 0x90000178, 0, 3,
1095                          pad_mux_value);
1096         status |= update_by_mnemonic(state, 0x90000178, 4, 3,
1097                          pad_mux_value);
1098         status |= update_by_mnemonic(state, 0x90000178, 8, 3,
1099                          pad_mux_value);
1100         break;
1101 
1102     case MXL_HYDRA_DEVICE_544:
1103     case MXL_HYDRA_DEVICE_542:
1104         status |= update_by_mnemonic(state, 0x9000016C, 4, 3, 1);
1105         status |= update_by_mnemonic(state, 0x9000016C, 8, 3, 0);
1106         status |= update_by_mnemonic(state, 0x9000016C, 12, 3, 0);
1107         status |= update_by_mnemonic(state, 0x9000016C, 16, 3, 0);
1108         status |= update_by_mnemonic(state, 0x90000170, 0, 3, 0);
1109         status |= update_by_mnemonic(state, 0x90000178, 12, 3, 1);
1110         status |= update_by_mnemonic(state, 0x90000178, 16, 3, 1);
1111         status |= update_by_mnemonic(state, 0x90000178, 20, 3, 1);
1112         status |= update_by_mnemonic(state, 0x90000178, 24, 3, 1);
1113         status |= update_by_mnemonic(state, 0x9000017C, 0, 3, 1);
1114         status |= update_by_mnemonic(state, 0x9000017C, 4, 3, 1);
1115         if (enable_serial_ts == MXL_ENABLE) {
1116             status |= update_by_mnemonic(state,
1117                 0x90000170, 4, 3, 0);
1118             status |= update_by_mnemonic(state,
1119                 0x90000170, 8, 3, 0);
1120             status |= update_by_mnemonic(state,
1121                 0x90000170, 12, 3, 0);
1122             status |= update_by_mnemonic(state,
1123                 0x90000170, 16, 3, 0);
1124             status |= update_by_mnemonic(state,
1125                 0x90000170, 20, 3, 1);
1126             status |= update_by_mnemonic(state,
1127                 0x90000170, 24, 3, 1);
1128             status |= update_by_mnemonic(state,
1129                 0x90000170, 28, 3, 2);
1130             status |= update_by_mnemonic(state,
1131                 0x90000174, 0, 3, 2);
1132             status |= update_by_mnemonic(state,
1133                 0x90000174, 4, 3, 2);
1134             status |= update_by_mnemonic(state,
1135                 0x90000174, 8, 3, 2);
1136             status |= update_by_mnemonic(state,
1137                 0x90000174, 12, 3, 2);
1138             status |= update_by_mnemonic(state,
1139                 0x90000174, 16, 3, 2);
1140             status |= update_by_mnemonic(state,
1141                 0x90000174, 20, 3, 2);
1142             status |= update_by_mnemonic(state,
1143                 0x90000174, 24, 3, 2);
1144             status |= update_by_mnemonic(state,
1145                 0x90000174, 28, 3, 2);
1146             status |= update_by_mnemonic(state,
1147                 0x90000178, 0, 3, 2);
1148             status |= update_by_mnemonic(state,
1149                 0x90000178, 4, 3, 2);
1150             status |= update_by_mnemonic(state,
1151                 0x90000178, 8, 3, 2);
1152         } else {
1153             status |= update_by_mnemonic(state,
1154                 0x90000170, 4, 3, 3);
1155             status |= update_by_mnemonic(state,
1156                 0x90000170, 8, 3, 3);
1157             status |= update_by_mnemonic(state,
1158                 0x90000170, 12, 3, 3);
1159             status |= update_by_mnemonic(state,
1160                 0x90000170, 16, 3, 3);
1161             status |= update_by_mnemonic(state,
1162                 0x90000170, 20, 3, 3);
1163             status |= update_by_mnemonic(state,
1164                 0x90000170, 24, 3, 3);
1165             status |= update_by_mnemonic(state,
1166                 0x90000170, 28, 3, 3);
1167             status |= update_by_mnemonic(state,
1168                 0x90000174, 0, 3, 3);
1169             status |= update_by_mnemonic(state,
1170                 0x90000174, 4, 3, 3);
1171             status |= update_by_mnemonic(state,
1172                 0x90000174, 8, 3, 3);
1173             status |= update_by_mnemonic(state,
1174                 0x90000174, 12, 3, 3);
1175             status |= update_by_mnemonic(state,
1176                 0x90000174, 16, 3, 3);
1177             status |= update_by_mnemonic(state,
1178                 0x90000174, 20, 3, 1);
1179             status |= update_by_mnemonic(state,
1180                 0x90000174, 24, 3, 1);
1181             status |= update_by_mnemonic(state,
1182                 0x90000174, 28, 3, 1);
1183             status |= update_by_mnemonic(state,
1184                 0x90000178, 0, 3, 1);
1185             status |= update_by_mnemonic(state,
1186                 0x90000178, 4, 3, 1);
1187             status |= update_by_mnemonic(state,
1188                 0x90000178, 8, 3, 1);
1189         }
1190         break;
1191 
1192     case MXL_HYDRA_DEVICE_568:
1193         if (enable_serial_ts == MXL_FALSE) {
1194             status |= update_by_mnemonic(state,
1195                 0x9000016C, 8, 3, 5);
1196             status |= update_by_mnemonic(state,
1197                 0x9000016C, 12, 3, 5);
1198             status |= update_by_mnemonic(state,
1199                 0x9000016C, 16, 3, 5);
1200             status |= update_by_mnemonic(state,
1201                 0x9000016C, 20, 3, 5);
1202             status |= update_by_mnemonic(state,
1203                 0x9000016C, 24, 3, 5);
1204             status |= update_by_mnemonic(state,
1205                 0x9000016C, 28, 3, 5);
1206             status |= update_by_mnemonic(state,
1207                 0x90000170, 0, 3, 5);
1208             status |= update_by_mnemonic(state,
1209                 0x90000170, 4, 3, 5);
1210             status |= update_by_mnemonic(state,
1211                 0x90000170, 8, 3, 5);
1212             status |= update_by_mnemonic(state,
1213                 0x90000170, 12, 3, 5);
1214             status |= update_by_mnemonic(state,
1215                 0x90000170, 16, 3, 5);
1216             status |= update_by_mnemonic(state,
1217                 0x90000170, 20, 3, 5);
1218 
1219             status |= update_by_mnemonic(state,
1220                 0x90000170, 24, 3, pad_mux_value);
1221             status |= update_by_mnemonic(state,
1222                 0x90000174, 0, 3, pad_mux_value);
1223             status |= update_by_mnemonic(state,
1224                 0x90000174, 4, 3, pad_mux_value);
1225             status |= update_by_mnemonic(state,
1226                 0x90000174, 8, 3, pad_mux_value);
1227             status |= update_by_mnemonic(state,
1228                 0x90000174, 12, 3, pad_mux_value);
1229             status |= update_by_mnemonic(state,
1230                 0x90000174, 16, 3, pad_mux_value);
1231             status |= update_by_mnemonic(state,
1232                 0x90000174, 20, 3, pad_mux_value);
1233             status |= update_by_mnemonic(state,
1234                 0x90000174, 24, 3, pad_mux_value);
1235             status |= update_by_mnemonic(state,
1236                 0x90000174, 28, 3, pad_mux_value);
1237             status |= update_by_mnemonic(state,
1238                 0x90000178, 0, 3, pad_mux_value);
1239             status |= update_by_mnemonic(state,
1240                 0x90000178, 4, 3, pad_mux_value);
1241 
1242             status |= update_by_mnemonic(state,
1243                 0x90000178, 8, 3, 5);
1244             status |= update_by_mnemonic(state,
1245                 0x90000178, 12, 3, 5);
1246             status |= update_by_mnemonic(state,
1247                 0x90000178, 16, 3, 5);
1248             status |= update_by_mnemonic(state,
1249                 0x90000178, 20, 3, 5);
1250             status |= update_by_mnemonic(state,
1251                 0x90000178, 24, 3, 5);
1252             status |= update_by_mnemonic(state,
1253                 0x90000178, 28, 3, 5);
1254             status |= update_by_mnemonic(state,
1255                 0x9000017C, 0, 3, 5);
1256             status |= update_by_mnemonic(state,
1257                 0x9000017C, 4, 3, 5);
1258         } else {
1259             status |= update_by_mnemonic(state,
1260                 0x90000170, 4, 3, pad_mux_value);
1261             status |= update_by_mnemonic(state,
1262                 0x90000170, 8, 3, pad_mux_value);
1263             status |= update_by_mnemonic(state,
1264                 0x90000170, 12, 3, pad_mux_value);
1265             status |= update_by_mnemonic(state,
1266                 0x90000170, 16, 3, pad_mux_value);
1267             status |= update_by_mnemonic(state,
1268                 0x90000170, 20, 3, pad_mux_value);
1269             status |= update_by_mnemonic(state,
1270                 0x90000170, 24, 3, pad_mux_value);
1271             status |= update_by_mnemonic(state,
1272                 0x90000170, 28, 3, pad_mux_value);
1273             status |= update_by_mnemonic(state,
1274                 0x90000174, 0, 3, pad_mux_value);
1275             status |= update_by_mnemonic(state,
1276                 0x90000174, 4, 3, pad_mux_value);
1277             status |= update_by_mnemonic(state,
1278                 0x90000174, 8, 3, pad_mux_value);
1279             status |= update_by_mnemonic(state,
1280                 0x90000174, 12, 3, pad_mux_value);
1281         }
1282         break;
1283 
1284 
1285     case MXL_HYDRA_DEVICE_584:
1286     default:
1287         status |= update_by_mnemonic(state,
1288             0x90000170, 4, 3, pad_mux_value);
1289         status |= update_by_mnemonic(state,
1290             0x90000170, 8, 3, pad_mux_value);
1291         status |= update_by_mnemonic(state,
1292             0x90000170, 12, 3, pad_mux_value);
1293         status |= update_by_mnemonic(state,
1294             0x90000170, 16, 3, pad_mux_value);
1295         status |= update_by_mnemonic(state,
1296             0x90000170, 20, 3, pad_mux_value);
1297         status |= update_by_mnemonic(state,
1298             0x90000170, 24, 3, pad_mux_value);
1299         status |= update_by_mnemonic(state,
1300             0x90000170, 28, 3, pad_mux_value);
1301         status |= update_by_mnemonic(state,
1302             0x90000174, 0, 3, pad_mux_value);
1303         status |= update_by_mnemonic(state,
1304             0x90000174, 4, 3, pad_mux_value);
1305         status |= update_by_mnemonic(state,
1306             0x90000174, 8, 3, pad_mux_value);
1307         status |= update_by_mnemonic(state,
1308             0x90000174, 12, 3, pad_mux_value);
1309         break;
1310     }
1311     return status;
1312 }
1313 
1314 static int set_drive_strength(struct mxl *state,
1315         enum MXL_HYDRA_TS_DRIVE_STRENGTH_E ts_drive_strength)
1316 {
1317     int stat = 0;
1318     u32 val;
1319 
1320     read_register(state, 0x90000194, &val);
1321     dev_info(state->i2cdev, "DIGIO = %08x\n", val);
1322     dev_info(state->i2cdev, "set drive_strength = %u\n", ts_drive_strength);
1323 
1324 
1325     stat |= update_by_mnemonic(state, 0x90000194, 0, 3, ts_drive_strength);
1326     stat |= update_by_mnemonic(state, 0x90000194, 20, 3, ts_drive_strength);
1327     stat |= update_by_mnemonic(state, 0x90000194, 24, 3, ts_drive_strength);
1328     stat |= update_by_mnemonic(state, 0x90000198, 12, 3, ts_drive_strength);
1329     stat |= update_by_mnemonic(state, 0x90000198, 16, 3, ts_drive_strength);
1330     stat |= update_by_mnemonic(state, 0x90000198, 20, 3, ts_drive_strength);
1331     stat |= update_by_mnemonic(state, 0x90000198, 24, 3, ts_drive_strength);
1332     stat |= update_by_mnemonic(state, 0x9000019C, 0, 3, ts_drive_strength);
1333     stat |= update_by_mnemonic(state, 0x9000019C, 4, 3, ts_drive_strength);
1334     stat |= update_by_mnemonic(state, 0x9000019C, 8, 3, ts_drive_strength);
1335     stat |= update_by_mnemonic(state, 0x9000019C, 24, 3, ts_drive_strength);
1336     stat |= update_by_mnemonic(state, 0x9000019C, 28, 3, ts_drive_strength);
1337     stat |= update_by_mnemonic(state, 0x900001A0, 0, 3, ts_drive_strength);
1338     stat |= update_by_mnemonic(state, 0x900001A0, 4, 3, ts_drive_strength);
1339     stat |= update_by_mnemonic(state, 0x900001A0, 20, 3, ts_drive_strength);
1340     stat |= update_by_mnemonic(state, 0x900001A0, 24, 3, ts_drive_strength);
1341     stat |= update_by_mnemonic(state, 0x900001A0, 28, 3, ts_drive_strength);
1342 
1343     return stat;
1344 }
1345 
1346 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable)
1347 {
1348     int stat = 0;
1349     struct MXL_HYDRA_TUNER_CMD ctrl_tuner_cmd;
1350     u8 cmd_size = sizeof(ctrl_tuner_cmd);
1351     u8 cmd_buff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN];
1352     u32 val, count = 10;
1353 
1354     ctrl_tuner_cmd.tuner_id = tuner;
1355     ctrl_tuner_cmd.enable = enable;
1356     BUILD_HYDRA_CMD(MXL_HYDRA_TUNER_ACTIVATE_CMD, MXL_CMD_WRITE,
1357             cmd_size, &ctrl_tuner_cmd, cmd_buff);
1358     stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
1359                 &cmd_buff[0]);
1360     if (stat)
1361         return stat;
1362     read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1363     while (--count && ((val >> tuner) & 1) != enable) {
1364         msleep(20);
1365         read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1366     }
1367     if (!count)
1368         return -1;
1369     read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1370     dev_dbg(state->i2cdev, "tuner %u ready = %u\n",
1371         tuner, (val >> tuner) & 1);
1372 
1373     return 0;
1374 }
1375 
1376 
1377 static int config_ts(struct mxl *state, enum MXL_HYDRA_DEMOD_ID_E demod_id,
1378              struct MXL_HYDRA_MPEGOUT_PARAM_T *mpeg_out_param_ptr)
1379 {
1380     int status = 0;
1381     u32 nco_count_min = 0;
1382     u32 clk_type = 0;
1383 
1384     struct MXL_REG_FIELD_T xpt_sync_polarity[MXL_HYDRA_DEMOD_MAX] = {
1385         {0x90700010, 8, 1}, {0x90700010, 9, 1},
1386         {0x90700010, 10, 1}, {0x90700010, 11, 1},
1387         {0x90700010, 12, 1}, {0x90700010, 13, 1},
1388         {0x90700010, 14, 1}, {0x90700010, 15, 1} };
1389     struct MXL_REG_FIELD_T xpt_clock_polarity[MXL_HYDRA_DEMOD_MAX] = {
1390         {0x90700010, 16, 1}, {0x90700010, 17, 1},
1391         {0x90700010, 18, 1}, {0x90700010, 19, 1},
1392         {0x90700010, 20, 1}, {0x90700010, 21, 1},
1393         {0x90700010, 22, 1}, {0x90700010, 23, 1} };
1394     struct MXL_REG_FIELD_T xpt_valid_polarity[MXL_HYDRA_DEMOD_MAX] = {
1395         {0x90700014, 0, 1}, {0x90700014, 1, 1},
1396         {0x90700014, 2, 1}, {0x90700014, 3, 1},
1397         {0x90700014, 4, 1}, {0x90700014, 5, 1},
1398         {0x90700014, 6, 1}, {0x90700014, 7, 1} };
1399     struct MXL_REG_FIELD_T xpt_ts_clock_phase[MXL_HYDRA_DEMOD_MAX] = {
1400         {0x90700018, 0, 3}, {0x90700018, 4, 3},
1401         {0x90700018, 8, 3}, {0x90700018, 12, 3},
1402         {0x90700018, 16, 3}, {0x90700018, 20, 3},
1403         {0x90700018, 24, 3}, {0x90700018, 28, 3} };
1404     struct MXL_REG_FIELD_T xpt_lsb_first[MXL_HYDRA_DEMOD_MAX] = {
1405         {0x9070000C, 16, 1}, {0x9070000C, 17, 1},
1406         {0x9070000C, 18, 1}, {0x9070000C, 19, 1},
1407         {0x9070000C, 20, 1}, {0x9070000C, 21, 1},
1408         {0x9070000C, 22, 1}, {0x9070000C, 23, 1} };
1409     struct MXL_REG_FIELD_T xpt_sync_byte[MXL_HYDRA_DEMOD_MAX] = {
1410         {0x90700010, 0, 1}, {0x90700010, 1, 1},
1411         {0x90700010, 2, 1}, {0x90700010, 3, 1},
1412         {0x90700010, 4, 1}, {0x90700010, 5, 1},
1413         {0x90700010, 6, 1}, {0x90700010, 7, 1} };
1414     struct MXL_REG_FIELD_T xpt_enable_output[MXL_HYDRA_DEMOD_MAX] = {
1415         {0x9070000C, 0, 1}, {0x9070000C, 1, 1},
1416         {0x9070000C, 2, 1}, {0x9070000C, 3, 1},
1417         {0x9070000C, 4, 1}, {0x9070000C, 5, 1},
1418         {0x9070000C, 6, 1}, {0x9070000C, 7, 1} };
1419     struct MXL_REG_FIELD_T xpt_err_replace_sync[MXL_HYDRA_DEMOD_MAX] = {
1420         {0x9070000C, 24, 1}, {0x9070000C, 25, 1},
1421         {0x9070000C, 26, 1}, {0x9070000C, 27, 1},
1422         {0x9070000C, 28, 1}, {0x9070000C, 29, 1},
1423         {0x9070000C, 30, 1}, {0x9070000C, 31, 1} };
1424     struct MXL_REG_FIELD_T xpt_err_replace_valid[MXL_HYDRA_DEMOD_MAX] = {
1425         {0x90700014, 8, 1}, {0x90700014, 9, 1},
1426         {0x90700014, 10, 1}, {0x90700014, 11, 1},
1427         {0x90700014, 12, 1}, {0x90700014, 13, 1},
1428         {0x90700014, 14, 1}, {0x90700014, 15, 1} };
1429     struct MXL_REG_FIELD_T xpt_continuous_clock[MXL_HYDRA_DEMOD_MAX] = {
1430         {0x907001D4, 0, 1}, {0x907001D4, 1, 1},
1431         {0x907001D4, 2, 1}, {0x907001D4, 3, 1},
1432         {0x907001D4, 4, 1}, {0x907001D4, 5, 1},
1433         {0x907001D4, 6, 1}, {0x907001D4, 7, 1} };
1434     struct MXL_REG_FIELD_T xpt_nco_clock_rate[MXL_HYDRA_DEMOD_MAX] = {
1435         {0x90700044, 16, 80}, {0x90700044, 16, 81},
1436         {0x90700044, 16, 82}, {0x90700044, 16, 83},
1437         {0x90700044, 16, 84}, {0x90700044, 16, 85},
1438         {0x90700044, 16, 86}, {0x90700044, 16, 87} };
1439 
1440     demod_id = state->base->ts_map[demod_id];
1441 
1442     if (mpeg_out_param_ptr->enable == MXL_ENABLE) {
1443         if (mpeg_out_param_ptr->mpeg_mode ==
1444             MXL_HYDRA_MPEG_MODE_PARALLEL) {
1445         } else {
1446             cfg_ts_pad_mux(state, MXL_TRUE);
1447             update_by_mnemonic(state,
1448                 0x90700010, 27, 1, MXL_FALSE);
1449         }
1450     }
1451 
1452     nco_count_min =
1453         (u32)(MXL_HYDRA_NCO_CLK / mpeg_out_param_ptr->max_mpeg_clk_rate);
1454 
1455     if (state->base->chipversion >= 2) {
1456         status |= update_by_mnemonic(state,
1457             xpt_nco_clock_rate[demod_id].reg_addr, /* Reg Addr */
1458             xpt_nco_clock_rate[demod_id].lsb_pos, /* LSB pos */
1459             xpt_nco_clock_rate[demod_id].num_of_bits, /* Num of bits */
1460             nco_count_min); /* Data */
1461     } else
1462         update_by_mnemonic(state, 0x90700044, 16, 8, nco_count_min);
1463 
1464     if (mpeg_out_param_ptr->mpeg_clk_type == MXL_HYDRA_MPEG_CLK_CONTINUOUS)
1465         clk_type = 1;
1466 
1467     if (mpeg_out_param_ptr->mpeg_mode < MXL_HYDRA_MPEG_MODE_PARALLEL) {
1468         status |= update_by_mnemonic(state,
1469             xpt_continuous_clock[demod_id].reg_addr,
1470             xpt_continuous_clock[demod_id].lsb_pos,
1471             xpt_continuous_clock[demod_id].num_of_bits,
1472             clk_type);
1473     } else
1474         update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type);
1475 
1476     status |= update_by_mnemonic(state,
1477         xpt_sync_polarity[demod_id].reg_addr,
1478         xpt_sync_polarity[demod_id].lsb_pos,
1479         xpt_sync_polarity[demod_id].num_of_bits,
1480         mpeg_out_param_ptr->mpeg_sync_pol);
1481 
1482     status |= update_by_mnemonic(state,
1483         xpt_valid_polarity[demod_id].reg_addr,
1484         xpt_valid_polarity[demod_id].lsb_pos,
1485         xpt_valid_polarity[demod_id].num_of_bits,
1486         mpeg_out_param_ptr->mpeg_valid_pol);
1487 
1488     status |= update_by_mnemonic(state,
1489         xpt_clock_polarity[demod_id].reg_addr,
1490         xpt_clock_polarity[demod_id].lsb_pos,
1491         xpt_clock_polarity[demod_id].num_of_bits,
1492         mpeg_out_param_ptr->mpeg_clk_pol);
1493 
1494     status |= update_by_mnemonic(state,
1495         xpt_sync_byte[demod_id].reg_addr,
1496         xpt_sync_byte[demod_id].lsb_pos,
1497         xpt_sync_byte[demod_id].num_of_bits,
1498         mpeg_out_param_ptr->mpeg_sync_pulse_width);
1499 
1500     status |= update_by_mnemonic(state,
1501         xpt_ts_clock_phase[demod_id].reg_addr,
1502         xpt_ts_clock_phase[demod_id].lsb_pos,
1503         xpt_ts_clock_phase[demod_id].num_of_bits,
1504         mpeg_out_param_ptr->mpeg_clk_phase);
1505 
1506     status |= update_by_mnemonic(state,
1507         xpt_lsb_first[demod_id].reg_addr,
1508         xpt_lsb_first[demod_id].lsb_pos,
1509         xpt_lsb_first[demod_id].num_of_bits,
1510         mpeg_out_param_ptr->lsb_or_msb_first);
1511 
1512     switch (mpeg_out_param_ptr->mpeg_error_indication) {
1513     case MXL_HYDRA_MPEG_ERR_REPLACE_SYNC:
1514         status |= update_by_mnemonic(state,
1515             xpt_err_replace_sync[demod_id].reg_addr,
1516             xpt_err_replace_sync[demod_id].lsb_pos,
1517             xpt_err_replace_sync[demod_id].num_of_bits,
1518             MXL_TRUE);
1519         status |= update_by_mnemonic(state,
1520             xpt_err_replace_valid[demod_id].reg_addr,
1521             xpt_err_replace_valid[demod_id].lsb_pos,
1522             xpt_err_replace_valid[demod_id].num_of_bits,
1523             MXL_FALSE);
1524         break;
1525 
1526     case MXL_HYDRA_MPEG_ERR_REPLACE_VALID:
1527         status |= update_by_mnemonic(state,
1528             xpt_err_replace_sync[demod_id].reg_addr,
1529             xpt_err_replace_sync[demod_id].lsb_pos,
1530             xpt_err_replace_sync[demod_id].num_of_bits,
1531             MXL_FALSE);
1532 
1533         status |= update_by_mnemonic(state,
1534             xpt_err_replace_valid[demod_id].reg_addr,
1535             xpt_err_replace_valid[demod_id].lsb_pos,
1536             xpt_err_replace_valid[demod_id].num_of_bits,
1537             MXL_TRUE);
1538         break;
1539 
1540     case MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED:
1541     default:
1542         status |= update_by_mnemonic(state,
1543             xpt_err_replace_sync[demod_id].reg_addr,
1544             xpt_err_replace_sync[demod_id].lsb_pos,
1545             xpt_err_replace_sync[demod_id].num_of_bits,
1546             MXL_FALSE);
1547 
1548         status |= update_by_mnemonic(state,
1549             xpt_err_replace_valid[demod_id].reg_addr,
1550             xpt_err_replace_valid[demod_id].lsb_pos,
1551             xpt_err_replace_valid[demod_id].num_of_bits,
1552             MXL_FALSE);
1553 
1554         break;
1555 
1556     }
1557 
1558     if (mpeg_out_param_ptr->mpeg_mode != MXL_HYDRA_MPEG_MODE_PARALLEL) {
1559         status |= update_by_mnemonic(state,
1560             xpt_enable_output[demod_id].reg_addr,
1561             xpt_enable_output[demod_id].lsb_pos,
1562             xpt_enable_output[demod_id].num_of_bits,
1563             mpeg_out_param_ptr->enable);
1564     }
1565     return status;
1566 }
1567 
1568 static int config_mux(struct mxl *state)
1569 {
1570     update_by_mnemonic(state, 0x9070000C, 0, 1, 0);
1571     update_by_mnemonic(state, 0x9070000C, 1, 1, 0);
1572     update_by_mnemonic(state, 0x9070000C, 2, 1, 0);
1573     update_by_mnemonic(state, 0x9070000C, 3, 1, 0);
1574     update_by_mnemonic(state, 0x9070000C, 4, 1, 0);
1575     update_by_mnemonic(state, 0x9070000C, 5, 1, 0);
1576     update_by_mnemonic(state, 0x9070000C, 6, 1, 0);
1577     update_by_mnemonic(state, 0x9070000C, 7, 1, 0);
1578     update_by_mnemonic(state, 0x90700008, 0, 2, 1);
1579     update_by_mnemonic(state, 0x90700008, 2, 2, 1);
1580     return 0;
1581 }
1582 
1583 static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg)
1584 {
1585     int stat = 0;
1586     u8 *buf;
1587 
1588     if (cfg->fw)
1589         return firmware_download(state, cfg->fw, cfg->fw_len);
1590 
1591     if (!cfg->fw_read)
1592         return -1;
1593 
1594     buf = vmalloc(0x40000);
1595     if (!buf)
1596         return -ENOMEM;
1597 
1598     cfg->fw_read(cfg->fw_priv, buf, 0x40000);
1599     stat = firmware_download(state, buf, 0x40000);
1600     vfree(buf);
1601 
1602     return stat;
1603 }
1604 
1605 static int validate_sku(struct mxl *state)
1606 {
1607     u32 pad_mux_bond = 0, prcm_chip_id = 0, prcm_so_cid = 0;
1608     int status;
1609     u32 type = state->base->type;
1610 
1611     status = read_by_mnemonic(state, 0x90000190, 0, 3, &pad_mux_bond);
1612     status |= read_by_mnemonic(state, 0x80030000, 0, 12, &prcm_chip_id);
1613     status |= read_by_mnemonic(state, 0x80030004, 24, 8, &prcm_so_cid);
1614     if (status)
1615         return -1;
1616 
1617     dev_info(state->i2cdev, "padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\n",
1618         pad_mux_bond, prcm_chip_id, prcm_so_cid);
1619 
1620     if (prcm_chip_id != 0x560) {
1621         switch (pad_mux_bond) {
1622         case MXL_HYDRA_SKU_ID_581:
1623             if (type == MXL_HYDRA_DEVICE_581)
1624                 return 0;
1625             if (type == MXL_HYDRA_DEVICE_581S) {
1626                 state->base->type = MXL_HYDRA_DEVICE_581;
1627                 return 0;
1628             }
1629             break;
1630         case MXL_HYDRA_SKU_ID_584:
1631             if (type == MXL_HYDRA_DEVICE_584)
1632                 return 0;
1633             break;
1634         case MXL_HYDRA_SKU_ID_544:
1635             if (type == MXL_HYDRA_DEVICE_544)
1636                 return 0;
1637             if (type == MXL_HYDRA_DEVICE_542)
1638                 return 0;
1639             break;
1640         case MXL_HYDRA_SKU_ID_582:
1641             if (type == MXL_HYDRA_DEVICE_582)
1642                 return 0;
1643             break;
1644         default:
1645             return -1;
1646         }
1647     } else {
1648 
1649     }
1650     return -1;
1651 }
1652 
1653 static int get_fwinfo(struct mxl *state)
1654 {
1655     int status;
1656     u32 val = 0;
1657 
1658     status = read_by_mnemonic(state, 0x90000190, 0, 3, &val);
1659     if (status)
1660         return status;
1661     dev_info(state->i2cdev, "chipID=%08x\n", val);
1662 
1663     status = read_by_mnemonic(state, 0x80030004, 8, 8, &val);
1664     if (status)
1665         return status;
1666     dev_info(state->i2cdev, "chipVer=%08x\n", val);
1667 
1668     status = read_register(state, HYDRA_FIRMWARE_VERSION, &val);
1669     if (status)
1670         return status;
1671     dev_info(state->i2cdev, "FWVer=%08x\n", val);
1672 
1673     state->base->fwversion = val;
1674     return status;
1675 }
1676 
1677 
1678 static u8 ts_map1_to_1[MXL_HYDRA_DEMOD_MAX] = {
1679     MXL_HYDRA_DEMOD_ID_0,
1680     MXL_HYDRA_DEMOD_ID_1,
1681     MXL_HYDRA_DEMOD_ID_2,
1682     MXL_HYDRA_DEMOD_ID_3,
1683     MXL_HYDRA_DEMOD_ID_4,
1684     MXL_HYDRA_DEMOD_ID_5,
1685     MXL_HYDRA_DEMOD_ID_6,
1686     MXL_HYDRA_DEMOD_ID_7,
1687 };
1688 
1689 static u8 ts_map54x[MXL_HYDRA_DEMOD_MAX] = {
1690     MXL_HYDRA_DEMOD_ID_2,
1691     MXL_HYDRA_DEMOD_ID_3,
1692     MXL_HYDRA_DEMOD_ID_4,
1693     MXL_HYDRA_DEMOD_ID_5,
1694     MXL_HYDRA_DEMOD_MAX,
1695     MXL_HYDRA_DEMOD_MAX,
1696     MXL_HYDRA_DEMOD_MAX,
1697     MXL_HYDRA_DEMOD_MAX,
1698 };
1699 
1700 static int probe(struct mxl *state, struct mxl5xx_cfg *cfg)
1701 {
1702     u32 chipver;
1703     int fw, status, j;
1704     struct MXL_HYDRA_MPEGOUT_PARAM_T mpeg_interface_cfg;
1705 
1706     state->base->ts_map = ts_map1_to_1;
1707 
1708     switch (state->base->type) {
1709     case MXL_HYDRA_DEVICE_581:
1710     case MXL_HYDRA_DEVICE_581S:
1711         state->base->can_clkout = 1;
1712         state->base->demod_num = 8;
1713         state->base->tuner_num = 1;
1714         state->base->sku_type = MXL_HYDRA_SKU_TYPE_581;
1715         break;
1716     case MXL_HYDRA_DEVICE_582:
1717         state->base->can_clkout = 1;
1718         state->base->demod_num = 8;
1719         state->base->tuner_num = 3;
1720         state->base->sku_type = MXL_HYDRA_SKU_TYPE_582;
1721         break;
1722     case MXL_HYDRA_DEVICE_585:
1723         state->base->can_clkout = 0;
1724         state->base->demod_num = 8;
1725         state->base->tuner_num = 4;
1726         state->base->sku_type = MXL_HYDRA_SKU_TYPE_585;
1727         break;
1728     case MXL_HYDRA_DEVICE_544:
1729         state->base->can_clkout = 0;
1730         state->base->demod_num = 4;
1731         state->base->tuner_num = 4;
1732         state->base->sku_type = MXL_HYDRA_SKU_TYPE_544;
1733         state->base->ts_map = ts_map54x;
1734         break;
1735     case MXL_HYDRA_DEVICE_541:
1736     case MXL_HYDRA_DEVICE_541S:
1737         state->base->can_clkout = 0;
1738         state->base->demod_num = 4;
1739         state->base->tuner_num = 1;
1740         state->base->sku_type = MXL_HYDRA_SKU_TYPE_541;
1741         state->base->ts_map = ts_map54x;
1742         break;
1743     case MXL_HYDRA_DEVICE_561:
1744     case MXL_HYDRA_DEVICE_561S:
1745         state->base->can_clkout = 0;
1746         state->base->demod_num = 6;
1747         state->base->tuner_num = 1;
1748         state->base->sku_type = MXL_HYDRA_SKU_TYPE_561;
1749         break;
1750     case MXL_HYDRA_DEVICE_568:
1751         state->base->can_clkout = 0;
1752         state->base->demod_num = 8;
1753         state->base->tuner_num = 1;
1754         state->base->chan_bond = 1;
1755         state->base->sku_type = MXL_HYDRA_SKU_TYPE_568;
1756         break;
1757     case MXL_HYDRA_DEVICE_542:
1758         state->base->can_clkout = 1;
1759         state->base->demod_num = 4;
1760         state->base->tuner_num = 3;
1761         state->base->sku_type = MXL_HYDRA_SKU_TYPE_542;
1762         state->base->ts_map = ts_map54x;
1763         break;
1764     case MXL_HYDRA_DEVICE_TEST:
1765     case MXL_HYDRA_DEVICE_584:
1766     default:
1767         state->base->can_clkout = 0;
1768         state->base->demod_num = 8;
1769         state->base->tuner_num = 4;
1770         state->base->sku_type = MXL_HYDRA_SKU_TYPE_584;
1771         break;
1772     }
1773 
1774     status = validate_sku(state);
1775     if (status)
1776         return status;
1777 
1778     update_by_mnemonic(state, 0x80030014, 9, 1, 1);
1779     update_by_mnemonic(state, 0x8003003C, 12, 1, 1);
1780     status = read_by_mnemonic(state, 0x80030000, 12, 4, &chipver);
1781     if (status)
1782         state->base->chipversion = 0;
1783     else
1784         state->base->chipversion = (chipver == 2) ? 2 : 1;
1785     dev_info(state->i2cdev, "Hydra chip version %u\n",
1786         state->base->chipversion);
1787 
1788     cfg_dev_xtal(state, cfg->clk, cfg->cap, 0);
1789 
1790     fw = firmware_is_alive(state);
1791     if (!fw) {
1792         status = load_fw(state, cfg);
1793         if (status)
1794             return status;
1795     }
1796     get_fwinfo(state);
1797 
1798     config_mux(state);
1799     mpeg_interface_cfg.enable = MXL_ENABLE;
1800     mpeg_interface_cfg.lsb_or_msb_first = MXL_HYDRA_MPEG_SERIAL_MSB_1ST;
1801     /*  supports only (0-104&139)MHz */
1802     if (cfg->ts_clk)
1803         mpeg_interface_cfg.max_mpeg_clk_rate = cfg->ts_clk;
1804     else
1805         mpeg_interface_cfg.max_mpeg_clk_rate = 69; /* 139; */
1806     mpeg_interface_cfg.mpeg_clk_phase = MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG;
1807     mpeg_interface_cfg.mpeg_clk_pol = MXL_HYDRA_MPEG_CLK_IN_PHASE;
1808     /* MXL_HYDRA_MPEG_CLK_GAPPED; */
1809     mpeg_interface_cfg.mpeg_clk_type = MXL_HYDRA_MPEG_CLK_CONTINUOUS;
1810     mpeg_interface_cfg.mpeg_error_indication =
1811         MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED;
1812     mpeg_interface_cfg.mpeg_mode = MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE;
1813     mpeg_interface_cfg.mpeg_sync_pol  = MXL_HYDRA_MPEG_ACTIVE_HIGH;
1814     mpeg_interface_cfg.mpeg_sync_pulse_width  = MXL_HYDRA_MPEG_SYNC_WIDTH_BIT;
1815     mpeg_interface_cfg.mpeg_valid_pol  = MXL_HYDRA_MPEG_ACTIVE_HIGH;
1816 
1817     for (j = 0; j < state->base->demod_num; j++) {
1818         status = config_ts(state, (enum MXL_HYDRA_DEMOD_ID_E) j,
1819                    &mpeg_interface_cfg);
1820         if (status)
1821             return status;
1822     }
1823     set_drive_strength(state, 1);
1824     return 0;
1825 }
1826 
1827 struct dvb_frontend *mxl5xx_attach(struct i2c_adapter *i2c,
1828     struct mxl5xx_cfg *cfg, u32 demod, u32 tuner,
1829     int (**fn_set_input)(struct dvb_frontend *, int))
1830 {
1831     struct mxl *state;
1832     struct mxl_base *base;
1833 
1834     state = kzalloc(sizeof(struct mxl), GFP_KERNEL);
1835     if (!state)
1836         return NULL;
1837 
1838     state->demod = demod;
1839     state->tuner = tuner;
1840     state->tuner_in_use = 0xffffffff;
1841     state->i2cdev = &i2c->dev;
1842 
1843     base = match_base(i2c, cfg->adr);
1844     if (base) {
1845         base->count++;
1846         if (base->count > base->demod_num)
1847             goto fail;
1848         state->base = base;
1849     } else {
1850         base = kzalloc(sizeof(struct mxl_base), GFP_KERNEL);
1851         if (!base)
1852             goto fail;
1853         base->i2c = i2c;
1854         base->adr = cfg->adr;
1855         base->type = cfg->type;
1856         base->count = 1;
1857         mutex_init(&base->i2c_lock);
1858         mutex_init(&base->status_lock);
1859         mutex_init(&base->tune_lock);
1860         INIT_LIST_HEAD(&base->mxls);
1861 
1862         state->base = base;
1863         if (probe(state, cfg) < 0) {
1864             kfree(base);
1865             goto fail;
1866         }
1867         list_add(&base->mxllist, &mxllist);
1868     }
1869     state->fe.ops               = mxl_ops;
1870     state->xbar[0]              = 4;
1871     state->xbar[1]              = demod;
1872     state->xbar[2]              = 8;
1873     state->fe.demodulator_priv  = state;
1874     *fn_set_input               = set_input;
1875 
1876     list_add(&state->mxl, &base->mxls);
1877     return &state->fe;
1878 
1879 fail:
1880     kfree(state);
1881     return NULL;
1882 }
1883 EXPORT_SYMBOL_GPL(mxl5xx_attach);
1884 
1885 MODULE_DESCRIPTION("MaxLinear MxL5xx DVB-S/S2 tuner-demodulator driver");
1886 MODULE_AUTHOR("Ralph and Marcus Metzler, Metzler Brothers Systementwicklung GbR");
1887 MODULE_LICENSE("GPL v2");
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