media/dvb-frontends/mt352_priv.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  Driver for Zarlink DVB-T MT352 demodulator
0004  *
0005  *  Written by Holger Waechtler <holger@qanu.de>
0006  *   and Daniel Mack <daniel@qanu.de>
0007  *
0008  *  AVerMedia AVerTV DVB-T 771 support by
0009  *       Wolfram Joost <dbox2@frokaschwei.de>
0010  *
0011  *  Support for Samsung TDTC9251DH01C(M) tuner
0012  *  Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
0013  *                     Amauri  Celani  <acelani@essegi.net>
0014  *
0015  *  DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
0016  *       Christopher Pascoe <c.pascoe@itee.uq.edu.au>
0017  */
0018
0019 #ifndef _MT352_PRIV_
0020 #define _MT352_PRIV_
0021
0022 #define ID_MT352        0x13
0023
0024 #define msb(x) (((x) >> 8) & 0xff)
0025 #define lsb(x) ((x) & 0xff)
0026
0027 enum mt352_reg_addr {
0028     STATUS_0           = 0x00,
0029     STATUS_1           = 0x01,
0030     STATUS_2           = 0x02,
0031     STATUS_3           = 0x03,
0032     STATUS_4           = 0x04,
0033     INTERRUPT_0        = 0x05,
0034     INTERRUPT_1        = 0x06,
0035     INTERRUPT_2        = 0x07,
0036     INTERRUPT_3        = 0x08,
0037     SNR                = 0x09,
0038     VIT_ERR_CNT_2      = 0x0A,
0039     VIT_ERR_CNT_1      = 0x0B,
0040     VIT_ERR_CNT_0      = 0x0C,
0041     RS_ERR_CNT_2       = 0x0D,
0042     RS_ERR_CNT_1       = 0x0E,
0043     RS_ERR_CNT_0       = 0x0F,
0044     RS_UBC_1           = 0x10,
0045     RS_UBC_0           = 0x11,
0046     AGC_GAIN_3         = 0x12,
0047     AGC_GAIN_2         = 0x13,
0048     AGC_GAIN_1         = 0x14,
0049     AGC_GAIN_0         = 0x15,
0050     FREQ_OFFSET_2      = 0x17,
0051     FREQ_OFFSET_1      = 0x18,
0052     FREQ_OFFSET_0      = 0x19,
0053     TIMING_OFFSET_1    = 0x1A,
0054     TIMING_OFFSET_0    = 0x1B,
0055     CHAN_FREQ_1        = 0x1C,
0056     CHAN_FREQ_0        = 0x1D,
0057     TPS_RECEIVED_1     = 0x1E,
0058     TPS_RECEIVED_0     = 0x1F,
0059     TPS_CURRENT_1      = 0x20,
0060     TPS_CURRENT_0      = 0x21,
0061     TPS_CELL_ID_1      = 0x22,
0062     TPS_CELL_ID_0      = 0x23,
0063     TPS_MISC_DATA_2    = 0x24,
0064     TPS_MISC_DATA_1    = 0x25,
0065     TPS_MISC_DATA_0    = 0x26,
0066     RESET              = 0x50,
0067     TPS_GIVEN_1        = 0x51,
0068     TPS_GIVEN_0        = 0x52,
0069     ACQ_CTL            = 0x53,
0070     TRL_NOMINAL_RATE_1 = 0x54,
0071     TRL_NOMINAL_RATE_0 = 0x55,
0072     INPUT_FREQ_1       = 0x56,
0073     INPUT_FREQ_0       = 0x57,
0074     TUNER_ADDR         = 0x58,
0075     CHAN_START_1       = 0x59,
0076     CHAN_START_0       = 0x5A,
0077     CONT_1             = 0x5B,
0078     CONT_0             = 0x5C,
0079     TUNER_GO           = 0x5D,
0080     STATUS_EN_0        = 0x5F,
0081     STATUS_EN_1        = 0x60,
0082     INTERRUPT_EN_0     = 0x61,
0083     INTERRUPT_EN_1     = 0x62,
0084     INTERRUPT_EN_2     = 0x63,
0085     INTERRUPT_EN_3     = 0x64,
0086     AGC_TARGET         = 0x67,
0087     AGC_CTL            = 0x68,
0088     CAPT_RANGE         = 0x75,
0089     SNR_SELECT_1       = 0x79,
0090     SNR_SELECT_0       = 0x7A,
0091     RS_ERR_PER_1       = 0x7C,
0092     RS_ERR_PER_0       = 0x7D,
0093     CHIP_ID            = 0x7F,
0094     CHAN_STOP_1        = 0x80,
0095     CHAN_STOP_0        = 0x81,
0096     CHAN_STEP_1        = 0x82,
0097     CHAN_STEP_0        = 0x83,
0098     FEC_LOCK_TIME      = 0x85,
0099     OFDM_LOCK_TIME     = 0x86,
0100     ACQ_DELAY          = 0x87,
0101     SCAN_CTL           = 0x88,
0102     CLOCK_CTL          = 0x89,
0103     CONFIG             = 0x8A,
0104     MCLK_RATIO         = 0x8B,
0105     GPP_CTL            = 0x8C,
0106     ADC_CTL_1          = 0x8E,
0107     ADC_CTL_0          = 0x8F
0108 };
0109
0110 /* here we assume 1/6MHz == 166.66kHz stepsize */
0111 #define IF_FREQUENCYx6 217    /* 6 * 36.16666666667MHz */
0112
0113 #endif                          /* _MT352_PRIV_ */