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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Driver for Zarlink DVB-T MT352 demodulator
0004  *
0005  *  Written by Holger Waechtler <holger@qanu.de>
0006  *   and Daniel Mack <daniel@qanu.de>
0007  *
0008  *  AVerMedia AVerTV DVB-T 771 support by
0009  *       Wolfram Joost <dbox2@frokaschwei.de>
0010  *
0011  *  Support for Samsung TDTC9251DH01C(M) tuner
0012  *  Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
0013  *                     Amauri  Celani  <acelani@essegi.net>
0014  *
0015  *  DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
0016  *       Christopher Pascoe <c.pascoe@itee.uq.edu.au>
0017  */
0018 
0019 #include <linux/kernel.h>
0020 #include <linux/module.h>
0021 #include <linux/init.h>
0022 #include <linux/delay.h>
0023 #include <linux/string.h>
0024 #include <linux/slab.h>
0025 
0026 #include <media/dvb_frontend.h>
0027 #include "mt352_priv.h"
0028 #include "mt352.h"
0029 
0030 struct mt352_state {
0031     struct i2c_adapter* i2c;
0032     struct dvb_frontend frontend;
0033 
0034     /* configuration settings */
0035     struct mt352_config config;
0036 };
0037 
0038 static int debug;
0039 #define dprintk(args...) \
0040     do { \
0041         if (debug) printk(KERN_DEBUG "mt352: " args); \
0042     } while (0)
0043 
0044 static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
0045 {
0046     struct mt352_state* state = fe->demodulator_priv;
0047     u8 buf[2] = { reg, val };
0048     struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
0049                    .buf = buf, .len = 2 };
0050     int err = i2c_transfer(state->i2c, &msg, 1);
0051     if (err != 1) {
0052         printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
0053         return err;
0054     }
0055     return 0;
0056 }
0057 
0058 static int _mt352_write(struct dvb_frontend* fe, const u8 ibuf[], int ilen)
0059 {
0060     int err,i;
0061     for (i=0; i < ilen-1; i++)
0062         if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
0063             return err;
0064 
0065     return 0;
0066 }
0067 
0068 static int mt352_read_register(struct mt352_state* state, u8 reg)
0069 {
0070     int ret;
0071     u8 b0 [] = { reg };
0072     u8 b1 [] = { 0 };
0073     struct i2c_msg msg [] = { { .addr = state->config.demod_address,
0074                     .flags = 0,
0075                     .buf = b0, .len = 1 },
0076                   { .addr = state->config.demod_address,
0077                     .flags = I2C_M_RD,
0078                     .buf = b1, .len = 1 } };
0079 
0080     ret = i2c_transfer(state->i2c, msg, 2);
0081 
0082     if (ret != 2) {
0083         printk("%s: readreg error (reg=%d, ret==%i)\n",
0084                __func__, reg, ret);
0085         return ret;
0086     }
0087 
0088     return b1[0];
0089 }
0090 
0091 static int mt352_sleep(struct dvb_frontend* fe)
0092 {
0093     static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
0094 
0095     _mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
0096     return 0;
0097 }
0098 
0099 static void mt352_calc_nominal_rate(struct mt352_state* state,
0100                     u32 bandwidth,
0101                     unsigned char *buf)
0102 {
0103     u32 adc_clock = 20480; /* 20.340 MHz */
0104     u32 bw,value;
0105 
0106     switch (bandwidth) {
0107     case 6000000:
0108         bw = 6;
0109         break;
0110     case 7000000:
0111         bw = 7;
0112         break;
0113     case 8000000:
0114     default:
0115         bw = 8;
0116         break;
0117     }
0118     if (state->config.adc_clock)
0119         adc_clock = state->config.adc_clock;
0120 
0121     value = 64 * bw * (1<<16) / (7 * 8);
0122     value = value * 1000 / adc_clock;
0123     dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
0124         __func__, bw, adc_clock, value);
0125     buf[0] = msb(value);
0126     buf[1] = lsb(value);
0127 }
0128 
0129 static void mt352_calc_input_freq(struct mt352_state* state,
0130                   unsigned char *buf)
0131 {
0132     int adc_clock = 20480; /* 20.480000 MHz */
0133     int if2       = 36167; /* 36.166667 MHz */
0134     int ife,value;
0135 
0136     if (state->config.adc_clock)
0137         adc_clock = state->config.adc_clock;
0138     if (state->config.if2)
0139         if2 = state->config.if2;
0140 
0141     if (adc_clock >= if2 * 2)
0142         ife = if2;
0143     else {
0144         ife = adc_clock - (if2 % adc_clock);
0145         if (ife > adc_clock / 2)
0146             ife = adc_clock - ife;
0147     }
0148     value = -16374 * ife / adc_clock;
0149     dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
0150         __func__, if2, ife, adc_clock, value, value & 0x3fff);
0151     buf[0] = msb(value);
0152     buf[1] = lsb(value);
0153 }
0154 
0155 static int mt352_set_parameters(struct dvb_frontend *fe)
0156 {
0157     struct dtv_frontend_properties *op = &fe->dtv_property_cache;
0158     struct mt352_state* state = fe->demodulator_priv;
0159     unsigned char buf[13];
0160     static unsigned char tuner_go[] = { 0x5d, 0x01 };
0161     static unsigned char fsm_go[]   = { 0x5e, 0x01 };
0162     unsigned int tps = 0;
0163 
0164     switch (op->code_rate_HP) {
0165         case FEC_2_3:
0166             tps |= (1 << 7);
0167             break;
0168         case FEC_3_4:
0169             tps |= (2 << 7);
0170             break;
0171         case FEC_5_6:
0172             tps |= (3 << 7);
0173             break;
0174         case FEC_7_8:
0175             tps |= (4 << 7);
0176             break;
0177         case FEC_1_2:
0178         case FEC_AUTO:
0179             break;
0180         default:
0181             return -EINVAL;
0182     }
0183 
0184     switch (op->code_rate_LP) {
0185         case FEC_2_3:
0186             tps |= (1 << 4);
0187             break;
0188         case FEC_3_4:
0189             tps |= (2 << 4);
0190             break;
0191         case FEC_5_6:
0192             tps |= (3 << 4);
0193             break;
0194         case FEC_7_8:
0195             tps |= (4 << 4);
0196             break;
0197         case FEC_1_2:
0198         case FEC_AUTO:
0199             break;
0200         case FEC_NONE:
0201             if (op->hierarchy == HIERARCHY_AUTO ||
0202                 op->hierarchy == HIERARCHY_NONE)
0203                 break;
0204             fallthrough;
0205         default:
0206             return -EINVAL;
0207     }
0208 
0209     switch (op->modulation) {
0210         case QPSK:
0211             break;
0212         case QAM_AUTO:
0213         case QAM_16:
0214             tps |= (1 << 13);
0215             break;
0216         case QAM_64:
0217             tps |= (2 << 13);
0218             break;
0219         default:
0220             return -EINVAL;
0221     }
0222 
0223     switch (op->transmission_mode) {
0224         case TRANSMISSION_MODE_2K:
0225         case TRANSMISSION_MODE_AUTO:
0226             break;
0227         case TRANSMISSION_MODE_8K:
0228             tps |= (1 << 0);
0229             break;
0230         default:
0231             return -EINVAL;
0232     }
0233 
0234     switch (op->guard_interval) {
0235         case GUARD_INTERVAL_1_32:
0236         case GUARD_INTERVAL_AUTO:
0237             break;
0238         case GUARD_INTERVAL_1_16:
0239             tps |= (1 << 2);
0240             break;
0241         case GUARD_INTERVAL_1_8:
0242             tps |= (2 << 2);
0243             break;
0244         case GUARD_INTERVAL_1_4:
0245             tps |= (3 << 2);
0246             break;
0247         default:
0248             return -EINVAL;
0249     }
0250 
0251     switch (op->hierarchy) {
0252         case HIERARCHY_AUTO:
0253         case HIERARCHY_NONE:
0254             break;
0255         case HIERARCHY_1:
0256             tps |= (1 << 10);
0257             break;
0258         case HIERARCHY_2:
0259             tps |= (2 << 10);
0260             break;
0261         case HIERARCHY_4:
0262             tps |= (3 << 10);
0263             break;
0264         default:
0265             return -EINVAL;
0266     }
0267 
0268 
0269     buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
0270 
0271     buf[1] = msb(tps);      /* TPS_GIVEN_(1|0) */
0272     buf[2] = lsb(tps);
0273 
0274     buf[3] = 0x50;  // old
0275 //  buf[3] = 0xf4;  // pinnacle
0276 
0277     mt352_calc_nominal_rate(state, op->bandwidth_hz, buf+4);
0278     mt352_calc_input_freq(state, buf+6);
0279 
0280     if (state->config.no_tuner) {
0281         if (fe->ops.tuner_ops.set_params) {
0282             fe->ops.tuner_ops.set_params(fe);
0283             if (fe->ops.i2c_gate_ctrl)
0284                 fe->ops.i2c_gate_ctrl(fe, 0);
0285         }
0286 
0287         _mt352_write(fe, buf, 8);
0288         _mt352_write(fe, fsm_go, 2);
0289     } else {
0290         if (fe->ops.tuner_ops.calc_regs) {
0291             fe->ops.tuner_ops.calc_regs(fe, buf+8, 5);
0292             buf[8] <<= 1;
0293             _mt352_write(fe, buf, sizeof(buf));
0294             _mt352_write(fe, tuner_go, 2);
0295         }
0296     }
0297 
0298     return 0;
0299 }
0300 
0301 static int mt352_get_parameters(struct dvb_frontend* fe,
0302                 struct dtv_frontend_properties *op)
0303 {
0304     struct mt352_state* state = fe->demodulator_priv;
0305     u16 tps;
0306     u16 div;
0307     u8 trl;
0308     static const u8 tps_fec_to_api[8] =
0309     {
0310         FEC_1_2,
0311         FEC_2_3,
0312         FEC_3_4,
0313         FEC_5_6,
0314         FEC_7_8,
0315         FEC_AUTO,
0316         FEC_AUTO,
0317         FEC_AUTO
0318     };
0319 
0320     if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
0321         return -EINVAL;
0322 
0323     /* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
0324      * the mt352 sometimes works with the wrong parameters
0325      */
0326     tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
0327     div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
0328     trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
0329 
0330     op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
0331     op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
0332 
0333     switch ( (tps >> 13) & 3)
0334     {
0335         case 0:
0336             op->modulation = QPSK;
0337             break;
0338         case 1:
0339             op->modulation = QAM_16;
0340             break;
0341         case 2:
0342             op->modulation = QAM_64;
0343             break;
0344         default:
0345             op->modulation = QAM_AUTO;
0346             break;
0347     }
0348 
0349     op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
0350 
0351     switch ( (tps >> 2) & 3)
0352     {
0353         case 0:
0354             op->guard_interval = GUARD_INTERVAL_1_32;
0355             break;
0356         case 1:
0357             op->guard_interval = GUARD_INTERVAL_1_16;
0358             break;
0359         case 2:
0360             op->guard_interval = GUARD_INTERVAL_1_8;
0361             break;
0362         case 3:
0363             op->guard_interval = GUARD_INTERVAL_1_4;
0364             break;
0365         default:
0366             op->guard_interval = GUARD_INTERVAL_AUTO;
0367             break;
0368     }
0369 
0370     switch ( (tps >> 10) & 7)
0371     {
0372         case 0:
0373             op->hierarchy = HIERARCHY_NONE;
0374             break;
0375         case 1:
0376             op->hierarchy = HIERARCHY_1;
0377             break;
0378         case 2:
0379             op->hierarchy = HIERARCHY_2;
0380             break;
0381         case 3:
0382             op->hierarchy = HIERARCHY_4;
0383             break;
0384         default:
0385             op->hierarchy = HIERARCHY_AUTO;
0386             break;
0387     }
0388 
0389     op->frequency = (500 * (div - IF_FREQUENCYx6)) / 3 * 1000;
0390 
0391     if (trl == 0x72)
0392         op->bandwidth_hz = 8000000;
0393     else if (trl == 0x64)
0394         op->bandwidth_hz = 7000000;
0395     else
0396         op->bandwidth_hz = 6000000;
0397 
0398 
0399     if (mt352_read_register(state, STATUS_2) & 0x02)
0400         op->inversion = INVERSION_OFF;
0401     else
0402         op->inversion = INVERSION_ON;
0403 
0404     return 0;
0405 }
0406 
0407 static int mt352_read_status(struct dvb_frontend *fe, enum fe_status *status)
0408 {
0409     struct mt352_state* state = fe->demodulator_priv;
0410     int s0, s1, s3;
0411 
0412     /* FIXME:
0413      *
0414      * The MT352 design manual from Zarlink states (page 46-47):
0415      *
0416      * Notes about the TUNER_GO register:
0417      *
0418      * If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
0419      * byte is copied from the tuner to the STATUS_3 register and
0420      * completion of the read operation is indicated by bit-5 of the
0421      * INTERRUPT_3 register.
0422      */
0423 
0424     if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
0425         return -EREMOTEIO;
0426     if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
0427         return -EREMOTEIO;
0428     if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
0429         return -EREMOTEIO;
0430 
0431     *status = 0;
0432     if (s0 & (1 << 4))
0433         *status |= FE_HAS_CARRIER;
0434     if (s0 & (1 << 1))
0435         *status |= FE_HAS_VITERBI;
0436     if (s0 & (1 << 5))
0437         *status |= FE_HAS_LOCK;
0438     if (s1 & (1 << 1))
0439         *status |= FE_HAS_SYNC;
0440     if (s3 & (1 << 6))
0441         *status |= FE_HAS_SIGNAL;
0442 
0443     if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
0444               (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
0445         *status &= ~FE_HAS_LOCK;
0446 
0447     return 0;
0448 }
0449 
0450 static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
0451 {
0452     struct mt352_state* state = fe->demodulator_priv;
0453 
0454     *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
0455            (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
0456            (mt352_read_register (state, RS_ERR_CNT_0));
0457 
0458     return 0;
0459 }
0460 
0461 static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
0462 {
0463     struct mt352_state* state = fe->demodulator_priv;
0464 
0465     /* align the 12 bit AGC gain with the most significant bits */
0466     u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
0467         (mt352_read_register(state, AGC_GAIN_0) << 4);
0468 
0469     /* inverse of gain is signal strength */
0470     *strength = ~signal;
0471     return 0;
0472 }
0473 
0474 static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
0475 {
0476     struct mt352_state* state = fe->demodulator_priv;
0477 
0478     u8 _snr = mt352_read_register (state, SNR);
0479     *snr = (_snr << 8) | _snr;
0480 
0481     return 0;
0482 }
0483 
0484 static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
0485 {
0486     struct mt352_state* state = fe->demodulator_priv;
0487 
0488     *ucblocks = (mt352_read_register (state,  RS_UBC_1) << 8) |
0489             (mt352_read_register (state,  RS_UBC_0));
0490 
0491     return 0;
0492 }
0493 
0494 static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
0495 {
0496     fe_tune_settings->min_delay_ms = 800;
0497     fe_tune_settings->step_size = 0;
0498     fe_tune_settings->max_drift = 0;
0499 
0500     return 0;
0501 }
0502 
0503 static int mt352_init(struct dvb_frontend* fe)
0504 {
0505     struct mt352_state* state = fe->demodulator_priv;
0506 
0507     static u8 mt352_reset_attach [] = { RESET, 0xC0 };
0508 
0509     dprintk("%s: hello\n",__func__);
0510 
0511     if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
0512         (mt352_read_register(state, CONFIG) & 0x20) == 0) {
0513 
0514         /* Do a "hard" reset */
0515         _mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
0516         return state->config.demod_init(fe);
0517     }
0518 
0519     return 0;
0520 }
0521 
0522 static void mt352_release(struct dvb_frontend* fe)
0523 {
0524     struct mt352_state* state = fe->demodulator_priv;
0525     kfree(state);
0526 }
0527 
0528 static const struct dvb_frontend_ops mt352_ops;
0529 
0530 struct dvb_frontend* mt352_attach(const struct mt352_config* config,
0531                   struct i2c_adapter* i2c)
0532 {
0533     struct mt352_state* state = NULL;
0534 
0535     /* allocate memory for the internal state */
0536     state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL);
0537     if (state == NULL) goto error;
0538 
0539     /* setup the state */
0540     state->i2c = i2c;
0541     memcpy(&state->config,config,sizeof(struct mt352_config));
0542 
0543     /* check if the demod is there */
0544     if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
0545 
0546     /* create dvb_frontend */
0547     memcpy(&state->frontend.ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
0548     state->frontend.demodulator_priv = state;
0549     return &state->frontend;
0550 
0551 error:
0552     kfree(state);
0553     return NULL;
0554 }
0555 
0556 static const struct dvb_frontend_ops mt352_ops = {
0557     .delsys = { SYS_DVBT },
0558     .info = {
0559         .name           = "Zarlink MT352 DVB-T",
0560         .frequency_min_hz   = 174 * MHz,
0561         .frequency_max_hz   = 862 * MHz,
0562         .frequency_stepsize_hz  = 166667,
0563         .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
0564             FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
0565             FE_CAN_FEC_AUTO |
0566             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
0567             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
0568             FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
0569             FE_CAN_MUTE_TS
0570     },
0571 
0572     .release = mt352_release,
0573 
0574     .init = mt352_init,
0575     .sleep = mt352_sleep,
0576     .write = _mt352_write,
0577 
0578     .set_frontend = mt352_set_parameters,
0579     .get_frontend = mt352_get_parameters,
0580     .get_tune_settings = mt352_get_tune_settings,
0581 
0582     .read_status = mt352_read_status,
0583     .read_ber = mt352_read_ber,
0584     .read_signal_strength = mt352_read_signal_strength,
0585     .read_snr = mt352_read_snr,
0586     .read_ucblocks = mt352_read_ucblocks,
0587 };
0588 
0589 module_param(debug, int, 0644);
0590 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
0591 
0592 MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
0593 MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
0594 MODULE_LICENSE("GPL");
0595 
0596 EXPORT_SYMBOL(mt352_attach);
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