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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003     Driver for Zarlink VP310/MT312/ZL10313 Satellite Channel Decoder
0004 
0005     Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
0006     Copyright (C) 2008 Matthias Schwarzott <zzam@gentoo.org>
0007 
0008 
0009     References:
0010     http://products.zarlink.com/product_profiles/MT312.htm
0011     http://products.zarlink.com/product_profiles/SL1935.htm
0012 */
0013 
0014 #include <linux/delay.h>
0015 #include <linux/errno.h>
0016 #include <linux/init.h>
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/string.h>
0020 #include <linux/slab.h>
0021 
0022 #include <media/dvb_frontend.h>
0023 #include "mt312_priv.h"
0024 #include "mt312.h"
0025 
0026 /* Max transfer size done by I2C transfer functions */
0027 #define MAX_XFER_SIZE  64
0028 
0029 struct mt312_state {
0030     struct i2c_adapter *i2c;
0031     /* configuration settings */
0032     const struct mt312_config *config;
0033     struct dvb_frontend frontend;
0034 
0035     u8 id;
0036     unsigned long xtal;
0037     u8 freq_mult;
0038 };
0039 
0040 static int debug;
0041 #define dprintk(args...) \
0042     do { \
0043         if (debug) \
0044             printk(KERN_DEBUG "mt312: " args); \
0045     } while (0)
0046 
0047 #define MT312_PLL_CLK       10000000UL  /* 10 MHz */
0048 #define MT312_PLL_CLK_10_111    10111000UL  /* 10.111 MHz */
0049 
0050 static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
0051               u8 *buf, const size_t count)
0052 {
0053     int ret;
0054     struct i2c_msg msg[2];
0055     u8 regbuf[1] = { reg };
0056 
0057     msg[0].addr = state->config->demod_address;
0058     msg[0].flags = 0;
0059     msg[0].buf = regbuf;
0060     msg[0].len = 1;
0061     msg[1].addr = state->config->demod_address;
0062     msg[1].flags = I2C_M_RD;
0063     msg[1].buf = buf;
0064     msg[1].len = count;
0065 
0066     ret = i2c_transfer(state->i2c, msg, 2);
0067 
0068     if (ret != 2) {
0069         printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret);
0070         return -EREMOTEIO;
0071     }
0072 
0073     if (debug) {
0074         int i;
0075         dprintk("R(%d):", reg & 0x7f);
0076         for (i = 0; i < count; i++)
0077             printk(KERN_CONT " %02x", buf[i]);
0078         printk("\n");
0079     }
0080 
0081     return 0;
0082 }
0083 
0084 static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg,
0085                const u8 *src, const size_t count)
0086 {
0087     int ret;
0088     u8 buf[MAX_XFER_SIZE];
0089     struct i2c_msg msg;
0090 
0091     if (1 + count > sizeof(buf)) {
0092         printk(KERN_WARNING
0093                "mt312: write: len=%zu is too big!\n", count);
0094         return -EINVAL;
0095     }
0096 
0097     if (debug) {
0098         int i;
0099         dprintk("W(%d):", reg & 0x7f);
0100         for (i = 0; i < count; i++)
0101             printk(KERN_CONT " %02x", src[i]);
0102         printk("\n");
0103     }
0104 
0105     buf[0] = reg;
0106     memcpy(&buf[1], src, count);
0107 
0108     msg.addr = state->config->demod_address;
0109     msg.flags = 0;
0110     msg.buf = buf;
0111     msg.len = count + 1;
0112 
0113     ret = i2c_transfer(state->i2c, &msg, 1);
0114 
0115     if (ret != 1) {
0116         dprintk("%s: ret == %d\n", __func__, ret);
0117         return -EREMOTEIO;
0118     }
0119 
0120     return 0;
0121 }
0122 
0123 static inline int mt312_readreg(struct mt312_state *state,
0124                 const enum mt312_reg_addr reg, u8 *val)
0125 {
0126     return mt312_read(state, reg, val, 1);
0127 }
0128 
0129 static inline int mt312_writereg(struct mt312_state *state,
0130                  const enum mt312_reg_addr reg, const u8 val)
0131 {
0132     u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
0133 
0134 
0135     return mt312_write(state, reg, &tmp, 1);
0136 }
0137 
0138 static int mt312_reset(struct mt312_state *state, const u8 full)
0139 {
0140     return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
0141 }
0142 
0143 static int mt312_get_inversion(struct mt312_state *state,
0144                    enum fe_spectral_inversion *i)
0145 {
0146     int ret;
0147     u8 vit_mode;
0148 
0149     ret = mt312_readreg(state, VIT_MODE, &vit_mode);
0150     if (ret < 0)
0151         return ret;
0152 
0153     if (vit_mode & 0x80)    /* auto inversion was used */
0154         *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
0155 
0156     return 0;
0157 }
0158 
0159 static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
0160 {
0161     int ret;
0162     u8 sym_rate_h;
0163     u8 dec_ratio;
0164     u16 sym_rat_op;
0165     u16 monitor;
0166     u8 buf[2];
0167 
0168     ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
0169     if (ret < 0)
0170         return ret;
0171 
0172     if (sym_rate_h & 0x80) {
0173         /* symbol rate search was used */
0174         ret = mt312_writereg(state, MON_CTRL, 0x03);
0175         if (ret < 0)
0176             return ret;
0177 
0178         ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
0179         if (ret < 0)
0180             return ret;
0181 
0182         monitor = (buf[0] << 8) | buf[1];
0183 
0184         dprintk("sr(auto) = %u\n",
0185             DIV_ROUND_CLOSEST(monitor * 15625, 4));
0186     } else {
0187         ret = mt312_writereg(state, MON_CTRL, 0x05);
0188         if (ret < 0)
0189             return ret;
0190 
0191         ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
0192         if (ret < 0)
0193             return ret;
0194 
0195         dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
0196 
0197         ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
0198         if (ret < 0)
0199             return ret;
0200 
0201         sym_rat_op = (buf[0] << 8) | buf[1];
0202 
0203         dprintk("sym_rat_op=%d dec_ratio=%d\n",
0204                sym_rat_op, dec_ratio);
0205         dprintk("*sr(manual) = %lu\n",
0206                (((state->xtal * 8192) / (sym_rat_op + 8192)) *
0207             2) - dec_ratio);
0208     }
0209 
0210     return 0;
0211 }
0212 
0213 static int mt312_get_code_rate(struct mt312_state *state, enum fe_code_rate *cr)
0214 {
0215     const enum fe_code_rate fec_tab[8] =
0216         { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
0217         FEC_AUTO, FEC_AUTO };
0218 
0219     int ret;
0220     u8 fec_status;
0221 
0222     ret = mt312_readreg(state, FEC_STATUS, &fec_status);
0223     if (ret < 0)
0224         return ret;
0225 
0226     *cr = fec_tab[(fec_status >> 4) & 0x07];
0227 
0228     return 0;
0229 }
0230 
0231 static int mt312_initfe(struct dvb_frontend *fe)
0232 {
0233     struct mt312_state *state = fe->demodulator_priv;
0234     int ret;
0235     u8 buf[2];
0236 
0237     /* wake up */
0238     ret = mt312_writereg(state, CONFIG,
0239             (state->freq_mult == 6 ? 0x88 : 0x8c));
0240     if (ret < 0)
0241         return ret;
0242 
0243     /* wait at least 150 usec */
0244     udelay(150);
0245 
0246     /* full reset */
0247     ret = mt312_reset(state, 1);
0248     if (ret < 0)
0249         return ret;
0250 
0251 /* Per datasheet, write correct values. 09/28/03 ACCJr.
0252  * If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */
0253     {
0254         u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02,
0255                   0x01, 0x00, 0x00, 0x00 };
0256 
0257         ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
0258         if (ret < 0)
0259             return ret;
0260     }
0261 
0262     switch (state->id) {
0263     case ID_ZL10313:
0264         /* enable ADC */
0265         ret = mt312_writereg(state, GPP_CTRL, 0x80);
0266         if (ret < 0)
0267             return ret;
0268 
0269         /* configure ZL10313 for optimal ADC performance */
0270         buf[0] = 0x80;
0271         buf[1] = 0xB0;
0272         ret = mt312_write(state, HW_CTRL, buf, 2);
0273         if (ret < 0)
0274             return ret;
0275 
0276         /* enable MPEG output and ADCs */
0277         ret = mt312_writereg(state, HW_CTRL, 0x00);
0278         if (ret < 0)
0279             return ret;
0280 
0281         ret = mt312_writereg(state, MPEG_CTRL, 0x00);
0282         if (ret < 0)
0283             return ret;
0284 
0285         break;
0286     }
0287 
0288     /* SYS_CLK */
0289     buf[0] = DIV_ROUND_CLOSEST(state->xtal * state->freq_mult * 2, 1000000);
0290 
0291     /* DISEQC_RATIO */
0292     buf[1] = DIV_ROUND_CLOSEST(state->xtal, 22000 * 4);
0293 
0294     ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
0295     if (ret < 0)
0296         return ret;
0297 
0298     ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
0299     if (ret < 0)
0300         return ret;
0301 
0302     /* different MOCLK polarity */
0303     switch (state->id) {
0304     case ID_ZL10313:
0305         buf[0] = 0x33;
0306         break;
0307     default:
0308         buf[0] = 0x53;
0309         break;
0310     }
0311 
0312     ret = mt312_writereg(state, OP_CTRL, buf[0]);
0313     if (ret < 0)
0314         return ret;
0315 
0316     /* TS_SW_LIM */
0317     buf[0] = 0x8c;
0318     buf[1] = 0x98;
0319 
0320     ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
0321     if (ret < 0)
0322         return ret;
0323 
0324     ret = mt312_writereg(state, CS_SW_LIM, 0x69);
0325     if (ret < 0)
0326         return ret;
0327 
0328     return 0;
0329 }
0330 
0331 static int mt312_send_master_cmd(struct dvb_frontend *fe,
0332                  struct dvb_diseqc_master_cmd *c)
0333 {
0334     struct mt312_state *state = fe->demodulator_priv;
0335     int ret;
0336     u8 diseqc_mode;
0337 
0338     if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
0339         return -EINVAL;
0340 
0341     ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
0342     if (ret < 0)
0343         return ret;
0344 
0345     ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
0346     if (ret < 0)
0347         return ret;
0348 
0349     ret = mt312_writereg(state, DISEQC_MODE,
0350                  (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
0351                  | 0x04);
0352     if (ret < 0)
0353         return ret;
0354 
0355     /* is there a better way to wait for message to be transmitted */
0356     msleep(100);
0357 
0358     /* set DISEQC_MODE[2:0] to zero if a return message is expected */
0359     if (c->msg[0] & 0x02) {
0360         ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
0361         if (ret < 0)
0362             return ret;
0363     }
0364 
0365     return 0;
0366 }
0367 
0368 static int mt312_send_burst(struct dvb_frontend *fe,
0369                 const enum fe_sec_mini_cmd c)
0370 {
0371     struct mt312_state *state = fe->demodulator_priv;
0372     const u8 mini_tab[2] = { 0x02, 0x03 };
0373 
0374     int ret;
0375     u8 diseqc_mode;
0376 
0377     if (c > SEC_MINI_B)
0378         return -EINVAL;
0379 
0380     ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
0381     if (ret < 0)
0382         return ret;
0383 
0384     ret = mt312_writereg(state, DISEQC_MODE,
0385                  (diseqc_mode & 0x40) | mini_tab[c]);
0386     if (ret < 0)
0387         return ret;
0388 
0389     return 0;
0390 }
0391 
0392 static int mt312_set_tone(struct dvb_frontend *fe,
0393               const enum fe_sec_tone_mode t)
0394 {
0395     struct mt312_state *state = fe->demodulator_priv;
0396     const u8 tone_tab[2] = { 0x01, 0x00 };
0397 
0398     int ret;
0399     u8 diseqc_mode;
0400 
0401     if (t > SEC_TONE_OFF)
0402         return -EINVAL;
0403 
0404     ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
0405     if (ret < 0)
0406         return ret;
0407 
0408     ret = mt312_writereg(state, DISEQC_MODE,
0409                  (diseqc_mode & 0x40) | tone_tab[t]);
0410     if (ret < 0)
0411         return ret;
0412 
0413     return 0;
0414 }
0415 
0416 static int mt312_set_voltage(struct dvb_frontend *fe,
0417                  const enum fe_sec_voltage v)
0418 {
0419     struct mt312_state *state = fe->demodulator_priv;
0420     const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
0421     u8 val;
0422 
0423     if (v > SEC_VOLTAGE_OFF)
0424         return -EINVAL;
0425 
0426     val = volt_tab[v];
0427     if (state->config->voltage_inverted)
0428         val ^= 0x40;
0429 
0430     return mt312_writereg(state, DISEQC_MODE, val);
0431 }
0432 
0433 static int mt312_read_status(struct dvb_frontend *fe, enum fe_status *s)
0434 {
0435     struct mt312_state *state = fe->demodulator_priv;
0436     int ret;
0437     u8 status[3];
0438 
0439     *s = 0;
0440 
0441     ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
0442     if (ret < 0)
0443         return ret;
0444 
0445     dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n",
0446         status[0], status[1], status[2]);
0447 
0448     if (status[0] & 0xc0)
0449         *s |= FE_HAS_SIGNAL;    /* signal noise ratio */
0450     if (status[0] & 0x04)
0451         *s |= FE_HAS_CARRIER;   /* qpsk carrier lock */
0452     if (status[2] & 0x02)
0453         *s |= FE_HAS_VITERBI;   /* viterbi lock */
0454     if (status[2] & 0x04)
0455         *s |= FE_HAS_SYNC;  /* byte align lock */
0456     if (status[0] & 0x01)
0457         *s |= FE_HAS_LOCK;  /* qpsk lock */
0458 
0459     return 0;
0460 }
0461 
0462 static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber)
0463 {
0464     struct mt312_state *state = fe->demodulator_priv;
0465     int ret;
0466     u8 buf[3];
0467 
0468     ret = mt312_read(state, RS_BERCNT_H, buf, 3);
0469     if (ret < 0)
0470         return ret;
0471 
0472     *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
0473 
0474     return 0;
0475 }
0476 
0477 static int mt312_read_signal_strength(struct dvb_frontend *fe,
0478                       u16 *signal_strength)
0479 {
0480     struct mt312_state *state = fe->demodulator_priv;
0481     int ret;
0482     u8 buf[3];
0483     u16 agc;
0484     s16 err_db;
0485 
0486     ret = mt312_read(state, AGC_H, buf, sizeof(buf));
0487     if (ret < 0)
0488         return ret;
0489 
0490     agc = (buf[0] << 6) | (buf[1] >> 2);
0491     err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
0492 
0493     *signal_strength = agc;
0494 
0495     dprintk("agc=%08x err_db=%hd\n", agc, err_db);
0496 
0497     return 0;
0498 }
0499 
0500 static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr)
0501 {
0502     struct mt312_state *state = fe->demodulator_priv;
0503     int ret;
0504     u8 buf[2];
0505 
0506     ret = mt312_read(state, M_SNR_H, buf, sizeof(buf));
0507     if (ret < 0)
0508         return ret;
0509 
0510     *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
0511 
0512     return 0;
0513 }
0514 
0515 static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc)
0516 {
0517     struct mt312_state *state = fe->demodulator_priv;
0518     int ret;
0519     u8 buf[2];
0520 
0521     ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf));
0522     if (ret < 0)
0523         return ret;
0524 
0525     *ubc = (buf[0] << 8) | buf[1];
0526 
0527     return 0;
0528 }
0529 
0530 static int mt312_set_frontend(struct dvb_frontend *fe)
0531 {
0532     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0533     struct mt312_state *state = fe->demodulator_priv;
0534     int ret;
0535     u8 buf[5], config_val;
0536     u16 sr;
0537 
0538     const u8 fec_tab[10] =
0539         { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
0540     const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
0541 
0542     dprintk("%s: Freq %d\n", __func__, p->frequency);
0543 
0544     if ((p->frequency < fe->ops.info.frequency_min_hz / kHz)
0545         || (p->frequency > fe->ops.info.frequency_max_hz / kHz))
0546         return -EINVAL;
0547 
0548     if (((int)p->inversion < INVERSION_OFF)
0549         || (p->inversion > INVERSION_ON))
0550         return -EINVAL;
0551 
0552     if ((p->symbol_rate < fe->ops.info.symbol_rate_min)
0553         || (p->symbol_rate > fe->ops.info.symbol_rate_max))
0554         return -EINVAL;
0555 
0556     if (((int)p->fec_inner < FEC_NONE)
0557         || (p->fec_inner > FEC_AUTO))
0558         return -EINVAL;
0559 
0560     if ((p->fec_inner == FEC_4_5)
0561         || (p->fec_inner == FEC_8_9))
0562         return -EINVAL;
0563 
0564     switch (state->id) {
0565     case ID_VP310:
0566     /* For now we will do this only for the VP310.
0567      * It should be better for the mt312 as well,
0568      * but tuning will be slower. ACCJr 09/29/03
0569      */
0570         ret = mt312_readreg(state, CONFIG, &config_val);
0571         if (ret < 0)
0572             return ret;
0573         if (p->symbol_rate >= 30000000) {
0574             /* Note that 30MS/s should use 90MHz */
0575             if (state->freq_mult == 6) {
0576                 /* We are running 60MHz */
0577                 state->freq_mult = 9;
0578                 ret = mt312_initfe(fe);
0579                 if (ret < 0)
0580                     return ret;
0581             }
0582         } else {
0583             if (state->freq_mult == 9) {
0584                 /* We are running 90MHz */
0585                 state->freq_mult = 6;
0586                 ret = mt312_initfe(fe);
0587                 if (ret < 0)
0588                     return ret;
0589             }
0590         }
0591         break;
0592 
0593     case ID_MT312:
0594     case ID_ZL10313:
0595         break;
0596 
0597     default:
0598         return -EINVAL;
0599     }
0600 
0601     if (fe->ops.tuner_ops.set_params) {
0602         fe->ops.tuner_ops.set_params(fe);
0603         if (fe->ops.i2c_gate_ctrl)
0604             fe->ops.i2c_gate_ctrl(fe, 0);
0605     }
0606 
0607     /* sr = (u16)(sr * 256.0 / 1000000.0) */
0608     sr = DIV_ROUND_CLOSEST(p->symbol_rate * 4, 15625);
0609 
0610     /* SYM_RATE */
0611     buf[0] = (sr >> 8) & 0x3f;
0612     buf[1] = (sr >> 0) & 0xff;
0613 
0614     /* VIT_MODE */
0615     buf[2] = inv_tab[p->inversion] | fec_tab[p->fec_inner];
0616 
0617     /* QPSK_CTRL */
0618     buf[3] = 0x40;      /* swap I and Q before QPSK demodulation */
0619 
0620     if (p->symbol_rate < 10000000)
0621         buf[3] |= 0x04; /* use afc mode */
0622 
0623     /* GO */
0624     buf[4] = 0x01;
0625 
0626     ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
0627     if (ret < 0)
0628         return ret;
0629 
0630     ret = mt312_reset(state, 0);
0631     if (ret < 0)
0632         return ret;
0633 
0634     return 0;
0635 }
0636 
0637 static int mt312_get_frontend(struct dvb_frontend *fe,
0638                   struct dtv_frontend_properties *p)
0639 {
0640     struct mt312_state *state = fe->demodulator_priv;
0641     int ret;
0642 
0643     ret = mt312_get_inversion(state, &p->inversion);
0644     if (ret < 0)
0645         return ret;
0646 
0647     ret = mt312_get_symbol_rate(state, &p->symbol_rate);
0648     if (ret < 0)
0649         return ret;
0650 
0651     ret = mt312_get_code_rate(state, &p->fec_inner);
0652     if (ret < 0)
0653         return ret;
0654 
0655     return 0;
0656 }
0657 
0658 static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
0659 {
0660     struct mt312_state *state = fe->demodulator_priv;
0661 
0662     u8 val = 0x00;
0663     int ret;
0664 
0665     switch (state->id) {
0666     case ID_ZL10313:
0667         ret = mt312_readreg(state, GPP_CTRL, &val);
0668         if (ret < 0)
0669             goto error;
0670 
0671         /* preserve this bit to not accidentally shutdown ADC */
0672         val &= 0x80;
0673         break;
0674     }
0675 
0676     if (enable)
0677         val |= 0x40;
0678     else
0679         val &= ~0x40;
0680 
0681     ret = mt312_writereg(state, GPP_CTRL, val);
0682 
0683 error:
0684     return ret;
0685 }
0686 
0687 static int mt312_sleep(struct dvb_frontend *fe)
0688 {
0689     struct mt312_state *state = fe->demodulator_priv;
0690     int ret;
0691     u8 config;
0692 
0693     /* reset all registers to defaults */
0694     ret = mt312_reset(state, 1);
0695     if (ret < 0)
0696         return ret;
0697 
0698     if (state->id == ID_ZL10313) {
0699         /* reset ADC */
0700         ret = mt312_writereg(state, GPP_CTRL, 0x00);
0701         if (ret < 0)
0702             return ret;
0703 
0704         /* full shutdown of ADCs, mpeg bus tristated */
0705         ret = mt312_writereg(state, HW_CTRL, 0x0d);
0706         if (ret < 0)
0707             return ret;
0708     }
0709 
0710     ret = mt312_readreg(state, CONFIG, &config);
0711     if (ret < 0)
0712         return ret;
0713 
0714     /* enter standby */
0715     ret = mt312_writereg(state, CONFIG, config & 0x7f);
0716     if (ret < 0)
0717         return ret;
0718 
0719     return 0;
0720 }
0721 
0722 static int mt312_get_tune_settings(struct dvb_frontend *fe,
0723         struct dvb_frontend_tune_settings *fesettings)
0724 {
0725     fesettings->min_delay_ms = 50;
0726     fesettings->step_size = 0;
0727     fesettings->max_drift = 0;
0728     return 0;
0729 }
0730 
0731 static void mt312_release(struct dvb_frontend *fe)
0732 {
0733     struct mt312_state *state = fe->demodulator_priv;
0734     kfree(state);
0735 }
0736 
0737 #define MT312_SYS_CLK       90000000UL  /* 90 MHz */
0738 static const struct dvb_frontend_ops mt312_ops = {
0739     .delsys = { SYS_DVBS },
0740     .info = {
0741         .name = "Zarlink ???? DVB-S",
0742         .frequency_min_hz =  950 * MHz,
0743         .frequency_max_hz = 2150 * MHz,
0744         /* FIXME: adjust freq to real used xtal */
0745         .frequency_stepsize_hz = MT312_PLL_CLK / 128,
0746         .symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */
0747         .symbol_rate_max = MT312_SYS_CLK / 2,
0748         .caps =
0749             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
0750             FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
0751             FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
0752             FE_CAN_RECOVER
0753     },
0754 
0755     .release = mt312_release,
0756 
0757     .init = mt312_initfe,
0758     .sleep = mt312_sleep,
0759     .i2c_gate_ctrl = mt312_i2c_gate_ctrl,
0760 
0761     .set_frontend = mt312_set_frontend,
0762     .get_frontend = mt312_get_frontend,
0763     .get_tune_settings = mt312_get_tune_settings,
0764 
0765     .read_status = mt312_read_status,
0766     .read_ber = mt312_read_ber,
0767     .read_signal_strength = mt312_read_signal_strength,
0768     .read_snr = mt312_read_snr,
0769     .read_ucblocks = mt312_read_ucblocks,
0770 
0771     .diseqc_send_master_cmd = mt312_send_master_cmd,
0772     .diseqc_send_burst = mt312_send_burst,
0773     .set_tone = mt312_set_tone,
0774     .set_voltage = mt312_set_voltage,
0775 };
0776 
0777 struct dvb_frontend *mt312_attach(const struct mt312_config *config,
0778                     struct i2c_adapter *i2c)
0779 {
0780     struct mt312_state *state = NULL;
0781 
0782     /* allocate memory for the internal state */
0783     state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL);
0784     if (state == NULL)
0785         goto error;
0786 
0787     /* setup the state */
0788     state->config = config;
0789     state->i2c = i2c;
0790 
0791     /* check if the demod is there */
0792     if (mt312_readreg(state, ID, &state->id) < 0)
0793         goto error;
0794 
0795     /* create dvb_frontend */
0796     memcpy(&state->frontend.ops, &mt312_ops,
0797         sizeof(struct dvb_frontend_ops));
0798     state->frontend.demodulator_priv = state;
0799 
0800     switch (state->id) {
0801     case ID_VP310:
0802         strscpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S",
0803             sizeof(state->frontend.ops.info.name));
0804         state->xtal = MT312_PLL_CLK;
0805         state->freq_mult = 9;
0806         break;
0807     case ID_MT312:
0808         strscpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S",
0809             sizeof(state->frontend.ops.info.name));
0810         state->xtal = MT312_PLL_CLK;
0811         state->freq_mult = 6;
0812         break;
0813     case ID_ZL10313:
0814         strscpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S",
0815             sizeof(state->frontend.ops.info.name));
0816         state->xtal = MT312_PLL_CLK_10_111;
0817         state->freq_mult = 9;
0818         break;
0819     default:
0820         printk(KERN_WARNING "Only Zarlink VP310/MT312/ZL10313 are supported chips.\n");
0821         goto error;
0822     }
0823 
0824     return &state->frontend;
0825 
0826 error:
0827     kfree(state);
0828     return NULL;
0829 }
0830 EXPORT_SYMBOL(mt312_attach);
0831 
0832 module_param(debug, int, 0644);
0833 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
0834 
0835 MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver");
0836 MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
0837 MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>");
0838 MODULE_LICENSE("GPL");
0839
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