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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Panasonic MN88472 DVB-T/T2/C demodulator driver
0004  *
0005  * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
0006  */
0007 
0008 #include "mn88472_priv.h"
0009 
0010 static int mn88472_get_tune_settings(struct dvb_frontend *fe,
0011                      struct dvb_frontend_tune_settings *s)
0012 {
0013     s->min_delay_ms = 1000;
0014     return 0;
0015 }
0016 
0017 static int mn88472_read_status(struct dvb_frontend *fe, enum fe_status *status)
0018 {
0019     struct i2c_client *client = fe->demodulator_priv;
0020     struct mn88472_dev *dev = i2c_get_clientdata(client);
0021     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0022     int ret, i, stmp;
0023     unsigned int utmp, utmp1, utmp2;
0024     u8 buf[5];
0025 
0026     if (!dev->active) {
0027         ret = -EAGAIN;
0028         goto err;
0029     }
0030 
0031     switch (c->delivery_system) {
0032     case SYS_DVBT:
0033         ret = regmap_read(dev->regmap[0], 0x7f, &utmp);
0034         if (ret)
0035             goto err;
0036         if ((utmp & 0x0f) >= 0x09)
0037             *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
0038                   FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
0039         else
0040             *status = 0;
0041         break;
0042     case SYS_DVBT2:
0043         ret = regmap_read(dev->regmap[2], 0x92, &utmp);
0044         if (ret)
0045             goto err;
0046         if ((utmp & 0x0f) >= 0x0d)
0047             *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
0048                   FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
0049         else if ((utmp & 0x0f) >= 0x0a)
0050             *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
0051                   FE_HAS_VITERBI;
0052         else if ((utmp & 0x0f) >= 0x07)
0053             *status = FE_HAS_SIGNAL | FE_HAS_CARRIER;
0054         else
0055             *status = 0;
0056         break;
0057     case SYS_DVBC_ANNEX_A:
0058         ret = regmap_read(dev->regmap[1], 0x84, &utmp);
0059         if (ret)
0060             goto err;
0061         if ((utmp & 0x0f) >= 0x08)
0062             *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
0063                   FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
0064         else
0065             *status = 0;
0066         break;
0067     default:
0068         ret = -EINVAL;
0069         goto err;
0070     }
0071 
0072     /* Signal strength */
0073     if (*status & FE_HAS_SIGNAL) {
0074         for (i = 0; i < 2; i++) {
0075             ret = regmap_bulk_read(dev->regmap[2], 0x8e + i,
0076                            &buf[i], 1);
0077             if (ret)
0078                 goto err;
0079         }
0080 
0081         utmp1 = buf[0] << 8 | buf[1] << 0 | buf[0] >> 2;
0082         dev_dbg(&client->dev, "strength=%u\n", utmp1);
0083 
0084         c->strength.stat[0].scale = FE_SCALE_RELATIVE;
0085         c->strength.stat[0].uvalue = utmp1;
0086     } else {
0087         c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0088     }
0089 
0090     /* CNR */
0091     if (*status & FE_HAS_VITERBI && c->delivery_system == SYS_DVBT) {
0092         /* DVB-T CNR */
0093         ret = regmap_bulk_read(dev->regmap[0], 0x9c, buf, 2);
0094         if (ret)
0095             goto err;
0096 
0097         utmp = buf[0] << 8 | buf[1] << 0;
0098         if (utmp) {
0099             /* CNR[dB]: 10 * log10(65536 / value) + 2 */
0100             /* log10(65536) = 80807124, 0.2 = 3355443 */
0101             stmp = ((u64)80807124 - intlog10(utmp) + 3355443)
0102                    * 10000 >> 24;
0103 
0104             dev_dbg(&client->dev, "cnr=%d value=%u\n", stmp, utmp);
0105         } else {
0106             stmp = 0;
0107         }
0108 
0109         c->cnr.stat[0].svalue = stmp;
0110         c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
0111     } else if (*status & FE_HAS_VITERBI &&
0112            c->delivery_system == SYS_DVBT2) {
0113         /* DVB-T2 CNR */
0114         for (i = 0; i < 3; i++) {
0115             ret = regmap_bulk_read(dev->regmap[2], 0xbc + i,
0116                            &buf[i], 1);
0117             if (ret)
0118                 goto err;
0119         }
0120 
0121         utmp = buf[1] << 8 | buf[2] << 0;
0122         utmp1 = (buf[0] >> 2) & 0x01; /* 0=SISO, 1=MISO */
0123         if (utmp) {
0124             if (utmp1) {
0125                 /* CNR[dB]: 10 * log10(16384 / value) - 6 */
0126                 /* log10(16384) = 70706234, 0.6 = 10066330 */
0127                 stmp = ((u64)70706234 - intlog10(utmp)
0128                        - 10066330) * 10000 >> 24;
0129                 dev_dbg(&client->dev, "cnr=%d value=%u MISO\n",
0130                     stmp, utmp);
0131             } else {
0132                 /* CNR[dB]: 10 * log10(65536 / value) + 2 */
0133                 /* log10(65536) = 80807124, 0.2 = 3355443 */
0134                 stmp = ((u64)80807124 - intlog10(utmp)
0135                        + 3355443) * 10000 >> 24;
0136 
0137                 dev_dbg(&client->dev, "cnr=%d value=%u SISO\n",
0138                     stmp, utmp);
0139             }
0140         } else {
0141             stmp = 0;
0142         }
0143 
0144         c->cnr.stat[0].svalue = stmp;
0145         c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
0146     } else if (*status & FE_HAS_VITERBI &&
0147            c->delivery_system == SYS_DVBC_ANNEX_A) {
0148         /* DVB-C CNR */
0149         ret = regmap_bulk_read(dev->regmap[1], 0xa1, buf, 4);
0150         if (ret)
0151             goto err;
0152 
0153         utmp1 = buf[0] << 8 | buf[1] << 0; /* signal */
0154         utmp2 = buf[2] << 8 | buf[3] << 0; /* noise */
0155         if (utmp1 && utmp2) {
0156             /* CNR[dB]: 10 * log10(8 * (signal / noise)) */
0157             /* log10(8) = 15151336 */
0158             stmp = ((u64)15151336 + intlog10(utmp1)
0159                    - intlog10(utmp2)) * 10000 >> 24;
0160 
0161             dev_dbg(&client->dev, "cnr=%d signal=%u noise=%u\n",
0162                 stmp, utmp1, utmp2);
0163         } else {
0164             stmp = 0;
0165         }
0166 
0167         c->cnr.stat[0].svalue = stmp;
0168         c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
0169     } else {
0170         c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0171     }
0172 
0173     /* PER */
0174     if (*status & FE_HAS_SYNC) {
0175         ret = regmap_bulk_read(dev->regmap[0], 0xe1, buf, 4);
0176         if (ret)
0177             goto err;
0178 
0179         utmp1 = buf[0] << 8 | buf[1] << 0;
0180         utmp2 = buf[2] << 8 | buf[3] << 0;
0181         dev_dbg(&client->dev, "block_error=%u block_count=%u\n",
0182             utmp1, utmp2);
0183 
0184         c->block_error.stat[0].scale = FE_SCALE_COUNTER;
0185         c->block_error.stat[0].uvalue += utmp1;
0186         c->block_count.stat[0].scale = FE_SCALE_COUNTER;
0187         c->block_count.stat[0].uvalue += utmp2;
0188     } else {
0189         c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0190         c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0191     }
0192 
0193     return 0;
0194 err:
0195     dev_dbg(&client->dev, "failed=%d\n", ret);
0196     return ret;
0197 }
0198 
0199 static int mn88472_set_frontend(struct dvb_frontend *fe)
0200 {
0201     struct i2c_client *client = fe->demodulator_priv;
0202     struct mn88472_dev *dev = i2c_get_clientdata(client);
0203     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0204     int ret, i;
0205     unsigned int utmp;
0206     u32 if_frequency;
0207     u8 buf[3], delivery_system_val, bandwidth_val, *bandwidth_vals_ptr;
0208     u8 reg_bank0_b4_val, reg_bank0_cd_val, reg_bank0_d4_val;
0209     u8 reg_bank0_d6_val;
0210 
0211     dev_dbg(&client->dev,
0212         "delivery_system=%u modulation=%u frequency=%u bandwidth_hz=%u symbol_rate=%u inversion=%d stream_id=%d\n",
0213         c->delivery_system, c->modulation, c->frequency,
0214         c->bandwidth_hz, c->symbol_rate, c->inversion, c->stream_id);
0215 
0216     if (!dev->active) {
0217         ret = -EAGAIN;
0218         goto err;
0219     }
0220 
0221     switch (c->delivery_system) {
0222     case SYS_DVBT:
0223         delivery_system_val = 0x02;
0224         reg_bank0_b4_val = 0x00;
0225         reg_bank0_cd_val = 0x1f;
0226         reg_bank0_d4_val = 0x0a;
0227         reg_bank0_d6_val = 0x48;
0228         break;
0229     case SYS_DVBT2:
0230         delivery_system_val = 0x03;
0231         reg_bank0_b4_val = 0xf6;
0232         reg_bank0_cd_val = 0x01;
0233         reg_bank0_d4_val = 0x09;
0234         reg_bank0_d6_val = 0x46;
0235         break;
0236     case SYS_DVBC_ANNEX_A:
0237         delivery_system_val = 0x04;
0238         reg_bank0_b4_val = 0x00;
0239         reg_bank0_cd_val = 0x17;
0240         reg_bank0_d4_val = 0x09;
0241         reg_bank0_d6_val = 0x48;
0242         break;
0243     default:
0244         ret = -EINVAL;
0245         goto err;
0246     }
0247 
0248     switch (c->delivery_system) {
0249     case SYS_DVBT:
0250     case SYS_DVBT2:
0251         switch (c->bandwidth_hz) {
0252         case 5000000:
0253             bandwidth_vals_ptr = "\xe5\x99\x9a\x1b\xa9\x1b\xa9";
0254             bandwidth_val = 0x03;
0255             break;
0256         case 6000000:
0257             bandwidth_vals_ptr = "\xbf\x55\x55\x15\x6b\x15\x6b";
0258             bandwidth_val = 0x02;
0259             break;
0260         case 7000000:
0261             bandwidth_vals_ptr = "\xa4\x00\x00\x0f\x2c\x0f\x2c";
0262             bandwidth_val = 0x01;
0263             break;
0264         case 8000000:
0265             bandwidth_vals_ptr = "\x8f\x80\x00\x08\xee\x08\xee";
0266             bandwidth_val = 0x00;
0267             break;
0268         default:
0269             ret = -EINVAL;
0270             goto err;
0271         }
0272         break;
0273     case SYS_DVBC_ANNEX_A:
0274         bandwidth_vals_ptr = NULL;
0275         bandwidth_val = 0x00;
0276         break;
0277     default:
0278         break;
0279     }
0280 
0281     /* Program tuner */
0282     if (fe->ops.tuner_ops.set_params) {
0283         ret = fe->ops.tuner_ops.set_params(fe);
0284         if (ret)
0285             goto err;
0286     }
0287 
0288     if (fe->ops.tuner_ops.get_if_frequency) {
0289         ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
0290         if (ret)
0291             goto err;
0292 
0293         dev_dbg(&client->dev, "get_if_frequency=%d\n", if_frequency);
0294     } else {
0295         ret = -EINVAL;
0296         goto err;
0297     }
0298 
0299     ret = regmap_write(dev->regmap[2], 0x00, 0x66);
0300     if (ret)
0301         goto err;
0302     ret = regmap_write(dev->regmap[2], 0x01, 0x00);
0303     if (ret)
0304         goto err;
0305     ret = regmap_write(dev->regmap[2], 0x02, 0x01);
0306     if (ret)
0307         goto err;
0308     ret = regmap_write(dev->regmap[2], 0x03, delivery_system_val);
0309     if (ret)
0310         goto err;
0311     ret = regmap_write(dev->regmap[2], 0x04, bandwidth_val);
0312     if (ret)
0313         goto err;
0314 
0315     /* IF */
0316     utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, dev->clk);
0317     buf[0] = (utmp >> 16) & 0xff;
0318     buf[1] = (utmp >>  8) & 0xff;
0319     buf[2] = (utmp >>  0) & 0xff;
0320     for (i = 0; i < 3; i++) {
0321         ret = regmap_write(dev->regmap[2], 0x10 + i, buf[i]);
0322         if (ret)
0323             goto err;
0324     }
0325 
0326     /* Bandwidth */
0327     if (bandwidth_vals_ptr) {
0328         for (i = 0; i < 7; i++) {
0329             ret = regmap_write(dev->regmap[2], 0x13 + i,
0330                        bandwidth_vals_ptr[i]);
0331             if (ret)
0332                 goto err;
0333         }
0334     }
0335 
0336     ret = regmap_write(dev->regmap[0], 0xb4, reg_bank0_b4_val);
0337     if (ret)
0338         goto err;
0339     ret = regmap_write(dev->regmap[0], 0xcd, reg_bank0_cd_val);
0340     if (ret)
0341         goto err;
0342     ret = regmap_write(dev->regmap[0], 0xd4, reg_bank0_d4_val);
0343     if (ret)
0344         goto err;
0345     ret = regmap_write(dev->regmap[0], 0xd6, reg_bank0_d6_val);
0346     if (ret)
0347         goto err;
0348 
0349     switch (c->delivery_system) {
0350     case SYS_DVBT:
0351         ret = regmap_write(dev->regmap[0], 0x07, 0x26);
0352         if (ret)
0353             goto err;
0354         ret = regmap_write(dev->regmap[0], 0x00, 0xba);
0355         if (ret)
0356             goto err;
0357         ret = regmap_write(dev->regmap[0], 0x01, 0x13);
0358         if (ret)
0359             goto err;
0360         break;
0361     case SYS_DVBT2:
0362         ret = regmap_write(dev->regmap[2], 0x2b, 0x13);
0363         if (ret)
0364             goto err;
0365         ret = regmap_write(dev->regmap[2], 0x4f, 0x05);
0366         if (ret)
0367             goto err;
0368         ret = regmap_write(dev->regmap[1], 0xf6, 0x05);
0369         if (ret)
0370             goto err;
0371         ret = regmap_write(dev->regmap[2], 0x32,
0372                 (c->stream_id == NO_STREAM_ID_FILTER) ? 0 :
0373                 c->stream_id );
0374         if (ret)
0375             goto err;
0376         break;
0377     case SYS_DVBC_ANNEX_A:
0378         break;
0379     default:
0380         break;
0381     }
0382 
0383     /* Reset FSM */
0384     ret = regmap_write(dev->regmap[2], 0xf8, 0x9f);
0385     if (ret)
0386         goto err;
0387 
0388     return 0;
0389 err:
0390     dev_dbg(&client->dev, "failed=%d\n", ret);
0391     return ret;
0392 }
0393 
0394 static int mn88472_init(struct dvb_frontend *fe)
0395 {
0396     struct i2c_client *client = fe->demodulator_priv;
0397     struct mn88472_dev *dev = i2c_get_clientdata(client);
0398     int ret, len, rem;
0399     unsigned int utmp;
0400     const struct firmware *firmware;
0401     const char *name = MN88472_FIRMWARE;
0402 
0403     dev_dbg(&client->dev, "\n");
0404 
0405     /* Power up */
0406     ret = regmap_write(dev->regmap[2], 0x05, 0x00);
0407     if (ret)
0408         goto err;
0409     ret = regmap_write(dev->regmap[2], 0x0b, 0x00);
0410     if (ret)
0411         goto err;
0412     ret = regmap_write(dev->regmap[2], 0x0c, 0x00);
0413     if (ret)
0414         goto err;
0415 
0416     /* Check if firmware is already running */
0417     ret = regmap_read(dev->regmap[0], 0xf5, &utmp);
0418     if (ret)
0419         goto err;
0420     if (!(utmp & 0x01))
0421         goto warm;
0422 
0423     ret = request_firmware(&firmware, name, &client->dev);
0424     if (ret) {
0425         dev_err(&client->dev, "firmware file '%s' not found\n", name);
0426         goto err;
0427     }
0428 
0429     dev_info(&client->dev, "downloading firmware from file '%s'\n", name);
0430 
0431     ret = regmap_write(dev->regmap[0], 0xf5, 0x03);
0432     if (ret)
0433         goto err_release_firmware;
0434 
0435     for (rem = firmware->size; rem > 0; rem -= (dev->i2c_write_max - 1)) {
0436         len = min(dev->i2c_write_max - 1, rem);
0437         ret = regmap_bulk_write(dev->regmap[0], 0xf6,
0438                     &firmware->data[firmware->size - rem],
0439                     len);
0440         if (ret) {
0441             dev_err(&client->dev, "firmware download failed %d\n",
0442                 ret);
0443             goto err_release_firmware;
0444         }
0445     }
0446 
0447     /* Parity check of firmware */
0448     ret = regmap_read(dev->regmap[0], 0xf8, &utmp);
0449     if (ret)
0450         goto err_release_firmware;
0451     if (utmp & 0x10) {
0452         ret = -EINVAL;
0453         dev_err(&client->dev, "firmware did not run\n");
0454         goto err_release_firmware;
0455     }
0456 
0457     ret = regmap_write(dev->regmap[0], 0xf5, 0x00);
0458     if (ret)
0459         goto err_release_firmware;
0460 
0461     release_firmware(firmware);
0462 warm:
0463     /* TS config */
0464     switch (dev->ts_mode) {
0465     case SERIAL_TS_MODE:
0466         utmp = 0x1d;
0467         break;
0468     case PARALLEL_TS_MODE:
0469         utmp = 0x00;
0470         break;
0471     default:
0472         ret = -EINVAL;
0473         goto err;
0474     }
0475     ret = regmap_write(dev->regmap[2], 0x08, utmp);
0476     if (ret)
0477         goto err;
0478 
0479     switch (dev->ts_clk) {
0480     case VARIABLE_TS_CLOCK:
0481         utmp = 0xe3;
0482         break;
0483     case FIXED_TS_CLOCK:
0484         utmp = 0xe1;
0485         break;
0486     default:
0487         ret = -EINVAL;
0488         goto err;
0489     }
0490     ret = regmap_write(dev->regmap[0], 0xd9, utmp);
0491     if (ret)
0492         goto err;
0493 
0494     dev->active = true;
0495 
0496     return 0;
0497 err_release_firmware:
0498     release_firmware(firmware);
0499 err:
0500     dev_dbg(&client->dev, "failed=%d\n", ret);
0501     return ret;
0502 }
0503 
0504 static int mn88472_sleep(struct dvb_frontend *fe)
0505 {
0506     struct i2c_client *client = fe->demodulator_priv;
0507     struct mn88472_dev *dev = i2c_get_clientdata(client);
0508     int ret;
0509 
0510     dev_dbg(&client->dev, "\n");
0511 
0512     /* Power down */
0513     ret = regmap_write(dev->regmap[2], 0x0c, 0x30);
0514     if (ret)
0515         goto err;
0516     ret = regmap_write(dev->regmap[2], 0x0b, 0x30);
0517     if (ret)
0518         goto err;
0519     ret = regmap_write(dev->regmap[2], 0x05, 0x3e);
0520     if (ret)
0521         goto err;
0522 
0523     return 0;
0524 err:
0525     dev_dbg(&client->dev, "failed=%d\n", ret);
0526     return ret;
0527 }
0528 
0529 static const struct dvb_frontend_ops mn88472_ops = {
0530     .delsys = {SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A},
0531     .info = {
0532         .name = "Panasonic MN88472",
0533         .symbol_rate_min = 1000000,
0534         .symbol_rate_max = 7200000,
0535         .caps = FE_CAN_FEC_1_2                 |
0536             FE_CAN_FEC_2_3                 |
0537             FE_CAN_FEC_3_4                 |
0538             FE_CAN_FEC_5_6                 |
0539             FE_CAN_FEC_7_8                 |
0540             FE_CAN_FEC_AUTO                |
0541             FE_CAN_QPSK                    |
0542             FE_CAN_QAM_16                  |
0543             FE_CAN_QAM_32                  |
0544             FE_CAN_QAM_64                  |
0545             FE_CAN_QAM_128                 |
0546             FE_CAN_QAM_256                 |
0547             FE_CAN_QAM_AUTO                |
0548             FE_CAN_TRANSMISSION_MODE_AUTO  |
0549             FE_CAN_GUARD_INTERVAL_AUTO     |
0550             FE_CAN_HIERARCHY_AUTO          |
0551             FE_CAN_MUTE_TS                 |
0552             FE_CAN_2G_MODULATION           |
0553             FE_CAN_MULTISTREAM
0554     },
0555 
0556     .get_tune_settings = mn88472_get_tune_settings,
0557 
0558     .init = mn88472_init,
0559     .sleep = mn88472_sleep,
0560 
0561     .set_frontend = mn88472_set_frontend,
0562 
0563     .read_status = mn88472_read_status,
0564 };
0565 
0566 static struct dvb_frontend *mn88472_get_dvb_frontend(struct i2c_client *client)
0567 {
0568     struct mn88472_dev *dev = i2c_get_clientdata(client);
0569 
0570     dev_dbg(&client->dev, "\n");
0571 
0572     return &dev->fe;
0573 }
0574 
0575 static int mn88472_probe(struct i2c_client *client,
0576              const struct i2c_device_id *id)
0577 {
0578     struct mn88472_config *pdata = client->dev.platform_data;
0579     struct mn88472_dev *dev;
0580     struct dtv_frontend_properties *c;
0581     int ret;
0582     unsigned int utmp;
0583     static const struct regmap_config regmap_config = {
0584         .reg_bits = 8,
0585         .val_bits = 8,
0586     };
0587 
0588     dev_dbg(&client->dev, "\n");
0589 
0590     dev = kzalloc(sizeof(*dev), GFP_KERNEL);
0591     if (!dev) {
0592         ret = -ENOMEM;
0593         goto err;
0594     }
0595 
0596     dev->i2c_write_max = pdata->i2c_wr_max ? pdata->i2c_wr_max : ~0;
0597     dev->clk = pdata->xtal;
0598     dev->ts_mode = pdata->ts_mode;
0599     dev->ts_clk = pdata->ts_clock;
0600     dev->client[0] = client;
0601     dev->regmap[0] = regmap_init_i2c(dev->client[0], &regmap_config);
0602     if (IS_ERR(dev->regmap[0])) {
0603         ret = PTR_ERR(dev->regmap[0]);
0604         goto err_kfree;
0605     }
0606 
0607     /*
0608      * Chip has three I2C addresses for different register banks. Used
0609      * addresses are 0x18, 0x1a and 0x1c. We register two dummy clients,
0610      * 0x1a and 0x1c, in order to get own I2C client for each register bank.
0611      *
0612      * Also, register bank 2 do not support sequential I/O. Only single
0613      * register write or read is allowed to that bank.
0614      */
0615     dev->client[1] = i2c_new_dummy_device(client->adapter, 0x1a);
0616     if (IS_ERR(dev->client[1])) {
0617         ret = PTR_ERR(dev->client[1]);
0618         dev_err(&client->dev, "I2C registration failed\n");
0619         goto err_regmap_0_regmap_exit;
0620     }
0621     dev->regmap[1] = regmap_init_i2c(dev->client[1], &regmap_config);
0622     if (IS_ERR(dev->regmap[1])) {
0623         ret = PTR_ERR(dev->regmap[1]);
0624         goto err_client_1_i2c_unregister_device;
0625     }
0626     i2c_set_clientdata(dev->client[1], dev);
0627 
0628     dev->client[2] = i2c_new_dummy_device(client->adapter, 0x1c);
0629     if (IS_ERR(dev->client[2])) {
0630         ret = PTR_ERR(dev->client[2]);
0631         dev_err(&client->dev, "2nd I2C registration failed\n");
0632         goto err_regmap_1_regmap_exit;
0633     }
0634     dev->regmap[2] = regmap_init_i2c(dev->client[2], &regmap_config);
0635     if (IS_ERR(dev->regmap[2])) {
0636         ret = PTR_ERR(dev->regmap[2]);
0637         goto err_client_2_i2c_unregister_device;
0638     }
0639     i2c_set_clientdata(dev->client[2], dev);
0640 
0641     /* Check demod answers with correct chip id */
0642     ret = regmap_read(dev->regmap[2], 0xff, &utmp);
0643     if (ret)
0644         goto err_regmap_2_regmap_exit;
0645 
0646     dev_dbg(&client->dev, "chip id=%02x\n", utmp);
0647 
0648     if (utmp != 0x02) {
0649         ret = -ENODEV;
0650         goto err_regmap_2_regmap_exit;
0651     }
0652 
0653     /* Sleep because chip is active by default */
0654     ret = regmap_write(dev->regmap[2], 0x05, 0x3e);
0655     if (ret)
0656         goto err_regmap_2_regmap_exit;
0657 
0658     /* Create dvb frontend */
0659     memcpy(&dev->fe.ops, &mn88472_ops, sizeof(struct dvb_frontend_ops));
0660     dev->fe.demodulator_priv = client;
0661     *pdata->fe = &dev->fe;
0662     i2c_set_clientdata(client, dev);
0663 
0664     /* Init stats to indicate which stats are supported */
0665     c = &dev->fe.dtv_property_cache;
0666     c->strength.len = 1;
0667     c->cnr.len = 1;
0668     c->block_error.len = 1;
0669     c->block_count.len = 1;
0670 
0671     /* Setup callbacks */
0672     pdata->get_dvb_frontend = mn88472_get_dvb_frontend;
0673 
0674     dev_info(&client->dev, "Panasonic MN88472 successfully identified\n");
0675 
0676     return 0;
0677 err_regmap_2_regmap_exit:
0678     regmap_exit(dev->regmap[2]);
0679 err_client_2_i2c_unregister_device:
0680     i2c_unregister_device(dev->client[2]);
0681 err_regmap_1_regmap_exit:
0682     regmap_exit(dev->regmap[1]);
0683 err_client_1_i2c_unregister_device:
0684     i2c_unregister_device(dev->client[1]);
0685 err_regmap_0_regmap_exit:
0686     regmap_exit(dev->regmap[0]);
0687 err_kfree:
0688     kfree(dev);
0689 err:
0690     dev_dbg(&client->dev, "failed=%d\n", ret);
0691     return ret;
0692 }
0693 
0694 static int mn88472_remove(struct i2c_client *client)
0695 {
0696     struct mn88472_dev *dev = i2c_get_clientdata(client);
0697 
0698     dev_dbg(&client->dev, "\n");
0699 
0700     regmap_exit(dev->regmap[2]);
0701     i2c_unregister_device(dev->client[2]);
0702 
0703     regmap_exit(dev->regmap[1]);
0704     i2c_unregister_device(dev->client[1]);
0705 
0706     regmap_exit(dev->regmap[0]);
0707 
0708     kfree(dev);
0709 
0710     return 0;
0711 }
0712 
0713 static const struct i2c_device_id mn88472_id_table[] = {
0714     {"mn88472", 0},
0715     {}
0716 };
0717 MODULE_DEVICE_TABLE(i2c, mn88472_id_table);
0718 
0719 static struct i2c_driver mn88472_driver = {
0720     .driver = {
0721         .name = "mn88472",
0722         .suppress_bind_attrs = true,
0723     },
0724     .probe    = mn88472_probe,
0725     .remove   = mn88472_remove,
0726     .id_table = mn88472_id_table,
0727 };
0728 
0729 module_i2c_driver(mn88472_driver);
0730 
0731 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
0732 MODULE_DESCRIPTION("Panasonic MN88472 DVB-T/T2/C demodulator driver");
0733 MODULE_LICENSE("GPL");
0734 MODULE_FIRMWARE(MN88472_FIRMWARE);
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