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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Socionext MN88443x series demodulator driver for ISDB-S/ISDB-T.
0004 //
0005 // Copyright (c) 2018 Socionext Inc.
0006 
0007 #include <linux/bitfield.h>
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/gpio/consumer.h>
0011 #include <linux/of_device.h>
0012 #include <linux/regmap.h>
0013 #include <media/dvb_math.h>
0014 
0015 #include "mn88443x.h"
0016 
0017 /* ISDB-S registers */
0018 #define ATSIDU_S                                    0x2f
0019 #define ATSIDL_S                                    0x30
0020 #define TSSET_S                                     0x31
0021 #define AGCREAD_S                                   0x5a
0022 #define CPMON1_S                                    0x5e
0023 #define   CPMON1_S_FSYNC                              BIT(5)
0024 #define   CPMON1_S_ERRMON                             BIT(4)
0025 #define   CPMON1_S_SIGOFF                             BIT(3)
0026 #define   CPMON1_S_W2LOCK                             BIT(2)
0027 #define   CPMON1_S_W1LOCK                             BIT(1)
0028 #define   CPMON1_S_DW1LOCK                            BIT(0)
0029 #define TRMON_S                                     0x60
0030 #define BERCNFLG_S                                  0x68
0031 #define   BERCNFLG_S_BERVRDY                          BIT(5)
0032 #define   BERCNFLG_S_BERVCHK                          BIT(4)
0033 #define   BERCNFLG_S_BERDRDY                          BIT(3)
0034 #define   BERCNFLG_S_BERDCHK                          BIT(2)
0035 #define CNRDXU_S                                    0x69
0036 #define CNRDXL_S                                    0x6a
0037 #define CNRDYU_S                                    0x6b
0038 #define CNRDYL_S                                    0x6c
0039 #define BERVRDU_S                                   0x71
0040 #define BERVRDL_S                                   0x72
0041 #define DOSET1_S                                    0x73
0042 
0043 /* Primary ISDB-T */
0044 #define PLLASET1                                    0x00
0045 #define PLLASET2                                    0x01
0046 #define PLLBSET1                                    0x02
0047 #define PLLBSET2                                    0x03
0048 #define PLLSET                                      0x04
0049 #define OUTCSET                                     0x08
0050 #define   OUTCSET_CHDRV_8MA                           0xff
0051 #define   OUTCSET_CHDRV_4MA                           0x00
0052 #define PLDWSET                                     0x09
0053 #define   PLDWSET_NORMAL                             0x00
0054 #define   PLDWSET_PULLDOWN                           0xff
0055 #define HIZSET1                                     0x0a
0056 #define HIZSET2                                     0x0b
0057 
0058 /* Secondary ISDB-T (for MN884434 only) */
0059 #define RCVSET                                      0x00
0060 #define TSSET1_M                                    0x01
0061 #define TSSET2_M                                    0x02
0062 #define TSSET3_M                                    0x03
0063 #define INTACSET                                    0x08
0064 #define HIZSET3                                     0x0b
0065 
0066 /* ISDB-T registers */
0067 #define TSSET1                                      0x05
0068 #define   TSSET1_TSASEL_MASK                          GENMASK(4, 3)
0069 #define   TSSET1_TSASEL_ISDBT                         (0x0 << 3)
0070 #define   TSSET1_TSASEL_ISDBS                         (0x1 << 3)
0071 #define   TSSET1_TSASEL_NONE                          (0x2 << 3)
0072 #define   TSSET1_TSBSEL_MASK                          GENMASK(2, 1)
0073 #define   TSSET1_TSBSEL_ISDBS                         (0x0 << 1)
0074 #define   TSSET1_TSBSEL_ISDBT                         (0x1 << 1)
0075 #define   TSSET1_TSBSEL_NONE                          (0x2 << 1)
0076 #define TSSET2                                      0x06
0077 #define TSSET3                                      0x07
0078 #define   TSSET3_INTASEL_MASK                         GENMASK(7, 6)
0079 #define   TSSET3_INTASEL_T                            (0x0 << 6)
0080 #define   TSSET3_INTASEL_S                            (0x1 << 6)
0081 #define   TSSET3_INTASEL_NONE                         (0x2 << 6)
0082 #define   TSSET3_INTBSEL_MASK                         GENMASK(5, 4)
0083 #define   TSSET3_INTBSEL_S                            (0x0 << 4)
0084 #define   TSSET3_INTBSEL_T                            (0x1 << 4)
0085 #define   TSSET3_INTBSEL_NONE                         (0x2 << 4)
0086 #define OUTSET2                                     0x0d
0087 #define PWDSET                                      0x0f
0088 #define   PWDSET_OFDMPD_MASK                          GENMASK(3, 2)
0089 #define   PWDSET_OFDMPD_DOWN                          BIT(3)
0090 #define   PWDSET_PSKPD_MASK                           GENMASK(1, 0)
0091 #define   PWDSET_PSKPD_DOWN                           BIT(1)
0092 #define CLKSET1_T                                   0x11
0093 #define MDSET_T                                     0x13
0094 #define   MDSET_T_MDAUTO_MASK                         GENMASK(7, 4)
0095 #define   MDSET_T_MDAUTO_AUTO                         (0xf << 4)
0096 #define   MDSET_T_MDAUTO_MANUAL                       (0x0 << 4)
0097 #define   MDSET_T_FFTS_MASK                           GENMASK(3, 2)
0098 #define   MDSET_T_FFTS_MODE1                          (0x0 << 2)
0099 #define   MDSET_T_FFTS_MODE2                          (0x1 << 2)
0100 #define   MDSET_T_FFTS_MODE3                          (0x2 << 2)
0101 #define   MDSET_T_GI_MASK                             GENMASK(1, 0)
0102 #define   MDSET_T_GI_1_32                             (0x0 << 0)
0103 #define   MDSET_T_GI_1_16                             (0x1 << 0)
0104 #define   MDSET_T_GI_1_8                              (0x2 << 0)
0105 #define   MDSET_T_GI_1_4                              (0x3 << 0)
0106 #define MDASET_T                                    0x14
0107 #define ADCSET1_T                                   0x20
0108 #define   ADCSET1_T_REFSEL_MASK                       GENMASK(1, 0)
0109 #define   ADCSET1_T_REFSEL_2V                         (0x3 << 0)
0110 #define   ADCSET1_T_REFSEL_1_5V                       (0x2 << 0)
0111 #define   ADCSET1_T_REFSEL_1V                         (0x1 << 0)
0112 #define NCOFREQU_T                                  0x24
0113 #define NCOFREQM_T                                  0x25
0114 #define NCOFREQL_T                                  0x26
0115 #define FADU_T                                      0x27
0116 #define FADM_T                                      0x28
0117 #define FADL_T                                      0x29
0118 #define AGCSET2_T                                   0x2c
0119 #define   AGCSET2_T_IFPOLINV_INC                      BIT(0)
0120 #define   AGCSET2_T_RFPOLINV_INC                      BIT(1)
0121 #define AGCV3_T                                     0x3e
0122 #define MDRD_T                                      0xa2
0123 #define   MDRD_T_SEGID_MASK                           GENMASK(5, 4)
0124 #define   MDRD_T_SEGID_13                             (0x0 << 4)
0125 #define   MDRD_T_SEGID_1                              (0x1 << 4)
0126 #define   MDRD_T_SEGID_3                              (0x2 << 4)
0127 #define   MDRD_T_FFTS_MASK                            GENMASK(3, 2)
0128 #define   MDRD_T_FFTS_MODE1                           (0x0 << 2)
0129 #define   MDRD_T_FFTS_MODE2                           (0x1 << 2)
0130 #define   MDRD_T_FFTS_MODE3                           (0x2 << 2)
0131 #define   MDRD_T_GI_MASK                              GENMASK(1, 0)
0132 #define   MDRD_T_GI_1_32                              (0x0 << 0)
0133 #define   MDRD_T_GI_1_16                              (0x1 << 0)
0134 #define   MDRD_T_GI_1_8                               (0x2 << 0)
0135 #define   MDRD_T_GI_1_4                               (0x3 << 0)
0136 #define SSEQRD_T                                    0xa3
0137 #define   SSEQRD_T_SSEQSTRD_MASK                      GENMASK(3, 0)
0138 #define   SSEQRD_T_SSEQSTRD_RESET                     (0x0 << 0)
0139 #define   SSEQRD_T_SSEQSTRD_TUNING                    (0x1 << 0)
0140 #define   SSEQRD_T_SSEQSTRD_AGC                       (0x2 << 0)
0141 #define   SSEQRD_T_SSEQSTRD_SEARCH                    (0x3 << 0)
0142 #define   SSEQRD_T_SSEQSTRD_CLOCK_SYNC                (0x4 << 0)
0143 #define   SSEQRD_T_SSEQSTRD_FREQ_SYNC                 (0x8 << 0)
0144 #define   SSEQRD_T_SSEQSTRD_FRAME_SYNC                (0x9 << 0)
0145 #define   SSEQRD_T_SSEQSTRD_SYNC                      (0xa << 0)
0146 #define   SSEQRD_T_SSEQSTRD_LOCK                      (0xb << 0)
0147 #define AGCRDU_T                                    0xa8
0148 #define AGCRDL_T                                    0xa9
0149 #define CNRDU_T                                     0xbe
0150 #define CNRDL_T                                     0xbf
0151 #define BERFLG_T                                    0xc0
0152 #define   BERFLG_T_BERDRDY                            BIT(7)
0153 #define   BERFLG_T_BERDCHK                            BIT(6)
0154 #define   BERFLG_T_BERVRDYA                           BIT(5)
0155 #define   BERFLG_T_BERVCHKA                           BIT(4)
0156 #define   BERFLG_T_BERVRDYB                           BIT(3)
0157 #define   BERFLG_T_BERVCHKB                           BIT(2)
0158 #define   BERFLG_T_BERVRDYC                           BIT(1)
0159 #define   BERFLG_T_BERVCHKC                           BIT(0)
0160 #define BERRDU_T                                    0xc1
0161 #define BERRDM_T                                    0xc2
0162 #define BERRDL_T                                    0xc3
0163 #define BERLENRDU_T                                 0xc4
0164 #define BERLENRDL_T                                 0xc5
0165 #define ERRFLG_T                                    0xc6
0166 #define   ERRFLG_T_BERDOVF                            BIT(7)
0167 #define   ERRFLG_T_BERVOVFA                           BIT(6)
0168 #define   ERRFLG_T_BERVOVFB                           BIT(5)
0169 #define   ERRFLG_T_BERVOVFC                           BIT(4)
0170 #define   ERRFLG_T_NERRFA                             BIT(3)
0171 #define   ERRFLG_T_NERRFB                             BIT(2)
0172 #define   ERRFLG_T_NERRFC                             BIT(1)
0173 #define   ERRFLG_T_NERRF                              BIT(0)
0174 #define DOSET1_T                                    0xcf
0175 
0176 #define CLK_LOW            4000000
0177 #define CLK_DIRECT         20200000
0178 #define CLK_MAX            25410000
0179 
0180 #define S_T_FREQ           8126984 /* 512 / 63 MHz */
0181 
0182 struct mn88443x_spec {
0183     bool primary;
0184 };
0185 
0186 struct mn88443x_priv {
0187     const struct mn88443x_spec *spec;
0188 
0189     struct dvb_frontend fe;
0190     struct clk *mclk;
0191     struct gpio_desc *reset_gpio;
0192     u32 clk_freq;
0193     u32 if_freq;
0194 
0195     /* Common */
0196     bool use_clkbuf;
0197 
0198     /* ISDB-S */
0199     struct i2c_client *client_s;
0200     struct regmap *regmap_s;
0201 
0202     /* ISDB-T */
0203     struct i2c_client *client_t;
0204     struct regmap *regmap_t;
0205 };
0206 
0207 static int mn88443x_cmn_power_on(struct mn88443x_priv *chip)
0208 {
0209     struct device *dev = &chip->client_s->dev;
0210     struct regmap *r_t = chip->regmap_t;
0211     int ret;
0212 
0213     ret = clk_prepare_enable(chip->mclk);
0214     if (ret) {
0215         dev_err(dev, "Failed to prepare and enable mclk: %d\n",
0216             ret);
0217         return ret;
0218     }
0219 
0220     gpiod_set_value_cansleep(chip->reset_gpio, 1);
0221     usleep_range(100, 1000);
0222     gpiod_set_value_cansleep(chip->reset_gpio, 0);
0223 
0224     if (chip->spec->primary) {
0225         regmap_write(r_t, OUTCSET, OUTCSET_CHDRV_8MA);
0226         regmap_write(r_t, PLDWSET, PLDWSET_NORMAL);
0227         regmap_write(r_t, HIZSET1, 0x80);
0228         regmap_write(r_t, HIZSET2, 0xe0);
0229     } else {
0230         regmap_write(r_t, HIZSET3, 0x8f);
0231     }
0232 
0233     return 0;
0234 }
0235 
0236 static void mn88443x_cmn_power_off(struct mn88443x_priv *chip)
0237 {
0238     gpiod_set_value_cansleep(chip->reset_gpio, 1);
0239 
0240     clk_disable_unprepare(chip->mclk);
0241 }
0242 
0243 static void mn88443x_s_sleep(struct mn88443x_priv *chip)
0244 {
0245     struct regmap *r_t = chip->regmap_t;
0246 
0247     regmap_update_bits(r_t, PWDSET, PWDSET_PSKPD_MASK,
0248                PWDSET_PSKPD_DOWN);
0249 }
0250 
0251 static void mn88443x_s_wake(struct mn88443x_priv *chip)
0252 {
0253     struct regmap *r_t = chip->regmap_t;
0254 
0255     regmap_update_bits(r_t, PWDSET, PWDSET_PSKPD_MASK, 0);
0256 }
0257 
0258 static void mn88443x_s_tune(struct mn88443x_priv *chip,
0259                 struct dtv_frontend_properties *c)
0260 {
0261     struct regmap *r_s = chip->regmap_s;
0262 
0263     regmap_write(r_s, ATSIDU_S, c->stream_id >> 8);
0264     regmap_write(r_s, ATSIDL_S, c->stream_id);
0265     regmap_write(r_s, TSSET_S, 0);
0266 }
0267 
0268 static int mn88443x_s_read_status(struct mn88443x_priv *chip,
0269                   struct dtv_frontend_properties *c,
0270                   enum fe_status *status)
0271 {
0272     struct regmap *r_s = chip->regmap_s;
0273     u32 cpmon, tmpu, tmpl, flg;
0274     u64 tmp;
0275 
0276     /* Sync detection */
0277     regmap_read(r_s, CPMON1_S, &cpmon);
0278 
0279     *status = 0;
0280     if (cpmon & CPMON1_S_FSYNC)
0281         *status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
0282     if (cpmon & CPMON1_S_W2LOCK)
0283         *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
0284 
0285     /* Signal strength */
0286     c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0287 
0288     if (*status & FE_HAS_SIGNAL) {
0289         u32 agc;
0290 
0291         regmap_read(r_s, AGCREAD_S, &tmpu);
0292         agc = tmpu << 8;
0293 
0294         c->strength.len = 1;
0295         c->strength.stat[0].scale = FE_SCALE_RELATIVE;
0296         c->strength.stat[0].uvalue = agc;
0297     }
0298 
0299     /* C/N rate */
0300     c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0301 
0302     if (*status & FE_HAS_VITERBI) {
0303         u32 cnr = 0, x, y, d;
0304         u64 d_3 = 0;
0305 
0306         regmap_read(r_s, CNRDXU_S, &tmpu);
0307         regmap_read(r_s, CNRDXL_S, &tmpl);
0308         x = (tmpu << 8) | tmpl;
0309         regmap_read(r_s, CNRDYU_S, &tmpu);
0310         regmap_read(r_s, CNRDYL_S, &tmpl);
0311         y = (tmpu << 8) | tmpl;
0312 
0313         /* CNR[dB]: 10 * log10(D) - 30.74 / D^3 - 3 */
0314         /*   D = x^2 / (2^15 * y - x^2) */
0315         d = (y << 15) - x * x;
0316         if (d > 0) {
0317             /* (2^4 * D)^3 = 2^12 * D^3 */
0318             /* 3.074 * 2^(12 + 24) = 211243671486 */
0319             d_3 = div_u64(16 * x * x, d);
0320             d_3 = d_3 * d_3 * d_3;
0321             if (d_3)
0322                 d_3 = div_u64(211243671486ULL, d_3);
0323         }
0324 
0325         if (d_3) {
0326             /* 0.3 * 2^24 = 5033164 */
0327             tmp = (s64)2 * intlog10(x) - intlog10(abs(d)) - d_3
0328                 - 5033164;
0329             cnr = div_u64(tmp * 10000, 1 << 24);
0330         }
0331 
0332         if (cnr) {
0333             c->cnr.len = 1;
0334             c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
0335             c->cnr.stat[0].uvalue = cnr;
0336         }
0337     }
0338 
0339     /* BER */
0340     c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0341     c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0342 
0343     regmap_read(r_s, BERCNFLG_S, &flg);
0344 
0345     if ((*status & FE_HAS_VITERBI) && (flg & BERCNFLG_S_BERVRDY)) {
0346         u32 bit_err, bit_cnt;
0347 
0348         regmap_read(r_s, BERVRDU_S, &tmpu);
0349         regmap_read(r_s, BERVRDL_S, &tmpl);
0350         bit_err = (tmpu << 8) | tmpl;
0351         bit_cnt = (1 << 13) * 204;
0352 
0353         if (bit_cnt) {
0354             c->post_bit_error.len = 1;
0355             c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
0356             c->post_bit_error.stat[0].uvalue = bit_err;
0357             c->post_bit_count.len = 1;
0358             c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
0359             c->post_bit_count.stat[0].uvalue = bit_cnt;
0360         }
0361     }
0362 
0363     return 0;
0364 }
0365 
0366 static void mn88443x_t_sleep(struct mn88443x_priv *chip)
0367 {
0368     struct regmap *r_t = chip->regmap_t;
0369 
0370     regmap_update_bits(r_t, PWDSET, PWDSET_OFDMPD_MASK,
0371                PWDSET_OFDMPD_DOWN);
0372 }
0373 
0374 static void mn88443x_t_wake(struct mn88443x_priv *chip)
0375 {
0376     struct regmap *r_t = chip->regmap_t;
0377 
0378     regmap_update_bits(r_t, PWDSET, PWDSET_OFDMPD_MASK, 0);
0379 }
0380 
0381 static bool mn88443x_t_is_valid_clk(u32 adckt, u32 if_freq)
0382 {
0383     if (if_freq == DIRECT_IF_57MHZ) {
0384         if (adckt >= CLK_DIRECT && adckt <= 21000000)
0385             return true;
0386         if (adckt >= 25300000 && adckt <= CLK_MAX)
0387             return true;
0388     } else if (if_freq == DIRECT_IF_44MHZ) {
0389         if (adckt >= 25000000 && adckt <= CLK_MAX)
0390             return true;
0391     } else if (if_freq >= LOW_IF_4MHZ && if_freq < DIRECT_IF_44MHZ) {
0392         if (adckt >= CLK_DIRECT && adckt <= CLK_MAX)
0393             return true;
0394     }
0395 
0396     return false;
0397 }
0398 
0399 static int mn88443x_t_set_freq(struct mn88443x_priv *chip)
0400 {
0401     struct device *dev = &chip->client_s->dev;
0402     struct regmap *r_t = chip->regmap_t;
0403     s64 adckt, nco, ad_t;
0404     u32 m, v;
0405 
0406     /* Clock buffer (but not supported) or XTAL */
0407     if (chip->clk_freq >= CLK_LOW && chip->clk_freq < CLK_DIRECT) {
0408         chip->use_clkbuf = true;
0409         regmap_write(r_t, CLKSET1_T, 0x07);
0410 
0411         adckt = 0;
0412     } else {
0413         chip->use_clkbuf = false;
0414         regmap_write(r_t, CLKSET1_T, 0x00);
0415 
0416         adckt = chip->clk_freq;
0417     }
0418     if (!mn88443x_t_is_valid_clk(adckt, chip->if_freq)) {
0419         dev_err(dev, "Invalid clock, CLK:%d, ADCKT:%lld, IF:%d\n",
0420             chip->clk_freq, adckt, chip->if_freq);
0421         return -EINVAL;
0422     }
0423 
0424     /* Direct IF or Low IF */
0425     if (chip->if_freq == DIRECT_IF_57MHZ ||
0426         chip->if_freq == DIRECT_IF_44MHZ)
0427         nco = adckt * 2 - chip->if_freq;
0428     else
0429         nco = -((s64)chip->if_freq);
0430     nco = div_s64(nco << 24, adckt);
0431     ad_t = div_s64(adckt << 22, S_T_FREQ);
0432 
0433     regmap_write(r_t, NCOFREQU_T, nco >> 16);
0434     regmap_write(r_t, NCOFREQM_T, nco >> 8);
0435     regmap_write(r_t, NCOFREQL_T, nco);
0436     regmap_write(r_t, FADU_T, ad_t >> 16);
0437     regmap_write(r_t, FADM_T, ad_t >> 8);
0438     regmap_write(r_t, FADL_T, ad_t);
0439 
0440     /* Level of IF */
0441     m = ADCSET1_T_REFSEL_MASK;
0442     v = ADCSET1_T_REFSEL_1_5V;
0443     regmap_update_bits(r_t, ADCSET1_T, m, v);
0444 
0445     /* Polarity of AGC */
0446     v = AGCSET2_T_IFPOLINV_INC | AGCSET2_T_RFPOLINV_INC;
0447     regmap_update_bits(r_t, AGCSET2_T, v, v);
0448 
0449     /* Lower output level of AGC */
0450     regmap_write(r_t, AGCV3_T, 0x00);
0451 
0452     regmap_write(r_t, MDSET_T, 0xfa);
0453 
0454     return 0;
0455 }
0456 
0457 static void mn88443x_t_tune(struct mn88443x_priv *chip,
0458                 struct dtv_frontend_properties *c)
0459 {
0460     struct regmap *r_t = chip->regmap_t;
0461     u32 m, v;
0462 
0463     m = MDSET_T_MDAUTO_MASK | MDSET_T_FFTS_MASK | MDSET_T_GI_MASK;
0464     v = MDSET_T_MDAUTO_AUTO | MDSET_T_FFTS_MODE3 | MDSET_T_GI_1_8;
0465     regmap_update_bits(r_t, MDSET_T, m, v);
0466 
0467     regmap_write(r_t, MDASET_T, 0);
0468 }
0469 
0470 static int mn88443x_t_read_status(struct mn88443x_priv *chip,
0471                   struct dtv_frontend_properties *c,
0472                   enum fe_status *status)
0473 {
0474     struct regmap *r_t = chip->regmap_t;
0475     u32 seqrd, st, flg, tmpu, tmpm, tmpl;
0476     u64 tmp;
0477 
0478     /* Sync detection */
0479     regmap_read(r_t, SSEQRD_T, &seqrd);
0480     st = seqrd & SSEQRD_T_SSEQSTRD_MASK;
0481 
0482     *status = 0;
0483     if (st >= SSEQRD_T_SSEQSTRD_SYNC)
0484         *status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
0485     if (st >= SSEQRD_T_SSEQSTRD_FRAME_SYNC)
0486         *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
0487 
0488     /* Signal strength */
0489     c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0490 
0491     if (*status & FE_HAS_SIGNAL) {
0492         u32 agc;
0493 
0494         regmap_read(r_t, AGCRDU_T, &tmpu);
0495         regmap_read(r_t, AGCRDL_T, &tmpl);
0496         agc = (tmpu << 8) | tmpl;
0497 
0498         c->strength.len = 1;
0499         c->strength.stat[0].scale = FE_SCALE_RELATIVE;
0500         c->strength.stat[0].uvalue = agc;
0501     }
0502 
0503     /* C/N rate */
0504     c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0505 
0506     if (*status & FE_HAS_VITERBI) {
0507         u32 cnr;
0508 
0509         regmap_read(r_t, CNRDU_T, &tmpu);
0510         regmap_read(r_t, CNRDL_T, &tmpl);
0511 
0512         if (tmpu || tmpl) {
0513             /* CNR[dB]: 10 * (log10(65536 / value) + 0.2) */
0514             /* intlog10(65536) = 80807124, 0.2 * 2^24 = 3355443 */
0515             tmp = (u64)80807124 - intlog10((tmpu << 8) | tmpl)
0516                 + 3355443;
0517             cnr = div_u64(tmp * 10000, 1 << 24);
0518         } else {
0519             cnr = 0;
0520         }
0521 
0522         c->cnr.len = 1;
0523         c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
0524         c->cnr.stat[0].uvalue = cnr;
0525     }
0526 
0527     /* BER */
0528     c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0529     c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0530 
0531     regmap_read(r_t, BERFLG_T, &flg);
0532 
0533     if ((*status & FE_HAS_VITERBI) && (flg & BERFLG_T_BERVRDYA)) {
0534         u32 bit_err, bit_cnt;
0535 
0536         regmap_read(r_t, BERRDU_T, &tmpu);
0537         regmap_read(r_t, BERRDM_T, &tmpm);
0538         regmap_read(r_t, BERRDL_T, &tmpl);
0539         bit_err = (tmpu << 16) | (tmpm << 8) | tmpl;
0540 
0541         regmap_read(r_t, BERLENRDU_T, &tmpu);
0542         regmap_read(r_t, BERLENRDL_T, &tmpl);
0543         bit_cnt = ((tmpu << 8) | tmpl) * 203 * 8;
0544 
0545         if (bit_cnt) {
0546             c->post_bit_error.len = 1;
0547             c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
0548             c->post_bit_error.stat[0].uvalue = bit_err;
0549             c->post_bit_count.len = 1;
0550             c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
0551             c->post_bit_count.stat[0].uvalue = bit_cnt;
0552         }
0553     }
0554 
0555     return 0;
0556 }
0557 
0558 static int mn88443x_sleep(struct dvb_frontend *fe)
0559 {
0560     struct mn88443x_priv *chip = fe->demodulator_priv;
0561 
0562     mn88443x_s_sleep(chip);
0563     mn88443x_t_sleep(chip);
0564 
0565     return 0;
0566 }
0567 
0568 static int mn88443x_set_frontend(struct dvb_frontend *fe)
0569 {
0570     struct mn88443x_priv *chip = fe->demodulator_priv;
0571     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0572     struct regmap *r_s = chip->regmap_s;
0573     struct regmap *r_t = chip->regmap_t;
0574     u8 tssel = 0, intsel = 0;
0575 
0576     if (c->delivery_system == SYS_ISDBS) {
0577         mn88443x_s_wake(chip);
0578         mn88443x_t_sleep(chip);
0579 
0580         tssel = TSSET1_TSASEL_ISDBS;
0581         intsel = TSSET3_INTASEL_S;
0582     } else if (c->delivery_system == SYS_ISDBT) {
0583         mn88443x_s_sleep(chip);
0584         mn88443x_t_wake(chip);
0585 
0586         mn88443x_t_set_freq(chip);
0587 
0588         tssel = TSSET1_TSASEL_ISDBT;
0589         intsel = TSSET3_INTASEL_T;
0590     }
0591 
0592     regmap_update_bits(r_t, TSSET1,
0593                TSSET1_TSASEL_MASK | TSSET1_TSBSEL_MASK,
0594                tssel | TSSET1_TSBSEL_NONE);
0595     regmap_write(r_t, TSSET2, 0);
0596     regmap_update_bits(r_t, TSSET3,
0597                TSSET3_INTASEL_MASK | TSSET3_INTBSEL_MASK,
0598                intsel | TSSET3_INTBSEL_NONE);
0599 
0600     regmap_write(r_t, DOSET1_T, 0x95);
0601     regmap_write(r_s, DOSET1_S, 0x80);
0602 
0603     if (c->delivery_system == SYS_ISDBS)
0604         mn88443x_s_tune(chip, c);
0605     else if (c->delivery_system == SYS_ISDBT)
0606         mn88443x_t_tune(chip, c);
0607 
0608     if (fe->ops.tuner_ops.set_params) {
0609         if (fe->ops.i2c_gate_ctrl)
0610             fe->ops.i2c_gate_ctrl(fe, 1);
0611         fe->ops.tuner_ops.set_params(fe);
0612         if (fe->ops.i2c_gate_ctrl)
0613             fe->ops.i2c_gate_ctrl(fe, 0);
0614     }
0615 
0616     return 0;
0617 }
0618 
0619 static int mn88443x_get_tune_settings(struct dvb_frontend *fe,
0620                       struct dvb_frontend_tune_settings *s)
0621 {
0622     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0623 
0624     s->min_delay_ms = 850;
0625 
0626     if (c->delivery_system == SYS_ISDBS) {
0627         s->max_drift = 30000 * 2 + 1;
0628         s->step_size = 30000;
0629     } else if (c->delivery_system == SYS_ISDBT) {
0630         s->max_drift = 142857 * 2 + 1;
0631         s->step_size = 142857 * 2;
0632     }
0633 
0634     return 0;
0635 }
0636 
0637 static int mn88443x_read_status(struct dvb_frontend *fe, enum fe_status *status)
0638 {
0639     struct mn88443x_priv *chip = fe->demodulator_priv;
0640     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0641 
0642     if (c->delivery_system == SYS_ISDBS)
0643         return mn88443x_s_read_status(chip, c, status);
0644 
0645     if (c->delivery_system == SYS_ISDBT)
0646         return mn88443x_t_read_status(chip, c, status);
0647 
0648     return -EINVAL;
0649 }
0650 
0651 static const struct dvb_frontend_ops mn88443x_ops = {
0652     .delsys = { SYS_ISDBS, SYS_ISDBT },
0653     .info = {
0654         .name = "Socionext MN88443x",
0655         .frequency_min_hz =  470 * MHz,
0656         .frequency_max_hz = 2071 * MHz,
0657         .symbol_rate_min  = 28860000,
0658         .symbol_rate_max  = 28860000,
0659         .caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO |
0660             FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
0661             FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
0662     },
0663 
0664     .sleep                   = mn88443x_sleep,
0665     .set_frontend            = mn88443x_set_frontend,
0666     .get_tune_settings       = mn88443x_get_tune_settings,
0667     .read_status             = mn88443x_read_status,
0668 };
0669 
0670 static const struct regmap_config regmap_config = {
0671     .reg_bits   = 8,
0672     .val_bits   = 8,
0673     .cache_type = REGCACHE_NONE,
0674 };
0675 
0676 static int mn88443x_probe(struct i2c_client *client,
0677               const struct i2c_device_id *id)
0678 {
0679     struct mn88443x_config *conf = client->dev.platform_data;
0680     struct mn88443x_priv *chip;
0681     struct device *dev = &client->dev;
0682     int ret;
0683 
0684     chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
0685     if (!chip)
0686         return -ENOMEM;
0687 
0688     if (dev->of_node)
0689         chip->spec = of_device_get_match_data(dev);
0690     else
0691         chip->spec = (struct mn88443x_spec *)id->driver_data;
0692     if (!chip->spec)
0693         return -EINVAL;
0694 
0695     chip->mclk = devm_clk_get(dev, "mclk");
0696     if (IS_ERR(chip->mclk) && !conf) {
0697         dev_err(dev, "Failed to request mclk: %ld\n",
0698             PTR_ERR(chip->mclk));
0699         return PTR_ERR(chip->mclk);
0700     }
0701 
0702     ret = of_property_read_u32(dev->of_node, "if-frequency",
0703                    &chip->if_freq);
0704     if (ret && !conf) {
0705         dev_err(dev, "Failed to load IF frequency: %d.\n", ret);
0706         return ret;
0707     }
0708 
0709     chip->reset_gpio = devm_gpiod_get_optional(dev, "reset",
0710                            GPIOD_OUT_HIGH);
0711     if (IS_ERR(chip->reset_gpio)) {
0712         dev_err(dev, "Failed to request reset_gpio: %ld\n",
0713             PTR_ERR(chip->reset_gpio));
0714         return PTR_ERR(chip->reset_gpio);
0715     }
0716 
0717     if (conf) {
0718         chip->mclk = conf->mclk;
0719         chip->if_freq = conf->if_freq;
0720         chip->reset_gpio = conf->reset_gpio;
0721 
0722         *conf->fe = &chip->fe;
0723     }
0724 
0725     chip->client_s = client;
0726     chip->regmap_s = devm_regmap_init_i2c(chip->client_s, &regmap_config);
0727     if (IS_ERR(chip->regmap_s))
0728         return PTR_ERR(chip->regmap_s);
0729 
0730     /*
0731      * Chip has two I2C addresses for each satellite/terrestrial system.
0732      * ISDB-T uses address ISDB-S + 4, so we register a dummy client.
0733      */
0734     chip->client_t = i2c_new_dummy_device(client->adapter, client->addr + 4);
0735     if (IS_ERR(chip->client_t))
0736         return PTR_ERR(chip->client_t);
0737 
0738     chip->regmap_t = devm_regmap_init_i2c(chip->client_t, &regmap_config);
0739     if (IS_ERR(chip->regmap_t)) {
0740         ret = PTR_ERR(chip->regmap_t);
0741         goto err_i2c_t;
0742     }
0743 
0744     chip->clk_freq = clk_get_rate(chip->mclk);
0745 
0746     memcpy(&chip->fe.ops, &mn88443x_ops, sizeof(mn88443x_ops));
0747     chip->fe.demodulator_priv = chip;
0748     i2c_set_clientdata(client, chip);
0749 
0750     ret = mn88443x_cmn_power_on(chip);
0751     if (ret)
0752         goto err_i2c_t;
0753 
0754     mn88443x_s_sleep(chip);
0755     mn88443x_t_sleep(chip);
0756 
0757     return 0;
0758 
0759 err_i2c_t:
0760     i2c_unregister_device(chip->client_t);
0761 
0762     return ret;
0763 }
0764 
0765 static int mn88443x_remove(struct i2c_client *client)
0766 {
0767     struct mn88443x_priv *chip = i2c_get_clientdata(client);
0768 
0769     mn88443x_cmn_power_off(chip);
0770 
0771     i2c_unregister_device(chip->client_t);
0772 
0773     return 0;
0774 }
0775 
0776 static const struct mn88443x_spec mn88443x_spec_pri = {
0777     .primary = true,
0778 };
0779 
0780 static const struct mn88443x_spec mn88443x_spec_sec = {
0781     .primary = false,
0782 };
0783 
0784 static const struct of_device_id mn88443x_of_match[] = {
0785     { .compatible = "socionext,mn884433",   .data = &mn88443x_spec_pri, },
0786     { .compatible = "socionext,mn884434-0", .data = &mn88443x_spec_pri, },
0787     { .compatible = "socionext,mn884434-1", .data = &mn88443x_spec_sec, },
0788     {}
0789 };
0790 MODULE_DEVICE_TABLE(of, mn88443x_of_match);
0791 
0792 static const struct i2c_device_id mn88443x_i2c_id[] = {
0793     { "mn884433",   (kernel_ulong_t)&mn88443x_spec_pri },
0794     { "mn884434-0", (kernel_ulong_t)&mn88443x_spec_pri },
0795     { "mn884434-1", (kernel_ulong_t)&mn88443x_spec_sec },
0796     {}
0797 };
0798 MODULE_DEVICE_TABLE(i2c, mn88443x_i2c_id);
0799 
0800 static struct i2c_driver mn88443x_driver = {
0801     .driver = {
0802         .name = "mn88443x",
0803         .of_match_table = of_match_ptr(mn88443x_of_match),
0804     },
0805     .probe    = mn88443x_probe,
0806     .remove   = mn88443x_remove,
0807     .id_table = mn88443x_i2c_id,
0808 };
0809 
0810 module_i2c_driver(mn88443x_driver);
0811 
0812 MODULE_AUTHOR("Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>");
0813 MODULE_DESCRIPTION("Socionext MN88443x series demodulator driver.");
0814 MODULE_LICENSE("GPL v2");
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