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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *   Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
0004  *
0005  *   Copyright (C) 2010-2013 Mauro Carvalho Chehab
0006  *   Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
0007  */
0008 
0009 #include <linux/kernel.h>
0010 #include <asm/div64.h>
0011 
0012 #include <media/dvb_frontend.h>
0013 #include "mb86a20s.h"
0014 
0015 #define NUM_LAYERS 3
0016 
0017 enum mb86a20s_bandwidth {
0018     MB86A20S_13SEG = 0,
0019     MB86A20S_13SEG_PARTIAL = 1,
0020     MB86A20S_1SEG = 2,
0021     MB86A20S_3SEG = 3,
0022 };
0023 
0024 static u8 mb86a20s_subchannel[] = {
0025     0xb0, 0xc0, 0xd0, 0xe0,
0026     0xf0, 0x00, 0x10, 0x20,
0027 };
0028 
0029 struct mb86a20s_state {
0030     struct i2c_adapter *i2c;
0031     const struct mb86a20s_config *config;
0032     u32 last_frequency;
0033 
0034     struct dvb_frontend frontend;
0035 
0036     u32 if_freq;
0037     enum mb86a20s_bandwidth bw;
0038     bool inversion;
0039     u32 subchannel;
0040 
0041     u32 estimated_rate[NUM_LAYERS];
0042     unsigned long get_strength_time;
0043 
0044     bool need_init;
0045 };
0046 
0047 struct regdata {
0048     u8 reg;
0049     u8 data;
0050 };
0051 
0052 #define BER_SAMPLING_RATE   1   /* Seconds */
0053 
0054 /*
0055  * Initialization sequence: Use whatevere default values that PV SBTVD
0056  * does on its initialisation, obtained via USB snoop
0057  */
0058 static struct regdata mb86a20s_init1[] = {
0059     { 0x70, 0x0f },
0060     { 0x70, 0xff },
0061     { 0x08, 0x01 },
0062     { 0x50, 0xd1 }, { 0x51, 0x20 },
0063 };
0064 
0065 static struct regdata mb86a20s_init2[] = {
0066     { 0x50, 0xd1 }, { 0x51, 0x22 },
0067     { 0x39, 0x01 },
0068     { 0x71, 0x00 },
0069     { 0x3b, 0x21 },
0070     { 0x3c, 0x3a },
0071     { 0x01, 0x0d },
0072     { 0x04, 0x08 }, { 0x05, 0x05 },
0073     { 0x04, 0x0e }, { 0x05, 0x00 },
0074     { 0x04, 0x0f }, { 0x05, 0x14 },
0075     { 0x04, 0x0b }, { 0x05, 0x8c },
0076     { 0x04, 0x00 }, { 0x05, 0x00 },
0077     { 0x04, 0x01 }, { 0x05, 0x07 },
0078     { 0x04, 0x02 }, { 0x05, 0x0f },
0079     { 0x04, 0x03 }, { 0x05, 0xa0 },
0080     { 0x04, 0x09 }, { 0x05, 0x00 },
0081     { 0x04, 0x0a }, { 0x05, 0xff },
0082     { 0x04, 0x27 }, { 0x05, 0x64 },
0083     { 0x04, 0x28 }, { 0x05, 0x00 },
0084     { 0x04, 0x1e }, { 0x05, 0xff },
0085     { 0x04, 0x29 }, { 0x05, 0x0a },
0086     { 0x04, 0x32 }, { 0x05, 0x0a },
0087     { 0x04, 0x14 }, { 0x05, 0x02 },
0088     { 0x04, 0x04 }, { 0x05, 0x00 },
0089     { 0x04, 0x05 }, { 0x05, 0x22 },
0090     { 0x04, 0x06 }, { 0x05, 0x0e },
0091     { 0x04, 0x07 }, { 0x05, 0xd8 },
0092     { 0x04, 0x12 }, { 0x05, 0x00 },
0093     { 0x04, 0x13 }, { 0x05, 0xff },
0094 
0095     /*
0096      * On this demod, when the bit count reaches the count below,
0097      * it collects the bit error count. The bit counters are initialized
0098      * to 65535 here. This warrants that all of them will be quickly
0099      * calculated when device gets locked. As TMCC is parsed, the values
0100      * will be adjusted later in the driver's code.
0101      */
0102     { 0x52, 0x01 },             /* Turn on BER before Viterbi */
0103     { 0x50, 0xa7 }, { 0x51, 0x00 },
0104     { 0x50, 0xa8 }, { 0x51, 0xff },
0105     { 0x50, 0xa9 }, { 0x51, 0xff },
0106     { 0x50, 0xaa }, { 0x51, 0x00 },
0107     { 0x50, 0xab }, { 0x51, 0xff },
0108     { 0x50, 0xac }, { 0x51, 0xff },
0109     { 0x50, 0xad }, { 0x51, 0x00 },
0110     { 0x50, 0xae }, { 0x51, 0xff },
0111     { 0x50, 0xaf }, { 0x51, 0xff },
0112 
0113     /*
0114      * On this demod, post BER counts blocks. When the count reaches the
0115      * value below, it collects the block error count. The block counters
0116      * are initialized to 127 here. This warrants that all of them will be
0117      * quickly calculated when device gets locked. As TMCC is parsed, the
0118      * values will be adjusted later in the driver's code.
0119      */
0120     { 0x5e, 0x07 },             /* Turn on BER after Viterbi */
0121     { 0x50, 0xdc }, { 0x51, 0x00 },
0122     { 0x50, 0xdd }, { 0x51, 0x7f },
0123     { 0x50, 0xde }, { 0x51, 0x00 },
0124     { 0x50, 0xdf }, { 0x51, 0x7f },
0125     { 0x50, 0xe0 }, { 0x51, 0x00 },
0126     { 0x50, 0xe1 }, { 0x51, 0x7f },
0127 
0128     /*
0129      * On this demod, when the block count reaches the count below,
0130      * it collects the block error count. The block counters are initialized
0131      * to 127 here. This warrants that all of them will be quickly
0132      * calculated when device gets locked. As TMCC is parsed, the values
0133      * will be adjusted later in the driver's code.
0134      */
0135     { 0x50, 0xb0 }, { 0x51, 0x07 },     /* Enable PER */
0136     { 0x50, 0xb2 }, { 0x51, 0x00 },
0137     { 0x50, 0xb3 }, { 0x51, 0x7f },
0138     { 0x50, 0xb4 }, { 0x51, 0x00 },
0139     { 0x50, 0xb5 }, { 0x51, 0x7f },
0140     { 0x50, 0xb6 }, { 0x51, 0x00 },
0141     { 0x50, 0xb7 }, { 0x51, 0x7f },
0142 
0143     { 0x50, 0x50 }, { 0x51, 0x02 },     /* MER manual mode */
0144     { 0x50, 0x51 }, { 0x51, 0x04 },     /* MER symbol 4 */
0145     { 0x45, 0x04 },             /* CN symbol 4 */
0146     { 0x48, 0x04 },             /* CN manual mode */
0147     { 0x50, 0xd5 }, { 0x51, 0x01 },
0148     { 0x50, 0xd6 }, { 0x51, 0x1f },
0149     { 0x50, 0xd2 }, { 0x51, 0x03 },
0150     { 0x50, 0xd7 }, { 0x51, 0x3f },
0151     { 0x1c, 0x01 },
0152     { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
0153     { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
0154     { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
0155     { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
0156     { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
0157     { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
0158     { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
0159     { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
0160     { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
0161     { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
0162     { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
0163     { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
0164     { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
0165     { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
0166     { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
0167     { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
0168     { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
0169     { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
0170     { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
0171     { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
0172     { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
0173     { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
0174     { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
0175     { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
0176     { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
0177     { 0x50, 0x1e }, { 0x51, 0x5d },
0178     { 0x50, 0x22 }, { 0x51, 0x00 },
0179     { 0x50, 0x23 }, { 0x51, 0xc8 },
0180     { 0x50, 0x24 }, { 0x51, 0x00 },
0181     { 0x50, 0x25 }, { 0x51, 0xf0 },
0182     { 0x50, 0x26 }, { 0x51, 0x00 },
0183     { 0x50, 0x27 }, { 0x51, 0xc3 },
0184     { 0x50, 0x39 }, { 0x51, 0x02 },
0185     { 0x50, 0xd5 }, { 0x51, 0x01 },
0186     { 0xd0, 0x00 },
0187 };
0188 
0189 static struct regdata mb86a20s_reset_reception[] = {
0190     { 0x70, 0xf0 },
0191     { 0x70, 0xff },
0192     { 0x08, 0x01 },
0193     { 0x08, 0x00 },
0194 };
0195 
0196 static struct regdata mb86a20s_per_ber_reset[] = {
0197     { 0x53, 0x00 }, /* pre BER Counter reset */
0198     { 0x53, 0x07 },
0199 
0200     { 0x5f, 0x00 }, /* post BER Counter reset */
0201     { 0x5f, 0x07 },
0202 
0203     { 0x50, 0xb1 }, /* PER Counter reset */
0204     { 0x51, 0x07 },
0205     { 0x51, 0x00 },
0206 };
0207 
0208 /*
0209  * I2C read/write functions and macros
0210  */
0211 
0212 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
0213                  u8 i2c_addr, u8 reg, u8 data)
0214 {
0215     u8 buf[] = { reg, data };
0216     struct i2c_msg msg = {
0217         .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
0218     };
0219     int rc;
0220 
0221     rc = i2c_transfer(state->i2c, &msg, 1);
0222     if (rc != 1) {
0223         dev_err(&state->i2c->dev,
0224             "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
0225             __func__, rc, reg, data);
0226         return rc;
0227     }
0228 
0229     return 0;
0230 }
0231 
0232 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
0233                      u8 i2c_addr, struct regdata *rd, int size)
0234 {
0235     int i, rc;
0236 
0237     for (i = 0; i < size; i++) {
0238         rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
0239                        rd[i].data);
0240         if (rc < 0)
0241             return rc;
0242     }
0243     return 0;
0244 }
0245 
0246 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
0247                 u8 i2c_addr, u8 reg)
0248 {
0249     u8 val;
0250     int rc;
0251     struct i2c_msg msg[] = {
0252         { .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
0253         { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
0254     };
0255 
0256     rc = i2c_transfer(state->i2c, msg, 2);
0257 
0258     if (rc != 2) {
0259         dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
0260             __func__, reg, rc);
0261         return (rc < 0) ? rc : -EIO;
0262     }
0263 
0264     return val;
0265 }
0266 
0267 #define mb86a20s_readreg(state, reg) \
0268     mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
0269 #define mb86a20s_writereg(state, reg, val) \
0270     mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
0271 #define mb86a20s_writeregdata(state, regdata) \
0272     mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
0273     regdata, ARRAY_SIZE(regdata))
0274 
0275 /*
0276  * Ancillary internal routines (likely compiled inlined)
0277  *
0278  * The functions below assume that gateway lock has already obtained
0279  */
0280 
0281 static int mb86a20s_read_status(struct dvb_frontend *fe, enum fe_status *status)
0282 {
0283     struct mb86a20s_state *state = fe->demodulator_priv;
0284     int val;
0285 
0286     *status = 0;
0287 
0288     val = mb86a20s_readreg(state, 0x0a);
0289     if (val < 0)
0290         return val;
0291 
0292     val &= 0xf;
0293     if (val >= 2)
0294         *status |= FE_HAS_SIGNAL;
0295 
0296     if (val >= 4)
0297         *status |= FE_HAS_CARRIER;
0298 
0299     if (val >= 5)
0300         *status |= FE_HAS_VITERBI;
0301 
0302     if (val >= 7)
0303         *status |= FE_HAS_SYNC;
0304 
0305     /*
0306      * Actually, on state S8, it starts receiving TS, but the TS
0307      * output is only on normal state after the transition to S9.
0308      */
0309     if (val >= 9)
0310         *status |= FE_HAS_LOCK;
0311 
0312     dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
0313          __func__, *status, val);
0314 
0315     return val;
0316 }
0317 
0318 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
0319 {
0320     struct mb86a20s_state *state = fe->demodulator_priv;
0321     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0322     int rc;
0323     unsigned rf_max, rf_min, rf;
0324 
0325     if (state->get_strength_time &&
0326        (!time_after(jiffies, state->get_strength_time)))
0327         return c->strength.stat[0].uvalue;
0328 
0329     /* Reset its value if an error happen */
0330     c->strength.stat[0].uvalue = 0;
0331 
0332     /* Does a binary search to get RF strength */
0333     rf_max = 0xfff;
0334     rf_min = 0;
0335     do {
0336         rf = (rf_max + rf_min) / 2;
0337         rc = mb86a20s_writereg(state, 0x04, 0x1f);
0338         if (rc < 0)
0339             return rc;
0340         rc = mb86a20s_writereg(state, 0x05, rf >> 8);
0341         if (rc < 0)
0342             return rc;
0343         rc = mb86a20s_writereg(state, 0x04, 0x20);
0344         if (rc < 0)
0345             return rc;
0346         rc = mb86a20s_writereg(state, 0x05, rf);
0347         if (rc < 0)
0348             return rc;
0349 
0350         rc = mb86a20s_readreg(state, 0x02);
0351         if (rc < 0)
0352             return rc;
0353         if (rc & 0x08)
0354             rf_min = (rf_max + rf_min) / 2;
0355         else
0356             rf_max = (rf_max + rf_min) / 2;
0357         if (rf_max - rf_min < 4) {
0358             rf = (rf_max + rf_min) / 2;
0359 
0360             /* Rescale it from 2^12 (4096) to 2^16 */
0361             rf = rf << (16 - 12);
0362             if (rf)
0363                 rf |= (1 << 12) - 1;
0364 
0365             dev_dbg(&state->i2c->dev,
0366                 "%s: signal strength = %d (%d < RF=%d < %d)\n",
0367                 __func__, rf, rf_min, rf >> 4, rf_max);
0368             c->strength.stat[0].uvalue = rf;
0369             state->get_strength_time = jiffies +
0370                            msecs_to_jiffies(1000);
0371             return 0;
0372         }
0373     } while (1);
0374 }
0375 
0376 static int mb86a20s_get_modulation(struct mb86a20s_state *state,
0377                    unsigned layer)
0378 {
0379     int rc;
0380     static unsigned char reg[] = {
0381         [0] = 0x86, /* Layer A */
0382         [1] = 0x8a, /* Layer B */
0383         [2] = 0x8e, /* Layer C */
0384     };
0385 
0386     if (layer >= ARRAY_SIZE(reg))
0387         return -EINVAL;
0388     rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
0389     if (rc < 0)
0390         return rc;
0391     rc = mb86a20s_readreg(state, 0x6e);
0392     if (rc < 0)
0393         return rc;
0394     switch ((rc >> 4) & 0x07) {
0395     case 0:
0396         return DQPSK;
0397     case 1:
0398         return QPSK;
0399     case 2:
0400         return QAM_16;
0401     case 3:
0402         return QAM_64;
0403     default:
0404         return QAM_AUTO;
0405     }
0406 }
0407 
0408 static int mb86a20s_get_fec(struct mb86a20s_state *state,
0409                 unsigned layer)
0410 {
0411     int rc;
0412 
0413     static unsigned char reg[] = {
0414         [0] = 0x87, /* Layer A */
0415         [1] = 0x8b, /* Layer B */
0416         [2] = 0x8f, /* Layer C */
0417     };
0418 
0419     if (layer >= ARRAY_SIZE(reg))
0420         return -EINVAL;
0421     rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
0422     if (rc < 0)
0423         return rc;
0424     rc = mb86a20s_readreg(state, 0x6e);
0425     if (rc < 0)
0426         return rc;
0427     switch ((rc >> 4) & 0x07) {
0428     case 0:
0429         return FEC_1_2;
0430     case 1:
0431         return FEC_2_3;
0432     case 2:
0433         return FEC_3_4;
0434     case 3:
0435         return FEC_5_6;
0436     case 4:
0437         return FEC_7_8;
0438     default:
0439         return FEC_AUTO;
0440     }
0441 }
0442 
0443 static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
0444                      unsigned layer)
0445 {
0446     int rc;
0447     static const int interleaving[] = {
0448         0, 1, 2, 4, 8
0449     };
0450 
0451     static const unsigned char reg[] = {
0452         [0] = 0x88, /* Layer A */
0453         [1] = 0x8c, /* Layer B */
0454         [2] = 0x90, /* Layer C */
0455     };
0456 
0457     if (layer >= ARRAY_SIZE(reg))
0458         return -EINVAL;
0459     rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
0460     if (rc < 0)
0461         return rc;
0462     rc = mb86a20s_readreg(state, 0x6e);
0463     if (rc < 0)
0464         return rc;
0465 
0466     return interleaving[(rc >> 4) & 0x07];
0467 }
0468 
0469 static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
0470                       unsigned layer)
0471 {
0472     int rc, count;
0473     static unsigned char reg[] = {
0474         [0] = 0x89, /* Layer A */
0475         [1] = 0x8d, /* Layer B */
0476         [2] = 0x91, /* Layer C */
0477     };
0478 
0479     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
0480 
0481     if (layer >= ARRAY_SIZE(reg))
0482         return -EINVAL;
0483 
0484     rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
0485     if (rc < 0)
0486         return rc;
0487     rc = mb86a20s_readreg(state, 0x6e);
0488     if (rc < 0)
0489         return rc;
0490     count = (rc >> 4) & 0x0f;
0491 
0492     dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
0493 
0494     return count;
0495 }
0496 
0497 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
0498 {
0499     struct mb86a20s_state *state = fe->demodulator_priv;
0500     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0501 
0502     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
0503 
0504     /* Fixed parameters */
0505     c->delivery_system = SYS_ISDBT;
0506     c->bandwidth_hz = 6000000;
0507 
0508     /* Initialize values that will be later autodetected */
0509     c->isdbt_layer_enabled = 0;
0510     c->transmission_mode = TRANSMISSION_MODE_AUTO;
0511     c->guard_interval = GUARD_INTERVAL_AUTO;
0512     c->isdbt_sb_mode = 0;
0513     c->isdbt_sb_segment_count = 0;
0514 }
0515 
0516 /*
0517  * Estimates the bit rate using the per-segment bit rate given by
0518  * ABNT/NBR 15601 spec (table 4).
0519  */
0520 static const u32 isdbt_rate[3][5][4] = {
0521     {   /* DQPSK/QPSK */
0522         {  280850,  312060,  330420,  340430 }, /* 1/2 */
0523         {  374470,  416080,  440560,  453910 }, /* 2/3 */
0524         {  421280,  468090,  495630,  510650 }, /* 3/4 */
0525         {  468090,  520100,  550700,  567390 }, /* 5/6 */
0526         {  491500,  546110,  578230,  595760 }, /* 7/8 */
0527     }, {    /* QAM16 */
0528         {  561710,  624130,  660840,  680870 }, /* 1/2 */
0529         {  748950,  832170,  881120,  907820 }, /* 2/3 */
0530         {  842570,  936190,  991260, 1021300 }, /* 3/4 */
0531         {  936190, 1040210, 1101400, 1134780 }, /* 5/6 */
0532         {  983000, 1092220, 1156470, 1191520 }, /* 7/8 */
0533     }, {    /* QAM64 */
0534         {  842570,  936190,  991260, 1021300 }, /* 1/2 */
0535         { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
0536         { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
0537         { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
0538         { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
0539     }
0540 };
0541 
0542 static u32 isdbt_layer_min_bitrate(struct dtv_frontend_properties *c,
0543                    u32 layer)
0544 {
0545     int mod, fec, guard;
0546 
0547     /*
0548      * If modulation/fec/guard is not detected, the default is
0549      * to consider the lowest bit rate, to avoid taking too long time
0550      * to get BER.
0551      */
0552     switch (c->layer[layer].modulation) {
0553     case DQPSK:
0554     case QPSK:
0555     default:
0556         mod = 0;
0557         break;
0558     case QAM_16:
0559         mod = 1;
0560         break;
0561     case QAM_64:
0562         mod = 2;
0563         break;
0564     }
0565 
0566     switch (c->layer[layer].fec) {
0567     default:
0568     case FEC_1_2:
0569     case FEC_AUTO:
0570         fec = 0;
0571         break;
0572     case FEC_2_3:
0573         fec = 1;
0574         break;
0575     case FEC_3_4:
0576         fec = 2;
0577         break;
0578     case FEC_5_6:
0579         fec = 3;
0580         break;
0581     case FEC_7_8:
0582         fec = 4;
0583         break;
0584     }
0585 
0586     switch (c->guard_interval) {
0587     default:
0588     case GUARD_INTERVAL_1_4:
0589         guard = 0;
0590         break;
0591     case GUARD_INTERVAL_1_8:
0592         guard = 1;
0593         break;
0594     case GUARD_INTERVAL_1_16:
0595         guard = 2;
0596         break;
0597     case GUARD_INTERVAL_1_32:
0598         guard = 3;
0599         break;
0600     }
0601 
0602     return isdbt_rate[mod][fec][guard] * c->layer[layer].segment_count;
0603 }
0604 
0605 static int mb86a20s_get_frontend(struct dvb_frontend *fe)
0606 {
0607     struct mb86a20s_state *state = fe->demodulator_priv;
0608     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0609     int layer, rc, rate, counter;
0610 
0611     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
0612 
0613     /* Reset frontend cache to default values */
0614     mb86a20s_reset_frontend_cache(fe);
0615 
0616     /* Check for partial reception */
0617     rc = mb86a20s_writereg(state, 0x6d, 0x85);
0618     if (rc < 0)
0619         return rc;
0620     rc = mb86a20s_readreg(state, 0x6e);
0621     if (rc < 0)
0622         return rc;
0623     c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
0624 
0625     /* Get per-layer data */
0626 
0627     for (layer = 0; layer < NUM_LAYERS; layer++) {
0628         dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
0629             __func__, 'A' + layer);
0630 
0631         rc = mb86a20s_get_segment_count(state, layer);
0632         if (rc < 0)
0633             goto noperlayer_error;
0634         if (rc >= 0 && rc < 14) {
0635             c->layer[layer].segment_count = rc;
0636         } else {
0637             c->layer[layer].segment_count = 0;
0638             state->estimated_rate[layer] = 0;
0639             continue;
0640         }
0641         c->isdbt_layer_enabled |= 1 << layer;
0642         rc = mb86a20s_get_modulation(state, layer);
0643         if (rc < 0)
0644             goto noperlayer_error;
0645         dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
0646             __func__, rc);
0647         c->layer[layer].modulation = rc;
0648         rc = mb86a20s_get_fec(state, layer);
0649         if (rc < 0)
0650             goto noperlayer_error;
0651         dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
0652             __func__, rc);
0653         c->layer[layer].fec = rc;
0654         rc = mb86a20s_get_interleaving(state, layer);
0655         if (rc < 0)
0656             goto noperlayer_error;
0657         dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
0658             __func__, rc);
0659         c->layer[layer].interleaving = rc;
0660 
0661         rate = isdbt_layer_min_bitrate(c, layer);
0662         counter = rate * BER_SAMPLING_RATE;
0663 
0664         /* Avoids sampling too quickly or to overflow the register */
0665         if (counter < 256)
0666             counter = 256;
0667         else if (counter > (1 << 24) - 1)
0668             counter = (1 << 24) - 1;
0669 
0670         dev_dbg(&state->i2c->dev,
0671             "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
0672             __func__, 'A' + layer, rate / 1000, counter, counter);
0673 
0674         state->estimated_rate[layer] = counter;
0675     }
0676 
0677     rc = mb86a20s_writereg(state, 0x6d, 0x84);
0678     if (rc < 0)
0679         return rc;
0680     if ((rc & 0x60) == 0x20) {
0681         c->isdbt_sb_mode = 1;
0682         /* At least, one segment should exist */
0683         if (!c->isdbt_sb_segment_count)
0684             c->isdbt_sb_segment_count = 1;
0685     }
0686 
0687     /* Get transmission mode and guard interval */
0688     rc = mb86a20s_readreg(state, 0x07);
0689     if (rc < 0)
0690         return rc;
0691     c->transmission_mode = TRANSMISSION_MODE_AUTO;
0692     if ((rc & 0x60) == 0x20) {
0693         /* Only modes 2 and 3 are supported */
0694         switch ((rc >> 2) & 0x03) {
0695         case 1:
0696             c->transmission_mode = TRANSMISSION_MODE_4K;
0697             break;
0698         case 2:
0699             c->transmission_mode = TRANSMISSION_MODE_8K;
0700             break;
0701         }
0702     }
0703     c->guard_interval = GUARD_INTERVAL_AUTO;
0704     if (!(rc & 0x10)) {
0705         /* Guard interval 1/32 is not supported */
0706         switch (rc & 0x3) {
0707         case 0:
0708             c->guard_interval = GUARD_INTERVAL_1_4;
0709             break;
0710         case 1:
0711             c->guard_interval = GUARD_INTERVAL_1_8;
0712             break;
0713         case 2:
0714             c->guard_interval = GUARD_INTERVAL_1_16;
0715             break;
0716         }
0717     }
0718     return 0;
0719 
0720 noperlayer_error:
0721 
0722     /* per-layer info is incomplete; discard all per-layer */
0723     c->isdbt_layer_enabled = 0;
0724 
0725     return rc;
0726 }
0727 
0728 static int mb86a20s_reset_counters(struct dvb_frontend *fe)
0729 {
0730     struct mb86a20s_state *state = fe->demodulator_priv;
0731     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0732     int rc, val;
0733 
0734     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
0735 
0736     /* Reset the counters, if the channel changed */
0737     if (state->last_frequency != c->frequency) {
0738         memset(&c->cnr, 0, sizeof(c->cnr));
0739         memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
0740         memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
0741         memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
0742         memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
0743         memset(&c->block_error, 0, sizeof(c->block_error));
0744         memset(&c->block_count, 0, sizeof(c->block_count));
0745 
0746         state->last_frequency = c->frequency;
0747     }
0748 
0749     /* Clear status for most stats */
0750 
0751     /* BER/PER counter reset */
0752     rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
0753     if (rc < 0)
0754         goto err;
0755 
0756     /* CNR counter reset */
0757     rc = mb86a20s_readreg(state, 0x45);
0758     if (rc < 0)
0759         goto err;
0760     val = rc;
0761     rc = mb86a20s_writereg(state, 0x45, val | 0x10);
0762     if (rc < 0)
0763         goto err;
0764     rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
0765     if (rc < 0)
0766         goto err;
0767 
0768     /* MER counter reset */
0769     rc = mb86a20s_writereg(state, 0x50, 0x50);
0770     if (rc < 0)
0771         goto err;
0772     rc = mb86a20s_readreg(state, 0x51);
0773     if (rc < 0)
0774         goto err;
0775     val = rc;
0776     rc = mb86a20s_writereg(state, 0x51, val | 0x01);
0777     if (rc < 0)
0778         goto err;
0779     rc = mb86a20s_writereg(state, 0x51, val & 0x06);
0780     if (rc < 0)
0781         goto err;
0782 
0783     goto ok;
0784 err:
0785     dev_err(&state->i2c->dev,
0786         "%s: Can't reset FE statistics (error %d).\n",
0787         __func__, rc);
0788 ok:
0789     return rc;
0790 }
0791 
0792 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
0793                 unsigned layer,
0794                 u32 *error, u32 *count)
0795 {
0796     struct mb86a20s_state *state = fe->demodulator_priv;
0797     int rc, val;
0798 
0799     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
0800 
0801     if (layer >= NUM_LAYERS)
0802         return -EINVAL;
0803 
0804     /* Check if the BER measures are already available */
0805     rc = mb86a20s_readreg(state, 0x54);
0806     if (rc < 0)
0807         return rc;
0808 
0809     /* Check if data is available for that layer */
0810     if (!(rc & (1 << layer))) {
0811         dev_dbg(&state->i2c->dev,
0812             "%s: preBER for layer %c is not available yet.\n",
0813             __func__, 'A' + layer);
0814         return -EBUSY;
0815     }
0816 
0817     /* Read Bit Error Count */
0818     rc = mb86a20s_readreg(state, 0x55 + layer * 3);
0819     if (rc < 0)
0820         return rc;
0821     *error = rc << 16;
0822     rc = mb86a20s_readreg(state, 0x56 + layer * 3);
0823     if (rc < 0)
0824         return rc;
0825     *error |= rc << 8;
0826     rc = mb86a20s_readreg(state, 0x57 + layer * 3);
0827     if (rc < 0)
0828         return rc;
0829     *error |= rc;
0830 
0831     dev_dbg(&state->i2c->dev,
0832         "%s: bit error before Viterbi for layer %c: %d.\n",
0833         __func__, 'A' + layer, *error);
0834 
0835     /* Read Bit Count */
0836     rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
0837     if (rc < 0)
0838         return rc;
0839     rc = mb86a20s_readreg(state, 0x51);
0840     if (rc < 0)
0841         return rc;
0842     *count = rc << 16;
0843     rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
0844     if (rc < 0)
0845         return rc;
0846     rc = mb86a20s_readreg(state, 0x51);
0847     if (rc < 0)
0848         return rc;
0849     *count |= rc << 8;
0850     rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
0851     if (rc < 0)
0852         return rc;
0853     rc = mb86a20s_readreg(state, 0x51);
0854     if (rc < 0)
0855         return rc;
0856     *count |= rc;
0857 
0858     dev_dbg(&state->i2c->dev,
0859         "%s: bit count before Viterbi for layer %c: %d.\n",
0860         __func__, 'A' + layer, *count);
0861 
0862 
0863     /*
0864      * As we get TMCC data from the frontend, we can better estimate the
0865      * BER bit counters, in order to do the BER measure during a longer
0866      * time. Use those data, if available, to update the bit count
0867      * measure.
0868      */
0869 
0870     if (state->estimated_rate[layer]
0871         && state->estimated_rate[layer] != *count) {
0872         dev_dbg(&state->i2c->dev,
0873             "%s: updating layer %c preBER counter to %d.\n",
0874             __func__, 'A' + layer, state->estimated_rate[layer]);
0875 
0876         /* Turn off BER before Viterbi */
0877         rc = mb86a20s_writereg(state, 0x52, 0x00);
0878 
0879         /* Update counter for this layer */
0880         rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
0881         if (rc < 0)
0882             return rc;
0883         rc = mb86a20s_writereg(state, 0x51,
0884                        state->estimated_rate[layer] >> 16);
0885         if (rc < 0)
0886             return rc;
0887         rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
0888         if (rc < 0)
0889             return rc;
0890         rc = mb86a20s_writereg(state, 0x51,
0891                        state->estimated_rate[layer] >> 8);
0892         if (rc < 0)
0893             return rc;
0894         rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
0895         if (rc < 0)
0896             return rc;
0897         rc = mb86a20s_writereg(state, 0x51,
0898                        state->estimated_rate[layer]);
0899         if (rc < 0)
0900             return rc;
0901 
0902         /* Turn on BER before Viterbi */
0903         rc = mb86a20s_writereg(state, 0x52, 0x01);
0904 
0905         /* Reset all preBER counters */
0906         rc = mb86a20s_writereg(state, 0x53, 0x00);
0907         if (rc < 0)
0908             return rc;
0909         rc = mb86a20s_writereg(state, 0x53, 0x07);
0910     } else {
0911         /* Reset counter to collect new data */
0912         rc = mb86a20s_readreg(state, 0x53);
0913         if (rc < 0)
0914             return rc;
0915         val = rc;
0916         rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
0917         if (rc < 0)
0918             return rc;
0919         rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
0920     }
0921 
0922     return rc;
0923 }
0924 
0925 static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
0926                  unsigned layer,
0927                   u32 *error, u32 *count)
0928 {
0929     struct mb86a20s_state *state = fe->demodulator_priv;
0930     u32 counter, collect_rate;
0931     int rc, val;
0932 
0933     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
0934 
0935     if (layer >= NUM_LAYERS)
0936         return -EINVAL;
0937 
0938     /* Check if the BER measures are already available */
0939     rc = mb86a20s_readreg(state, 0x60);
0940     if (rc < 0)
0941         return rc;
0942 
0943     /* Check if data is available for that layer */
0944     if (!(rc & (1 << layer))) {
0945         dev_dbg(&state->i2c->dev,
0946             "%s: post BER for layer %c is not available yet.\n",
0947             __func__, 'A' + layer);
0948         return -EBUSY;
0949     }
0950 
0951     /* Read Bit Error Count */
0952     rc = mb86a20s_readreg(state, 0x64 + layer * 3);
0953     if (rc < 0)
0954         return rc;
0955     *error = rc << 16;
0956     rc = mb86a20s_readreg(state, 0x65 + layer * 3);
0957     if (rc < 0)
0958         return rc;
0959     *error |= rc << 8;
0960     rc = mb86a20s_readreg(state, 0x66 + layer * 3);
0961     if (rc < 0)
0962         return rc;
0963     *error |= rc;
0964 
0965     dev_dbg(&state->i2c->dev,
0966         "%s: post bit error for layer %c: %d.\n",
0967         __func__, 'A' + layer, *error);
0968 
0969     /* Read Bit Count */
0970     rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
0971     if (rc < 0)
0972         return rc;
0973     rc = mb86a20s_readreg(state, 0x51);
0974     if (rc < 0)
0975         return rc;
0976     counter = rc << 8;
0977     rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
0978     if (rc < 0)
0979         return rc;
0980     rc = mb86a20s_readreg(state, 0x51);
0981     if (rc < 0)
0982         return rc;
0983     counter |= rc;
0984     *count = counter * 204 * 8;
0985 
0986     dev_dbg(&state->i2c->dev,
0987         "%s: post bit count for layer %c: %d.\n",
0988         __func__, 'A' + layer, *count);
0989 
0990     /*
0991      * As we get TMCC data from the frontend, we can better estimate the
0992      * BER bit counters, in order to do the BER measure during a longer
0993      * time. Use those data, if available, to update the bit count
0994      * measure.
0995      */
0996 
0997     if (!state->estimated_rate[layer])
0998         goto reset_measurement;
0999 
1000     collect_rate = state->estimated_rate[layer] / 204 / 8;
1001     if (collect_rate < 32)
1002         collect_rate = 32;
1003     if (collect_rate > 65535)
1004         collect_rate = 65535;
1005     if (collect_rate != counter) {
1006         dev_dbg(&state->i2c->dev,
1007             "%s: updating postBER counter on layer %c to %d.\n",
1008             __func__, 'A' + layer, collect_rate);
1009 
1010         /* Turn off BER after Viterbi */
1011         rc = mb86a20s_writereg(state, 0x5e, 0x00);
1012 
1013         /* Update counter for this layer */
1014         rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1015         if (rc < 0)
1016             return rc;
1017         rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1018         if (rc < 0)
1019             return rc;
1020         rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1021         if (rc < 0)
1022             return rc;
1023         rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1024         if (rc < 0)
1025             return rc;
1026 
1027         /* Turn on BER after Viterbi */
1028         rc = mb86a20s_writereg(state, 0x5e, 0x07);
1029 
1030         /* Reset all preBER counters */
1031         rc = mb86a20s_writereg(state, 0x5f, 0x00);
1032         if (rc < 0)
1033             return rc;
1034         rc = mb86a20s_writereg(state, 0x5f, 0x07);
1035 
1036         return rc;
1037     }
1038 
1039 reset_measurement:
1040     /* Reset counter to collect new data */
1041     rc = mb86a20s_readreg(state, 0x5f);
1042     if (rc < 0)
1043         return rc;
1044     val = rc;
1045     rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
1046     if (rc < 0)
1047         return rc;
1048     rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
1049 
1050     return rc;
1051 }
1052 
1053 static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1054                 unsigned layer,
1055                 u32 *error, u32 *count)
1056 {
1057     struct mb86a20s_state *state = fe->demodulator_priv;
1058     int rc, val;
1059     u32 collect_rate;
1060     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1061 
1062     if (layer >= NUM_LAYERS)
1063         return -EINVAL;
1064 
1065     /* Check if the PER measures are already available */
1066     rc = mb86a20s_writereg(state, 0x50, 0xb8);
1067     if (rc < 0)
1068         return rc;
1069     rc = mb86a20s_readreg(state, 0x51);
1070     if (rc < 0)
1071         return rc;
1072 
1073     /* Check if data is available for that layer */
1074 
1075     if (!(rc & (1 << layer))) {
1076         dev_dbg(&state->i2c->dev,
1077             "%s: block counts for layer %c aren't available yet.\n",
1078             __func__, 'A' + layer);
1079         return -EBUSY;
1080     }
1081 
1082     /* Read Packet error Count */
1083     rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1084     if (rc < 0)
1085         return rc;
1086     rc = mb86a20s_readreg(state, 0x51);
1087     if (rc < 0)
1088         return rc;
1089     *error = rc << 8;
1090     rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1091     if (rc < 0)
1092         return rc;
1093     rc = mb86a20s_readreg(state, 0x51);
1094     if (rc < 0)
1095         return rc;
1096     *error |= rc;
1097     dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
1098         __func__, 'A' + layer, *error);
1099 
1100     /* Read Bit Count */
1101     rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1102     if (rc < 0)
1103         return rc;
1104     rc = mb86a20s_readreg(state, 0x51);
1105     if (rc < 0)
1106         return rc;
1107     *count = rc << 8;
1108     rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1109     if (rc < 0)
1110         return rc;
1111     rc = mb86a20s_readreg(state, 0x51);
1112     if (rc < 0)
1113         return rc;
1114     *count |= rc;
1115 
1116     dev_dbg(&state->i2c->dev,
1117         "%s: block count for layer %c: %d.\n",
1118         __func__, 'A' + layer, *count);
1119 
1120     /*
1121      * As we get TMCC data from the frontend, we can better estimate the
1122      * BER bit counters, in order to do the BER measure during a longer
1123      * time. Use those data, if available, to update the bit count
1124      * measure.
1125      */
1126 
1127     if (!state->estimated_rate[layer])
1128         goto reset_measurement;
1129 
1130     collect_rate = state->estimated_rate[layer] / 204 / 8;
1131     if (collect_rate < 32)
1132         collect_rate = 32;
1133     if (collect_rate > 65535)
1134         collect_rate = 65535;
1135 
1136     if (collect_rate != *count) {
1137         dev_dbg(&state->i2c->dev,
1138             "%s: updating PER counter on layer %c to %d.\n",
1139             __func__, 'A' + layer, collect_rate);
1140 
1141         /* Stop PER measurement */
1142         rc = mb86a20s_writereg(state, 0x50, 0xb0);
1143         if (rc < 0)
1144             return rc;
1145         rc = mb86a20s_writereg(state, 0x51, 0x00);
1146         if (rc < 0)
1147             return rc;
1148 
1149         /* Update this layer's counter */
1150         rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1151         if (rc < 0)
1152             return rc;
1153         rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1154         if (rc < 0)
1155             return rc;
1156         rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1157         if (rc < 0)
1158             return rc;
1159         rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1160         if (rc < 0)
1161             return rc;
1162 
1163         /* start PER measurement */
1164         rc = mb86a20s_writereg(state, 0x50, 0xb0);
1165         if (rc < 0)
1166             return rc;
1167         rc = mb86a20s_writereg(state, 0x51, 0x07);
1168         if (rc < 0)
1169             return rc;
1170 
1171         /* Reset all counters to collect new data */
1172         rc = mb86a20s_writereg(state, 0x50, 0xb1);
1173         if (rc < 0)
1174             return rc;
1175         rc = mb86a20s_writereg(state, 0x51, 0x07);
1176         if (rc < 0)
1177             return rc;
1178         rc = mb86a20s_writereg(state, 0x51, 0x00);
1179 
1180         return rc;
1181     }
1182 
1183 reset_measurement:
1184     /* Reset counter to collect new data */
1185     rc = mb86a20s_writereg(state, 0x50, 0xb1);
1186     if (rc < 0)
1187         return rc;
1188     rc = mb86a20s_readreg(state, 0x51);
1189     if (rc < 0)
1190         return rc;
1191     val = rc;
1192     rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
1193     if (rc < 0)
1194         return rc;
1195     rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
1196 
1197     return rc;
1198 }
1199 
1200 struct linear_segments {
1201     unsigned x, y;
1202 };
1203 
1204 /*
1205  * All tables below return a dB/1000 measurement
1206  */
1207 
1208 static const struct linear_segments cnr_to_db_table[] = {
1209     { 19648,     0},
1210     { 18187,  1000},
1211     { 16534,  2000},
1212     { 14823,  3000},
1213     { 13161,  4000},
1214     { 11622,  5000},
1215     { 10279,  6000},
1216     {  9089,  7000},
1217     {  8042,  8000},
1218     {  7137,  9000},
1219     {  6342, 10000},
1220     {  5641, 11000},
1221     {  5030, 12000},
1222     {  4474, 13000},
1223     {  3988, 14000},
1224     {  3556, 15000},
1225     {  3180, 16000},
1226     {  2841, 17000},
1227     {  2541, 18000},
1228     {  2276, 19000},
1229     {  2038, 20000},
1230     {  1800, 21000},
1231     {  1625, 22000},
1232     {  1462, 23000},
1233     {  1324, 24000},
1234     {  1175, 25000},
1235     {  1063, 26000},
1236     {   980, 27000},
1237     {   907, 28000},
1238     {   840, 29000},
1239     {   788, 30000},
1240 };
1241 
1242 static const struct linear_segments cnr_64qam_table[] = {
1243     { 3922688,     0},
1244     { 3920384,  1000},
1245     { 3902720,  2000},
1246     { 3894784,  3000},
1247     { 3882496,  4000},
1248     { 3872768,  5000},
1249     { 3858944,  6000},
1250     { 3851520,  7000},
1251     { 3838976,  8000},
1252     { 3829248,  9000},
1253     { 3818240, 10000},
1254     { 3806976, 11000},
1255     { 3791872, 12000},
1256     { 3767040, 13000},
1257     { 3720960, 14000},
1258     { 3637504, 15000},
1259     { 3498496, 16000},
1260     { 3296000, 17000},
1261     { 3031040, 18000},
1262     { 2715392, 19000},
1263     { 2362624, 20000},
1264     { 1963264, 21000},
1265     { 1649664, 22000},
1266     { 1366784, 23000},
1267     { 1120768, 24000},
1268     {  890880, 25000},
1269     {  723456, 26000},
1270     {  612096, 27000},
1271     {  518912, 28000},
1272     {  448256, 29000},
1273     {  388864, 30000},
1274 };
1275 
1276 static const struct linear_segments cnr_16qam_table[] = {
1277     { 5314816,     0},
1278     { 5219072,  1000},
1279     { 5118720,  2000},
1280     { 4998912,  3000},
1281     { 4875520,  4000},
1282     { 4736000,  5000},
1283     { 4604160,  6000},
1284     { 4458752,  7000},
1285     { 4300288,  8000},
1286     { 4092928,  9000},
1287     { 3836160, 10000},
1288     { 3521024, 11000},
1289     { 3155968, 12000},
1290     { 2756864, 13000},
1291     { 2347008, 14000},
1292     { 1955072, 15000},
1293     { 1593600, 16000},
1294     { 1297920, 17000},
1295     { 1043968, 18000},
1296     {  839680, 19000},
1297     {  672256, 20000},
1298     {  523008, 21000},
1299     {  424704, 22000},
1300     {  345088, 23000},
1301     {  280064, 24000},
1302     {  221440, 25000},
1303     {  179712, 26000},
1304     {  151040, 27000},
1305     {  128512, 28000},
1306     {  110080, 29000},
1307     {   95744, 30000},
1308 };
1309 
1310 static const struct linear_segments cnr_qpsk_table[] = {
1311     { 2834176,     0},
1312     { 2683648,  1000},
1313     { 2536960,  2000},
1314     { 2391808,  3000},
1315     { 2133248,  4000},
1316     { 1906176,  5000},
1317     { 1666560,  6000},
1318     { 1422080,  7000},
1319     { 1189632,  8000},
1320     {  976384,  9000},
1321     {  790272, 10000},
1322     {  633344, 11000},
1323     {  505600, 12000},
1324     {  402944, 13000},
1325     {  320768, 14000},
1326     {  255488, 15000},
1327     {  204032, 16000},
1328     {  163072, 17000},
1329     {  130304, 18000},
1330     {  105216, 19000},
1331     {   83456, 20000},
1332     {   65024, 21000},
1333     {   52480, 22000},
1334     {   42752, 23000},
1335     {   34560, 24000},
1336     {   27136, 25000},
1337     {   22016, 26000},
1338     {   18432, 27000},
1339     {   15616, 28000},
1340     {   13312, 29000},
1341     {   11520, 30000},
1342 };
1343 
1344 static u32 interpolate_value(u32 value, const struct linear_segments *segments,
1345                  unsigned len)
1346 {
1347     u64 tmp64;
1348     u32 dx, dy;
1349     int i, ret;
1350 
1351     if (value >= segments[0].x)
1352         return segments[0].y;
1353     if (value < segments[len-1].x)
1354         return segments[len-1].y;
1355 
1356     for (i = 1; i < len - 1; i++) {
1357         /* If value is identical, no need to interpolate */
1358         if (value == segments[i].x)
1359             return segments[i].y;
1360         if (value > segments[i].x)
1361             break;
1362     }
1363 
1364     /* Linear interpolation between the two (x,y) points */
1365     dy = segments[i].y - segments[i - 1].y;
1366     dx = segments[i - 1].x - segments[i].x;
1367     tmp64 = value - segments[i].x;
1368     tmp64 *= dy;
1369     do_div(tmp64, dx);
1370     ret = segments[i].y - tmp64;
1371 
1372     return ret;
1373 }
1374 
1375 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1376 {
1377     struct mb86a20s_state *state = fe->demodulator_priv;
1378     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1379     u32 cnr_linear, cnr;
1380     int rc, val;
1381 
1382     /* Check if CNR is available */
1383     rc = mb86a20s_readreg(state, 0x45);
1384     if (rc < 0)
1385         return rc;
1386 
1387     if (!(rc & 0x40)) {
1388         dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
1389              __func__);
1390         return -EBUSY;
1391     }
1392     val = rc;
1393 
1394     rc = mb86a20s_readreg(state, 0x46);
1395     if (rc < 0)
1396         return rc;
1397     cnr_linear = rc << 8;
1398 
1399     rc = mb86a20s_readreg(state, 0x46);
1400     if (rc < 0)
1401         return rc;
1402     cnr_linear |= rc;
1403 
1404     cnr = interpolate_value(cnr_linear,
1405                 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1406 
1407     c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1408     c->cnr.stat[0].svalue = cnr;
1409 
1410     dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1411         __func__, cnr / 1000, cnr % 1000, cnr_linear);
1412 
1413     /* CNR counter reset */
1414     rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1415     if (rc < 0)
1416         return rc;
1417     rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1418 
1419     return rc;
1420 }
1421 
1422 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
1423 {
1424     struct mb86a20s_state *state = fe->demodulator_priv;
1425     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1426     u32 mer, cnr;
1427     int rc, val, layer;
1428     const struct linear_segments *segs;
1429     unsigned segs_len;
1430 
1431     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1432 
1433     /* Check if the measures are already available */
1434     rc = mb86a20s_writereg(state, 0x50, 0x5b);
1435     if (rc < 0)
1436         return rc;
1437     rc = mb86a20s_readreg(state, 0x51);
1438     if (rc < 0)
1439         return rc;
1440 
1441     /* Check if data is available */
1442     if (!(rc & 0x01)) {
1443         dev_dbg(&state->i2c->dev,
1444             "%s: MER measures aren't available yet.\n", __func__);
1445         return -EBUSY;
1446     }
1447 
1448     /* Read all layers */
1449     for (layer = 0; layer < NUM_LAYERS; layer++) {
1450         if (!(c->isdbt_layer_enabled & (1 << layer))) {
1451             c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1452             continue;
1453         }
1454 
1455         rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
1456         if (rc < 0)
1457             return rc;
1458         rc = mb86a20s_readreg(state, 0x51);
1459         if (rc < 0)
1460             return rc;
1461         mer = rc << 16;
1462         rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
1463         if (rc < 0)
1464             return rc;
1465         rc = mb86a20s_readreg(state, 0x51);
1466         if (rc < 0)
1467             return rc;
1468         mer |= rc << 8;
1469         rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
1470         if (rc < 0)
1471             return rc;
1472         rc = mb86a20s_readreg(state, 0x51);
1473         if (rc < 0)
1474             return rc;
1475         mer |= rc;
1476 
1477         switch (c->layer[layer].modulation) {
1478         case DQPSK:
1479         case QPSK:
1480             segs = cnr_qpsk_table;
1481             segs_len = ARRAY_SIZE(cnr_qpsk_table);
1482             break;
1483         case QAM_16:
1484             segs = cnr_16qam_table;
1485             segs_len = ARRAY_SIZE(cnr_16qam_table);
1486             break;
1487         default:
1488         case QAM_64:
1489             segs = cnr_64qam_table;
1490             segs_len = ARRAY_SIZE(cnr_64qam_table);
1491             break;
1492         }
1493         cnr = interpolate_value(mer, segs, segs_len);
1494 
1495         c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
1496         c->cnr.stat[1 + layer].svalue = cnr;
1497 
1498         dev_dbg(&state->i2c->dev,
1499             "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1500             __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
1501 
1502     }
1503 
1504     /* Start a new MER measurement */
1505     /* MER counter reset */
1506     rc = mb86a20s_writereg(state, 0x50, 0x50);
1507     if (rc < 0)
1508         return rc;
1509     rc = mb86a20s_readreg(state, 0x51);
1510     if (rc < 0)
1511         return rc;
1512     val = rc;
1513 
1514     rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1515     if (rc < 0)
1516         return rc;
1517     rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1518     if (rc < 0)
1519         return rc;
1520 
1521     return 0;
1522 }
1523 
1524 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1525 {
1526     struct mb86a20s_state *state = fe->demodulator_priv;
1527     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1528     int layer;
1529 
1530     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1531 
1532     /* Fill the length of each status counter */
1533 
1534     /* Only global stats */
1535     c->strength.len = 1;
1536 
1537     /* Per-layer stats - 3 layers + global */
1538     c->cnr.len = NUM_LAYERS + 1;
1539     c->pre_bit_error.len = NUM_LAYERS + 1;
1540     c->pre_bit_count.len = NUM_LAYERS + 1;
1541     c->post_bit_error.len = NUM_LAYERS + 1;
1542     c->post_bit_count.len = NUM_LAYERS + 1;
1543     c->block_error.len = NUM_LAYERS + 1;
1544     c->block_count.len = NUM_LAYERS + 1;
1545 
1546     /* Signal is always available */
1547     c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1548     c->strength.stat[0].uvalue = 0;
1549 
1550     /* Put all of them at FE_SCALE_NOT_AVAILABLE */
1551     for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
1552         c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1553         c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1554         c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1555         c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1556         c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1557         c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1558         c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1559     }
1560 }
1561 
1562 static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
1563 {
1564     struct mb86a20s_state *state = fe->demodulator_priv;
1565     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1566     int rc = 0, layer;
1567     u32 bit_error = 0, bit_count = 0;
1568     u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
1569     u32 t_post_bit_error = 0, t_post_bit_count = 0;
1570     u32 block_error = 0, block_count = 0;
1571     u32 t_block_error = 0, t_block_count = 0;
1572     int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1573     int per_layers = 0;
1574 
1575     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1576 
1577     mb86a20s_get_main_CNR(fe);
1578 
1579     /* Get per-layer stats */
1580     mb86a20s_get_blk_error_layer_CNR(fe);
1581 
1582     /*
1583      * At state 7, only CNR is available
1584      * For BER measures, state=9 is required
1585      * FIXME: we may get MER measures with state=8
1586      */
1587     if (status_nr < 9)
1588         return 0;
1589 
1590     for (layer = 0; layer < NUM_LAYERS; layer++) {
1591         if (c->isdbt_layer_enabled & (1 << layer)) {
1592             /* Layer is active and has rc segments */
1593             active_layers++;
1594 
1595             /* Handle BER before vterbi */
1596             rc = mb86a20s_get_pre_ber(fe, layer,
1597                           &bit_error, &bit_count);
1598             if (rc >= 0) {
1599                 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1600                 c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
1601                 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1602                 c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
1603             } else if (rc != -EBUSY) {
1604                 /*
1605                     * If an I/O error happened,
1606                     * measures are now unavailable
1607                     */
1608                 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1609                 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1610                 dev_err(&state->i2c->dev,
1611                     "%s: Can't get BER for layer %c (error %d).\n",
1612                     __func__, 'A' + layer, rc);
1613             }
1614             if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1615                 pre_ber_layers++;
1616 
1617             /* Handle BER post vterbi */
1618             rc = mb86a20s_get_post_ber(fe, layer,
1619                            &bit_error, &bit_count);
1620             if (rc >= 0) {
1621                 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1622                 c->post_bit_error.stat[1 + layer].uvalue += bit_error;
1623                 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1624                 c->post_bit_count.stat[1 + layer].uvalue += bit_count;
1625             } else if (rc != -EBUSY) {
1626                 /*
1627                     * If an I/O error happened,
1628                     * measures are now unavailable
1629                     */
1630                 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1631                 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1632                 dev_err(&state->i2c->dev,
1633                     "%s: Can't get BER for layer %c (error %d).\n",
1634                     __func__, 'A' + layer, rc);
1635             }
1636             if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1637                 post_ber_layers++;
1638 
1639             /* Handle Block errors for PER/UCB reports */
1640             rc = mb86a20s_get_blk_error(fe, layer,
1641                         &block_error,
1642                         &block_count);
1643             if (rc >= 0) {
1644                 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1645                 c->block_error.stat[1 + layer].uvalue += block_error;
1646                 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1647                 c->block_count.stat[1 + layer].uvalue += block_count;
1648             } else if (rc != -EBUSY) {
1649                 /*
1650                     * If an I/O error happened,
1651                     * measures are now unavailable
1652                     */
1653                 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1654                 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1655                 dev_err(&state->i2c->dev,
1656                     "%s: Can't get PER for layer %c (error %d).\n",
1657                     __func__, 'A' + layer, rc);
1658 
1659             }
1660             if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1661                 per_layers++;
1662 
1663             /* Update total preBER */
1664             t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
1665             t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
1666 
1667             /* Update total postBER */
1668             t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
1669             t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
1670 
1671             /* Update total PER */
1672             t_block_error += c->block_error.stat[1 + layer].uvalue;
1673             t_block_count += c->block_count.stat[1 + layer].uvalue;
1674         }
1675     }
1676 
1677     /*
1678      * Start showing global count if at least one error count is
1679      * available.
1680      */
1681     if (pre_ber_layers) {
1682         /*
1683          * At least one per-layer BER measure was read. We can now
1684          * calculate the total BER
1685          *
1686          * Total Bit Error/Count is calculated as the sum of the
1687          * bit errors on all active layers.
1688          */
1689         c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1690         c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1691         c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1692         c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
1693     } else {
1694         c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1695         c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1696     }
1697 
1698     /*
1699      * Start showing global count if at least one error count is
1700      * available.
1701      */
1702     if (post_ber_layers) {
1703         /*
1704          * At least one per-layer BER measure was read. We can now
1705          * calculate the total BER
1706          *
1707          * Total Bit Error/Count is calculated as the sum of the
1708          * bit errors on all active layers.
1709          */
1710         c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1711         c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1712         c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1713         c->post_bit_count.stat[0].uvalue = t_post_bit_count;
1714     } else {
1715         c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1716         c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1717     }
1718 
1719     if (per_layers) {
1720         /*
1721          * At least one per-layer UCB measure was read. We can now
1722          * calculate the total UCB
1723          *
1724          * Total block Error/Count is calculated as the sum of the
1725          * block errors on all active layers.
1726          */
1727         c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1728         c->block_error.stat[0].uvalue = t_block_error;
1729         c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1730         c->block_count.stat[0].uvalue = t_block_count;
1731     } else {
1732         c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1733         c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1734     }
1735 
1736     return rc;
1737 }
1738 
1739 /*
1740  * The functions below are called via DVB callbacks, so they need to
1741  * properly use the I2C gate control
1742  */
1743 
1744 static int mb86a20s_initfe(struct dvb_frontend *fe)
1745 {
1746     struct mb86a20s_state *state = fe->demodulator_priv;
1747     u64 pll;
1748     u32 fclk;
1749     int rc;
1750     u8  regD5 = 1, reg71, reg09 = 0x3a;
1751 
1752     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1753 
1754     if (fe->ops.i2c_gate_ctrl)
1755         fe->ops.i2c_gate_ctrl(fe, 0);
1756 
1757     /* Initialize the frontend */
1758     rc = mb86a20s_writeregdata(state, mb86a20s_init1);
1759     if (rc < 0)
1760         goto err;
1761 
1762     if (!state->inversion)
1763         reg09 |= 0x04;
1764     rc = mb86a20s_writereg(state, 0x09, reg09);
1765     if (rc < 0)
1766         goto err;
1767     if (!state->bw)
1768         reg71 = 1;
1769     else
1770         reg71 = 0;
1771     rc = mb86a20s_writereg(state, 0x39, reg71);
1772     if (rc < 0)
1773         goto err;
1774     rc = mb86a20s_writereg(state, 0x71, state->bw);
1775     if (rc < 0)
1776         goto err;
1777     if (state->subchannel) {
1778         rc = mb86a20s_writereg(state, 0x44, state->subchannel);
1779         if (rc < 0)
1780             goto err;
1781     }
1782 
1783     fclk = state->config->fclk;
1784     if (!fclk)
1785         fclk = 32571428;
1786 
1787     /* Adjust IF frequency to match tuner */
1788     if (fe->ops.tuner_ops.get_if_frequency)
1789         fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1790 
1791     if (!state->if_freq)
1792         state->if_freq = 3300000;
1793 
1794     pll = (((u64)1) << 34) * state->if_freq;
1795     do_div(pll, 63 * fclk);
1796     pll = (1 << 25) - pll;
1797     rc = mb86a20s_writereg(state, 0x28, 0x2a);
1798     if (rc < 0)
1799         goto err;
1800     rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1801     if (rc < 0)
1802         goto err;
1803     rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1804     if (rc < 0)
1805         goto err;
1806     rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1807     if (rc < 0)
1808         goto err;
1809     dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
1810         __func__, fclk, state->if_freq, (long long)pll);
1811 
1812     /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1813     pll = state->if_freq * 1677721600L;
1814     do_div(pll, 1628571429L);
1815     rc = mb86a20s_writereg(state, 0x28, 0x20);
1816     if (rc < 0)
1817         goto err;
1818     rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1819     if (rc < 0)
1820         goto err;
1821     rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1822     if (rc < 0)
1823         goto err;
1824     rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1825     if (rc < 0)
1826         goto err;
1827     dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
1828         __func__, state->if_freq, (long long)pll);
1829 
1830     if (!state->config->is_serial)
1831         regD5 &= ~1;
1832 
1833     rc = mb86a20s_writereg(state, 0x50, 0xd5);
1834     if (rc < 0)
1835         goto err;
1836     rc = mb86a20s_writereg(state, 0x51, regD5);
1837     if (rc < 0)
1838         goto err;
1839 
1840     rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1841     if (rc < 0)
1842         goto err;
1843 
1844 
1845 err:
1846     if (fe->ops.i2c_gate_ctrl)
1847         fe->ops.i2c_gate_ctrl(fe, 1);
1848 
1849     if (rc < 0) {
1850         state->need_init = true;
1851         dev_info(&state->i2c->dev,
1852              "mb86a20s: Init failed. Will try again later\n");
1853     } else {
1854         state->need_init = false;
1855         dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
1856     }
1857     return rc;
1858 }
1859 
1860 static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1861 {
1862     struct mb86a20s_state *state = fe->demodulator_priv;
1863     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1864     int rc, if_freq;
1865     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1866 
1867     if (!c->isdbt_layer_enabled)
1868         c->isdbt_layer_enabled = 7;
1869 
1870     if (c->isdbt_layer_enabled == 1)
1871         state->bw = MB86A20S_1SEG;
1872     else if (c->isdbt_partial_reception)
1873         state->bw = MB86A20S_13SEG_PARTIAL;
1874     else
1875         state->bw = MB86A20S_13SEG;
1876 
1877     if (c->inversion == INVERSION_ON)
1878         state->inversion = true;
1879     else
1880         state->inversion = false;
1881 
1882     if (!c->isdbt_sb_mode) {
1883         state->subchannel = 0;
1884     } else {
1885         if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
1886             c->isdbt_sb_subchannel = 0;
1887 
1888         state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
1889     }
1890 
1891     /*
1892      * Gate should already be opened, but it doesn't hurt to
1893      * double-check
1894      */
1895     if (fe->ops.i2c_gate_ctrl)
1896         fe->ops.i2c_gate_ctrl(fe, 1);
1897     fe->ops.tuner_ops.set_params(fe);
1898 
1899     if (fe->ops.tuner_ops.get_if_frequency)
1900         fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1901 
1902     /*
1903      * Make it more reliable: if, for some reason, the initial
1904      * device initialization doesn't happen, initialize it when
1905      * a SBTVD parameters are adjusted.
1906      *
1907      * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1908      * the agc callback logic is not called during DVB attach time,
1909      * causing mb86a20s to not be initialized with Kworld SBTVD.
1910      * So, this hack is needed, in order to make Kworld SBTVD to work.
1911      *
1912      * It is also needed to change the IF after the initial init.
1913      *
1914      * HACK: Always init the frontend when set_frontend is called:
1915      * it was noticed that, on some devices, it fails to lock on a
1916      * different channel. So, it is better to reset everything, even
1917      * wasting some time, than to loose channel lock.
1918      */
1919     mb86a20s_initfe(fe);
1920 
1921     if (fe->ops.i2c_gate_ctrl)
1922         fe->ops.i2c_gate_ctrl(fe, 0);
1923 
1924     rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
1925     mb86a20s_reset_counters(fe);
1926     mb86a20s_stats_not_ready(fe);
1927 
1928     if (fe->ops.i2c_gate_ctrl)
1929         fe->ops.i2c_gate_ctrl(fe, 1);
1930 
1931     return rc;
1932 }
1933 
1934 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1935                       enum fe_status *status)
1936 {
1937     struct mb86a20s_state *state = fe->demodulator_priv;
1938     int rc, status_nr;
1939 
1940     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1941 
1942     if (fe->ops.i2c_gate_ctrl)
1943         fe->ops.i2c_gate_ctrl(fe, 0);
1944 
1945     /* Get lock */
1946     status_nr = mb86a20s_read_status(fe, status);
1947     if (status_nr < 7) {
1948         mb86a20s_stats_not_ready(fe);
1949         mb86a20s_reset_frontend_cache(fe);
1950     }
1951     if (status_nr < 0) {
1952         dev_err(&state->i2c->dev,
1953             "%s: Can't read frontend lock status\n", __func__);
1954         rc = status_nr;
1955         goto error;
1956     }
1957 
1958     /* Get signal strength */
1959     rc = mb86a20s_read_signal_strength(fe);
1960     if (rc < 0) {
1961         dev_err(&state->i2c->dev,
1962             "%s: Can't reset VBER registers.\n", __func__);
1963         mb86a20s_stats_not_ready(fe);
1964         mb86a20s_reset_frontend_cache(fe);
1965 
1966         rc = 0;     /* Status is OK */
1967         goto error;
1968     }
1969 
1970     if (status_nr >= 7) {
1971         /* Get TMCC info*/
1972         rc = mb86a20s_get_frontend(fe);
1973         if (rc < 0) {
1974             dev_err(&state->i2c->dev,
1975                 "%s: Can't get FE TMCC data.\n", __func__);
1976             rc = 0;     /* Status is OK */
1977             goto error;
1978         }
1979 
1980         /* Get statistics */
1981         rc = mb86a20s_get_stats(fe, status_nr);
1982         if (rc < 0 && rc != -EBUSY) {
1983             dev_err(&state->i2c->dev,
1984                 "%s: Can't get FE statistics.\n", __func__);
1985             rc = 0;
1986             goto error;
1987         }
1988         rc = 0; /* Don't return EBUSY to userspace */
1989     }
1990     goto ok;
1991 
1992 error:
1993     mb86a20s_stats_not_ready(fe);
1994 
1995 ok:
1996     if (fe->ops.i2c_gate_ctrl)
1997         fe->ops.i2c_gate_ctrl(fe, 1);
1998 
1999     return rc;
2000 }
2001 
2002 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
2003                             u16 *strength)
2004 {
2005     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2006 
2007 
2008     *strength = c->strength.stat[0].uvalue;
2009 
2010     return 0;
2011 }
2012 
2013 static int mb86a20s_tune(struct dvb_frontend *fe,
2014             bool re_tune,
2015             unsigned int mode_flags,
2016             unsigned int *delay,
2017             enum fe_status *status)
2018 {
2019     struct mb86a20s_state *state = fe->demodulator_priv;
2020     int rc = 0;
2021 
2022     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2023 
2024     if (re_tune)
2025         rc = mb86a20s_set_frontend(fe);
2026 
2027     if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
2028         mb86a20s_read_status_and_stats(fe, status);
2029 
2030     return rc;
2031 }
2032 
2033 static void mb86a20s_release(struct dvb_frontend *fe)
2034 {
2035     struct mb86a20s_state *state = fe->demodulator_priv;
2036 
2037     dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2038 
2039     kfree(state);
2040 }
2041 
2042 static enum dvbfe_algo mb86a20s_get_frontend_algo(struct dvb_frontend *fe)
2043 {
2044     return DVBFE_ALGO_HW;
2045 }
2046 
2047 static const struct dvb_frontend_ops mb86a20s_ops;
2048 
2049 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
2050                     struct i2c_adapter *i2c)
2051 {
2052     struct mb86a20s_state *state;
2053     u8  rev;
2054 
2055     dev_dbg(&i2c->dev, "%s called.\n", __func__);
2056 
2057     /* allocate memory for the internal state */
2058     state = kzalloc(sizeof(*state), GFP_KERNEL);
2059     if (!state)
2060         return NULL;
2061 
2062     /* setup the state */
2063     state->config = config;
2064     state->i2c = i2c;
2065 
2066     /* create dvb_frontend */
2067     memcpy(&state->frontend.ops, &mb86a20s_ops,
2068         sizeof(struct dvb_frontend_ops));
2069     state->frontend.demodulator_priv = state;
2070 
2071     /* Check if it is a mb86a20s frontend */
2072     rev = mb86a20s_readreg(state, 0);
2073     if (rev != 0x13) {
2074         kfree(state);
2075         dev_dbg(&i2c->dev,
2076             "Frontend revision %d is unknown - aborting.\n",
2077                rev);
2078         return NULL;
2079     }
2080 
2081     dev_info(&i2c->dev, "Detected a Fujitsu mb86a20s frontend\n");
2082     return &state->frontend;
2083 }
2084 EXPORT_SYMBOL(mb86a20s_attach);
2085 
2086 static const struct dvb_frontend_ops mb86a20s_ops = {
2087     .delsys = { SYS_ISDBT },
2088     /* Use dib8000 values per default */
2089     .info = {
2090         .name = "Fujitsu mb86A20s",
2091         .caps = FE_CAN_RECOVER  |
2092             FE_CAN_FEC_1_2  | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2093             FE_CAN_FEC_5_6  | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2094             FE_CAN_QPSK     | FE_CAN_QAM_16  | FE_CAN_QAM_64 |
2095             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2096             FE_CAN_GUARD_INTERVAL_AUTO    | FE_CAN_HIERARCHY_AUTO,
2097         /* Actually, those values depend on the used tuner */
2098         .frequency_min_hz =  45 * MHz,
2099         .frequency_max_hz = 864 * MHz,
2100         .frequency_stepsize_hz = 62500,
2101     },
2102 
2103     .release = mb86a20s_release,
2104 
2105     .init = mb86a20s_initfe,
2106     .set_frontend = mb86a20s_set_frontend,
2107     .read_status = mb86a20s_read_status_and_stats,
2108     .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
2109     .tune = mb86a20s_tune,
2110     .get_frontend_algo = mb86a20s_get_frontend_algo,
2111 };
2112 
2113 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2114 MODULE_AUTHOR("Mauro Carvalho Chehab");
2115 MODULE_LICENSE("GPL");
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