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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003     Driver for M88RS2000 demodulator and tuner
0004 
0005     Copyright (C) 2012 Malcolm Priestley (tvboxspy@gmail.com)
0006     Beta Driver
0007 
0008     Include various calculation code from DS3000 driver.
0009     Copyright (C) 2009 Konstantin Dimitrov.
0010 
0011 
0012 */
0013 #include <linux/init.h>
0014 #include <linux/module.h>
0015 #include <linux/device.h>
0016 #include <linux/jiffies.h>
0017 #include <linux/string.h>
0018 #include <linux/slab.h>
0019 #include <linux/types.h>
0020 
0021 
0022 #include <media/dvb_frontend.h>
0023 #include "m88rs2000.h"
0024 
0025 struct m88rs2000_state {
0026     struct i2c_adapter *i2c;
0027     const struct m88rs2000_config *config;
0028     struct dvb_frontend frontend;
0029     u8 no_lock_count;
0030     u32 tuner_frequency;
0031     u32 symbol_rate;
0032     enum fe_code_rate fec_inner;
0033     u8 tuner_level;
0034     int errmode;
0035 };
0036 
0037 static int m88rs2000_debug;
0038 
0039 module_param_named(debug, m88rs2000_debug, int, 0644);
0040 MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
0041 
0042 #define dprintk(level, args...) do { \
0043     if (level & m88rs2000_debug) \
0044         printk(KERN_DEBUG "m88rs2000-fe: " args); \
0045 } while (0)
0046 
0047 #define deb_info(args...)  dprintk(0x01, args)
0048 #define info(format, arg...) \
0049     printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg)
0050 
0051 static int m88rs2000_writereg(struct m88rs2000_state *state,
0052     u8 reg, u8 data)
0053 {
0054     int ret;
0055     u8 buf[] = { reg, data };
0056     struct i2c_msg msg = {
0057         .addr = state->config->demod_addr,
0058         .flags = 0,
0059         .buf = buf,
0060         .len = 2
0061     };
0062 
0063     ret = i2c_transfer(state->i2c, &msg, 1);
0064 
0065     if (ret != 1)
0066         deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
0067              __func__, reg, data, ret);
0068 
0069     return (ret != 1) ? -EREMOTEIO : 0;
0070 }
0071 
0072 static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg)
0073 {
0074     int ret;
0075     u8 b0[] = { reg };
0076     u8 b1[] = { 0 };
0077 
0078     struct i2c_msg msg[] = {
0079         {
0080             .addr = state->config->demod_addr,
0081             .flags = 0,
0082             .buf = b0,
0083             .len = 1
0084         }, {
0085             .addr = state->config->demod_addr,
0086             .flags = I2C_M_RD,
0087             .buf = b1,
0088             .len = 1
0089         }
0090     };
0091 
0092     ret = i2c_transfer(state->i2c, msg, 2);
0093 
0094     if (ret != 2)
0095         deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n",
0096                 __func__, reg, ret);
0097 
0098     return b1[0];
0099 }
0100 
0101 static u32 m88rs2000_get_mclk(struct dvb_frontend *fe)
0102 {
0103     struct m88rs2000_state *state = fe->demodulator_priv;
0104     u32 mclk;
0105     u8 reg;
0106     /* Must not be 0x00 or 0xff */
0107     reg = m88rs2000_readreg(state, 0x86);
0108     if (!reg || reg == 0xff)
0109         return 0;
0110 
0111     reg /= 2;
0112     reg += 1;
0113 
0114     mclk = (u32)(reg * RS2000_FE_CRYSTAL_KHZ + 28 / 2) / 28;
0115 
0116     return mclk;
0117 }
0118 
0119 static int m88rs2000_set_carrieroffset(struct dvb_frontend *fe, s16 offset)
0120 {
0121     struct m88rs2000_state *state = fe->demodulator_priv;
0122     u32 mclk;
0123     s32 tmp;
0124     u8 reg;
0125     int ret;
0126 
0127     mclk = m88rs2000_get_mclk(fe);
0128     if (!mclk)
0129         return -EINVAL;
0130 
0131     tmp = (offset * 4096 + (s32)mclk / 2) / (s32)mclk;
0132     if (tmp < 0)
0133         tmp += 4096;
0134 
0135     /* Carrier Offset */
0136     ret = m88rs2000_writereg(state, 0x9c, (u8)(tmp >> 4));
0137 
0138     reg = m88rs2000_readreg(state, 0x9d);
0139     reg &= 0xf;
0140     reg |= (u8)(tmp & 0xf) << 4;
0141 
0142     ret |= m88rs2000_writereg(state, 0x9d, reg);
0143 
0144     return ret;
0145 }
0146 
0147 static int m88rs2000_set_symbolrate(struct dvb_frontend *fe, u32 srate)
0148 {
0149     struct m88rs2000_state *state = fe->demodulator_priv;
0150     int ret;
0151     u64 temp;
0152     u32 mclk;
0153     u8 b[3];
0154 
0155     if ((srate < 1000000) || (srate > 45000000))
0156         return -EINVAL;
0157 
0158     mclk = m88rs2000_get_mclk(fe);
0159     if (!mclk)
0160         return -EINVAL;
0161 
0162     temp = srate / 1000;
0163     temp *= 1 << 24;
0164 
0165     do_div(temp, mclk);
0166 
0167     b[0] = (u8) (temp >> 16) & 0xff;
0168     b[1] = (u8) (temp >> 8) & 0xff;
0169     b[2] = (u8) temp & 0xff;
0170 
0171     ret = m88rs2000_writereg(state, 0x93, b[2]);
0172     ret |= m88rs2000_writereg(state, 0x94, b[1]);
0173     ret |= m88rs2000_writereg(state, 0x95, b[0]);
0174 
0175     if (srate > 10000000)
0176         ret |= m88rs2000_writereg(state, 0xa0, 0x20);
0177     else
0178         ret |= m88rs2000_writereg(state, 0xa0, 0x60);
0179 
0180     ret |= m88rs2000_writereg(state, 0xa1, 0xe0);
0181 
0182     if (srate > 12000000)
0183         ret |= m88rs2000_writereg(state, 0xa3, 0x20);
0184     else if (srate > 2800000)
0185         ret |= m88rs2000_writereg(state, 0xa3, 0x98);
0186     else
0187         ret |= m88rs2000_writereg(state, 0xa3, 0x90);
0188 
0189     deb_info("m88rs2000: m88rs2000_set_symbolrate\n");
0190     return ret;
0191 }
0192 
0193 static int m88rs2000_send_diseqc_msg(struct dvb_frontend *fe,
0194                     struct dvb_diseqc_master_cmd *m)
0195 {
0196     struct m88rs2000_state *state = fe->demodulator_priv;
0197 
0198     int i;
0199     u8 reg;
0200     deb_info("%s\n", __func__);
0201     m88rs2000_writereg(state, 0x9a, 0x30);
0202     reg = m88rs2000_readreg(state, 0xb2);
0203     reg &= 0x3f;
0204     m88rs2000_writereg(state, 0xb2, reg);
0205     for (i = 0; i <  m->msg_len; i++)
0206         m88rs2000_writereg(state, 0xb3 + i, m->msg[i]);
0207 
0208     reg = m88rs2000_readreg(state, 0xb1);
0209     reg &= 0x87;
0210     reg |= ((m->msg_len - 1) << 3) | 0x07;
0211     reg &= 0x7f;
0212     m88rs2000_writereg(state, 0xb1, reg);
0213 
0214     for (i = 0; i < 15; i++) {
0215         if ((m88rs2000_readreg(state, 0xb1) & 0x40) == 0x0)
0216             break;
0217         msleep(20);
0218     }
0219 
0220     reg = m88rs2000_readreg(state, 0xb1);
0221     if ((reg & 0x40) > 0x0) {
0222         reg &= 0x7f;
0223         reg |= 0x40;
0224         m88rs2000_writereg(state, 0xb1, reg);
0225     }
0226 
0227     reg = m88rs2000_readreg(state, 0xb2);
0228     reg &= 0x3f;
0229     reg |= 0x80;
0230     m88rs2000_writereg(state, 0xb2, reg);
0231     m88rs2000_writereg(state, 0x9a, 0xb0);
0232 
0233 
0234     return 0;
0235 }
0236 
0237 static int m88rs2000_send_diseqc_burst(struct dvb_frontend *fe,
0238                        enum fe_sec_mini_cmd burst)
0239 {
0240     struct m88rs2000_state *state = fe->demodulator_priv;
0241     u8 reg0, reg1;
0242     deb_info("%s\n", __func__);
0243     m88rs2000_writereg(state, 0x9a, 0x30);
0244     msleep(50);
0245     reg0 = m88rs2000_readreg(state, 0xb1);
0246     reg1 = m88rs2000_readreg(state, 0xb2);
0247     /* TODO complete this section */
0248     m88rs2000_writereg(state, 0xb2, reg1);
0249     m88rs2000_writereg(state, 0xb1, reg0);
0250     m88rs2000_writereg(state, 0x9a, 0xb0);
0251 
0252     return 0;
0253 }
0254 
0255 static int m88rs2000_set_tone(struct dvb_frontend *fe,
0256                   enum fe_sec_tone_mode tone)
0257 {
0258     struct m88rs2000_state *state = fe->demodulator_priv;
0259     u8 reg0, reg1;
0260     m88rs2000_writereg(state, 0x9a, 0x30);
0261     reg0 = m88rs2000_readreg(state, 0xb1);
0262     reg1 = m88rs2000_readreg(state, 0xb2);
0263 
0264     reg1 &= 0x3f;
0265 
0266     switch (tone) {
0267     case SEC_TONE_ON:
0268         reg0 |= 0x4;
0269         reg0 &= 0xbc;
0270         break;
0271     case SEC_TONE_OFF:
0272         reg1 |= 0x80;
0273         break;
0274     default:
0275         break;
0276     }
0277     m88rs2000_writereg(state, 0xb2, reg1);
0278     m88rs2000_writereg(state, 0xb1, reg0);
0279     m88rs2000_writereg(state, 0x9a, 0xb0);
0280     return 0;
0281 }
0282 
0283 struct inittab {
0284     u8 cmd;
0285     u8 reg;
0286     u8 val;
0287 };
0288 
0289 static struct inittab m88rs2000_setup[] = {
0290     {DEMOD_WRITE, 0x9a, 0x30},
0291     {DEMOD_WRITE, 0x00, 0x01},
0292     {WRITE_DELAY, 0x19, 0x00},
0293     {DEMOD_WRITE, 0x00, 0x00},
0294     {DEMOD_WRITE, 0x9a, 0xb0},
0295     {DEMOD_WRITE, 0x81, 0xc1},
0296     {DEMOD_WRITE, 0x81, 0x81},
0297     {DEMOD_WRITE, 0x86, 0xc6},
0298     {DEMOD_WRITE, 0x9a, 0x30},
0299     {DEMOD_WRITE, 0xf0, 0x22},
0300     {DEMOD_WRITE, 0xf1, 0xbf},
0301     {DEMOD_WRITE, 0xb0, 0x45},
0302     {DEMOD_WRITE, 0xb2, 0x01}, /* set voltage pin always set 1*/
0303     {DEMOD_WRITE, 0x9a, 0xb0},
0304     {0xff, 0xaa, 0xff}
0305 };
0306 
0307 static struct inittab m88rs2000_shutdown[] = {
0308     {DEMOD_WRITE, 0x9a, 0x30},
0309     {DEMOD_WRITE, 0xb0, 0x00},
0310     {DEMOD_WRITE, 0xf1, 0x89},
0311     {DEMOD_WRITE, 0x00, 0x01},
0312     {DEMOD_WRITE, 0x9a, 0xb0},
0313     {DEMOD_WRITE, 0x81, 0x81},
0314     {0xff, 0xaa, 0xff}
0315 };
0316 
0317 static struct inittab fe_reset[] = {
0318     {DEMOD_WRITE, 0x00, 0x01},
0319     {DEMOD_WRITE, 0x20, 0x81},
0320     {DEMOD_WRITE, 0x21, 0x80},
0321     {DEMOD_WRITE, 0x10, 0x33},
0322     {DEMOD_WRITE, 0x11, 0x44},
0323     {DEMOD_WRITE, 0x12, 0x07},
0324     {DEMOD_WRITE, 0x18, 0x20},
0325     {DEMOD_WRITE, 0x28, 0x04},
0326     {DEMOD_WRITE, 0x29, 0x8e},
0327     {DEMOD_WRITE, 0x3b, 0xff},
0328     {DEMOD_WRITE, 0x32, 0x10},
0329     {DEMOD_WRITE, 0x33, 0x02},
0330     {DEMOD_WRITE, 0x34, 0x30},
0331     {DEMOD_WRITE, 0x35, 0xff},
0332     {DEMOD_WRITE, 0x38, 0x50},
0333     {DEMOD_WRITE, 0x39, 0x68},
0334     {DEMOD_WRITE, 0x3c, 0x7f},
0335     {DEMOD_WRITE, 0x3d, 0x0f},
0336     {DEMOD_WRITE, 0x45, 0x20},
0337     {DEMOD_WRITE, 0x46, 0x24},
0338     {DEMOD_WRITE, 0x47, 0x7c},
0339     {DEMOD_WRITE, 0x48, 0x16},
0340     {DEMOD_WRITE, 0x49, 0x04},
0341     {DEMOD_WRITE, 0x4a, 0x01},
0342     {DEMOD_WRITE, 0x4b, 0x78},
0343     {DEMOD_WRITE, 0X4d, 0xd2},
0344     {DEMOD_WRITE, 0x4e, 0x6d},
0345     {DEMOD_WRITE, 0x50, 0x30},
0346     {DEMOD_WRITE, 0x51, 0x30},
0347     {DEMOD_WRITE, 0x54, 0x7b},
0348     {DEMOD_WRITE, 0x56, 0x09},
0349     {DEMOD_WRITE, 0x58, 0x59},
0350     {DEMOD_WRITE, 0x59, 0x37},
0351     {DEMOD_WRITE, 0x63, 0xfa},
0352     {0xff, 0xaa, 0xff}
0353 };
0354 
0355 static struct inittab fe_trigger[] = {
0356     {DEMOD_WRITE, 0x97, 0x04},
0357     {DEMOD_WRITE, 0x99, 0x77},
0358     {DEMOD_WRITE, 0x9b, 0x64},
0359     {DEMOD_WRITE, 0x9e, 0x00},
0360     {DEMOD_WRITE, 0x9f, 0xf8},
0361     {DEMOD_WRITE, 0x98, 0xff},
0362     {DEMOD_WRITE, 0xc0, 0x0f},
0363     {DEMOD_WRITE, 0x89, 0x01},
0364     {DEMOD_WRITE, 0x00, 0x00},
0365     {WRITE_DELAY, 0x0a, 0x00},
0366     {DEMOD_WRITE, 0x00, 0x01},
0367     {DEMOD_WRITE, 0x00, 0x00},
0368     {DEMOD_WRITE, 0x9a, 0xb0},
0369     {0xff, 0xaa, 0xff}
0370 };
0371 
0372 static int m88rs2000_tab_set(struct m88rs2000_state *state,
0373         struct inittab *tab)
0374 {
0375     int ret = 0;
0376     u8 i;
0377     if (tab == NULL)
0378         return -EINVAL;
0379 
0380     for (i = 0; i < 255; i++) {
0381         switch (tab[i].cmd) {
0382         case 0x01:
0383             ret = m88rs2000_writereg(state, tab[i].reg,
0384                 tab[i].val);
0385             break;
0386         case 0x10:
0387             if (tab[i].reg > 0)
0388                 mdelay(tab[i].reg);
0389             break;
0390         case 0xff:
0391             if (tab[i].reg == 0xaa && tab[i].val == 0xff)
0392                 return 0;
0393             break;
0394         case 0x00:
0395             break;
0396         default:
0397             return -EINVAL;
0398         }
0399         if (ret < 0)
0400             return -ENODEV;
0401     }
0402     return 0;
0403 }
0404 
0405 static int m88rs2000_set_voltage(struct dvb_frontend *fe,
0406                  enum fe_sec_voltage volt)
0407 {
0408     struct m88rs2000_state *state = fe->demodulator_priv;
0409     u8 data;
0410 
0411     data = m88rs2000_readreg(state, 0xb2);
0412     data |= 0x03; /* bit0 V/H, bit1 off/on */
0413 
0414     switch (volt) {
0415     case SEC_VOLTAGE_18:
0416         data &= ~0x03;
0417         break;
0418     case SEC_VOLTAGE_13:
0419         data &= ~0x03;
0420         data |= 0x01;
0421         break;
0422     case SEC_VOLTAGE_OFF:
0423         break;
0424     }
0425 
0426     m88rs2000_writereg(state, 0xb2, data);
0427 
0428     return 0;
0429 }
0430 
0431 static int m88rs2000_init(struct dvb_frontend *fe)
0432 {
0433     struct m88rs2000_state *state = fe->demodulator_priv;
0434     int ret;
0435 
0436     deb_info("m88rs2000: init chip\n");
0437     /* Setup frontend from shutdown/cold */
0438     if (state->config->inittab)
0439         ret = m88rs2000_tab_set(state,
0440                 (struct inittab *)state->config->inittab);
0441     else
0442         ret = m88rs2000_tab_set(state, m88rs2000_setup);
0443 
0444     return ret;
0445 }
0446 
0447 static int m88rs2000_sleep(struct dvb_frontend *fe)
0448 {
0449     struct m88rs2000_state *state = fe->demodulator_priv;
0450     int ret;
0451     /* Shutdown the frondend */
0452     ret = m88rs2000_tab_set(state, m88rs2000_shutdown);
0453     return ret;
0454 }
0455 
0456 static int m88rs2000_read_status(struct dvb_frontend *fe,
0457                  enum fe_status *status)
0458 {
0459     struct m88rs2000_state *state = fe->demodulator_priv;
0460     u8 reg = m88rs2000_readreg(state, 0x8c);
0461 
0462     *status = 0;
0463 
0464     if ((reg & 0xee) == 0xee) {
0465         *status = FE_HAS_CARRIER | FE_HAS_SIGNAL | FE_HAS_VITERBI
0466             | FE_HAS_SYNC | FE_HAS_LOCK;
0467         if (state->config->set_ts_params)
0468             state->config->set_ts_params(fe, CALL_IS_READ);
0469     }
0470     return 0;
0471 }
0472 
0473 static int m88rs2000_read_ber(struct dvb_frontend *fe, u32 *ber)
0474 {
0475     struct m88rs2000_state *state = fe->demodulator_priv;
0476     u8 tmp0, tmp1;
0477 
0478     m88rs2000_writereg(state, 0x9a, 0x30);
0479     tmp0 = m88rs2000_readreg(state, 0xd8);
0480     if ((tmp0 & 0x10) != 0) {
0481         m88rs2000_writereg(state, 0x9a, 0xb0);
0482         *ber = 0xffffffff;
0483         return 0;
0484     }
0485 
0486     *ber = (m88rs2000_readreg(state, 0xd7) << 8) |
0487         m88rs2000_readreg(state, 0xd6);
0488 
0489     tmp1 = m88rs2000_readreg(state, 0xd9);
0490     m88rs2000_writereg(state, 0xd9, (tmp1 & ~7) | 4);
0491     /* needs twice */
0492     m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
0493     m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);
0494     m88rs2000_writereg(state, 0x9a, 0xb0);
0495 
0496     return 0;
0497 }
0498 
0499 static int m88rs2000_read_signal_strength(struct dvb_frontend *fe,
0500     u16 *strength)
0501 {
0502     if (fe->ops.tuner_ops.get_rf_strength)
0503         fe->ops.tuner_ops.get_rf_strength(fe, strength);
0504 
0505     return 0;
0506 }
0507 
0508 static int m88rs2000_read_snr(struct dvb_frontend *fe, u16 *snr)
0509 {
0510     struct m88rs2000_state *state = fe->demodulator_priv;
0511 
0512     *snr = 512 * m88rs2000_readreg(state, 0x65);
0513 
0514     return 0;
0515 }
0516 
0517 static int m88rs2000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
0518 {
0519     struct m88rs2000_state *state = fe->demodulator_priv;
0520     u8 tmp;
0521 
0522     *ucblocks = (m88rs2000_readreg(state, 0xd5) << 8) |
0523             m88rs2000_readreg(state, 0xd4);
0524     tmp = m88rs2000_readreg(state, 0xd8);
0525     m88rs2000_writereg(state, 0xd8, tmp & ~0x20);
0526     /* needs two times */
0527     m88rs2000_writereg(state, 0xd8, tmp | 0x20);
0528     m88rs2000_writereg(state, 0xd8, tmp | 0x20);
0529 
0530     return 0;
0531 }
0532 
0533 static int m88rs2000_set_fec(struct m88rs2000_state *state,
0534                  enum fe_code_rate fec)
0535 {
0536     u8 fec_set, reg;
0537     int ret;
0538 
0539     switch (fec) {
0540     case FEC_1_2:
0541         fec_set = 0x8;
0542         break;
0543     case FEC_2_3:
0544         fec_set = 0x10;
0545         break;
0546     case FEC_3_4:
0547         fec_set = 0x20;
0548         break;
0549     case FEC_5_6:
0550         fec_set = 0x40;
0551         break;
0552     case FEC_7_8:
0553         fec_set = 0x80;
0554         break;
0555     case FEC_AUTO:
0556     default:
0557         fec_set = 0x0;
0558     }
0559 
0560     reg = m88rs2000_readreg(state, 0x70);
0561     reg &= 0x7;
0562     ret = m88rs2000_writereg(state, 0x70, reg | fec_set);
0563 
0564     ret |= m88rs2000_writereg(state, 0x76, 0x8);
0565 
0566     return ret;
0567 }
0568 
0569 static enum fe_code_rate m88rs2000_get_fec(struct m88rs2000_state *state)
0570 {
0571     u8 reg;
0572     m88rs2000_writereg(state, 0x9a, 0x30);
0573     reg = m88rs2000_readreg(state, 0x76);
0574     m88rs2000_writereg(state, 0x9a, 0xb0);
0575 
0576     reg &= 0xf0;
0577     reg >>= 5;
0578 
0579     switch (reg) {
0580     case 0x4:
0581         return FEC_1_2;
0582     case 0x3:
0583         return FEC_2_3;
0584     case 0x2:
0585         return FEC_3_4;
0586     case 0x1:
0587         return FEC_5_6;
0588     case 0x0:
0589         return FEC_7_8;
0590     default:
0591         break;
0592     }
0593 
0594     return FEC_AUTO;
0595 }
0596 
0597 static int m88rs2000_set_frontend(struct dvb_frontend *fe)
0598 {
0599     struct m88rs2000_state *state = fe->demodulator_priv;
0600     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0601     enum fe_status status = 0;
0602     int i, ret = 0;
0603     u32 tuner_freq;
0604     s16 offset = 0;
0605     u8 reg;
0606 
0607     state->no_lock_count = 0;
0608 
0609     if (c->delivery_system != SYS_DVBS) {
0610         deb_info("%s: unsupported delivery system selected (%d)\n",
0611              __func__, c->delivery_system);
0612         return -EOPNOTSUPP;
0613     }
0614 
0615     /* Set Tuner */
0616     if (fe->ops.tuner_ops.set_params)
0617         ret = fe->ops.tuner_ops.set_params(fe);
0618 
0619     if (ret < 0)
0620         return -ENODEV;
0621 
0622     if (fe->ops.tuner_ops.get_frequency) {
0623         ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_freq);
0624 
0625         if (ret < 0)
0626             return -ENODEV;
0627 
0628         offset = (s16)((s32)tuner_freq - c->frequency);
0629     } else {
0630         offset = 0;
0631     }
0632 
0633     /* default mclk value 96.4285 * 2 * 1000 = 192857 */
0634     if (((c->frequency % 192857) >= (192857 - 3000)) ||
0635                 (c->frequency % 192857) <= 3000)
0636         ret = m88rs2000_writereg(state, 0x86, 0xc2);
0637     else
0638         ret = m88rs2000_writereg(state, 0x86, 0xc6);
0639 
0640     ret |= m88rs2000_set_carrieroffset(fe, offset);
0641     if (ret < 0)
0642         return -ENODEV;
0643 
0644     /* Reset demod by symbol rate */
0645     if (c->symbol_rate > 27500000)
0646         ret = m88rs2000_writereg(state, 0xf1, 0xa4);
0647     else
0648         ret = m88rs2000_writereg(state, 0xf1, 0xbf);
0649 
0650     ret |= m88rs2000_tab_set(state, fe_reset);
0651     if (ret < 0)
0652         return -ENODEV;
0653 
0654     /* Set FEC */
0655     ret = m88rs2000_set_fec(state, c->fec_inner);
0656     ret |= m88rs2000_writereg(state, 0x85, 0x1);
0657     ret |= m88rs2000_writereg(state, 0x8a, 0xbf);
0658     ret |= m88rs2000_writereg(state, 0x8d, 0x1e);
0659     ret |= m88rs2000_writereg(state, 0x90, 0xf1);
0660     ret |= m88rs2000_writereg(state, 0x91, 0x08);
0661 
0662     if (ret < 0)
0663         return -ENODEV;
0664 
0665     /* Set Symbol Rate */
0666     ret = m88rs2000_set_symbolrate(fe, c->symbol_rate);
0667     if (ret < 0)
0668         return -ENODEV;
0669 
0670     /* Set up Demod */
0671     ret = m88rs2000_tab_set(state, fe_trigger);
0672     if (ret < 0)
0673         return -ENODEV;
0674 
0675     for (i = 0; i < 25; i++) {
0676         reg = m88rs2000_readreg(state, 0x8c);
0677         if ((reg & 0xee) == 0xee) {
0678             status = FE_HAS_LOCK;
0679             break;
0680         }
0681         state->no_lock_count++;
0682         if (state->no_lock_count == 15) {
0683             reg = m88rs2000_readreg(state, 0x70);
0684             reg ^= 0x4;
0685             m88rs2000_writereg(state, 0x70, reg);
0686             state->no_lock_count = 0;
0687         }
0688         msleep(20);
0689     }
0690 
0691     if (status & FE_HAS_LOCK) {
0692         state->fec_inner = m88rs2000_get_fec(state);
0693         /* Unknown suspect SNR level */
0694         reg = m88rs2000_readreg(state, 0x65);
0695     }
0696 
0697     state->tuner_frequency = c->frequency;
0698     state->symbol_rate = c->symbol_rate;
0699     return 0;
0700 }
0701 
0702 static int m88rs2000_get_frontend(struct dvb_frontend *fe,
0703                   struct dtv_frontend_properties *c)
0704 {
0705     struct m88rs2000_state *state = fe->demodulator_priv;
0706 
0707     c->fec_inner = state->fec_inner;
0708     c->frequency = state->tuner_frequency;
0709     c->symbol_rate = state->symbol_rate;
0710     return 0;
0711 }
0712 
0713 static int m88rs2000_get_tune_settings(struct dvb_frontend *fe,
0714     struct dvb_frontend_tune_settings *tune)
0715 {
0716     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0717 
0718     if (c->symbol_rate > 3000000)
0719         tune->min_delay_ms = 2000;
0720     else
0721         tune->min_delay_ms = 3000;
0722 
0723     tune->step_size = c->symbol_rate / 16000;
0724     tune->max_drift = c->symbol_rate / 2000;
0725 
0726     return 0;
0727 }
0728 
0729 static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
0730 {
0731     struct m88rs2000_state *state = fe->demodulator_priv;
0732 
0733     if (enable)
0734         m88rs2000_writereg(state, 0x81, 0x84);
0735     else
0736         m88rs2000_writereg(state, 0x81, 0x81);
0737     udelay(10);
0738     return 0;
0739 }
0740 
0741 static void m88rs2000_release(struct dvb_frontend *fe)
0742 {
0743     struct m88rs2000_state *state = fe->demodulator_priv;
0744     kfree(state);
0745 }
0746 
0747 static const struct dvb_frontend_ops m88rs2000_ops = {
0748     .delsys = { SYS_DVBS },
0749     .info = {
0750         .name           = "M88RS2000 DVB-S",
0751         .frequency_min_hz   =  950 * MHz,
0752         .frequency_max_hz   = 2150 * MHz,
0753         .frequency_stepsize_hz  = 1 * MHz,
0754         .frequency_tolerance_hz = 5 * MHz,
0755         .symbol_rate_min    = 1000000,
0756         .symbol_rate_max    = 45000000,
0757         .symbol_rate_tolerance  = 500,  /* ppm */
0758         .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
0759               FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
0760               FE_CAN_QPSK | FE_CAN_INVERSION_AUTO |
0761               FE_CAN_FEC_AUTO
0762     },
0763 
0764     .release = m88rs2000_release,
0765     .init = m88rs2000_init,
0766     .sleep = m88rs2000_sleep,
0767     .i2c_gate_ctrl = m88rs2000_i2c_gate_ctrl,
0768     .read_status = m88rs2000_read_status,
0769     .read_ber = m88rs2000_read_ber,
0770     .read_signal_strength = m88rs2000_read_signal_strength,
0771     .read_snr = m88rs2000_read_snr,
0772     .read_ucblocks = m88rs2000_read_ucblocks,
0773     .diseqc_send_master_cmd = m88rs2000_send_diseqc_msg,
0774     .diseqc_send_burst = m88rs2000_send_diseqc_burst,
0775     .set_tone = m88rs2000_set_tone,
0776     .set_voltage = m88rs2000_set_voltage,
0777 
0778     .set_frontend = m88rs2000_set_frontend,
0779     .get_frontend = m88rs2000_get_frontend,
0780     .get_tune_settings = m88rs2000_get_tune_settings,
0781 };
0782 
0783 struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config,
0784                     struct i2c_adapter *i2c)
0785 {
0786     struct m88rs2000_state *state = NULL;
0787 
0788     /* allocate memory for the internal state */
0789     state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL);
0790     if (state == NULL)
0791         goto error;
0792 
0793     /* setup the state */
0794     state->config = config;
0795     state->i2c = i2c;
0796     state->tuner_frequency = 0;
0797     state->symbol_rate = 0;
0798     state->fec_inner = 0;
0799 
0800     /* create dvb_frontend */
0801     memcpy(&state->frontend.ops, &m88rs2000_ops,
0802             sizeof(struct dvb_frontend_ops));
0803     state->frontend.demodulator_priv = state;
0804     return &state->frontend;
0805 
0806 error:
0807     kfree(state);
0808 
0809     return NULL;
0810 }
0811 EXPORT_SYMBOL(m88rs2000_attach);
0812 
0813 MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver");
0814 MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
0815 MODULE_LICENSE("GPL");
0816 MODULE_VERSION("1.13");
0817
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