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OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *    Support for Legend Silicon GB20600 (a.k.a DMB-TH) demodulator
0004  *    LGS8913, LGS8GL5, LGS8G75
0005  *    experimental support LGS8G42, LGS8G52
0006  *
0007  *    Copyright (C) 2007-2009 David T.L. Wong <davidtlwong@gmail.com>
0008  *    Copyright (C) 2008 Sirius International (Hong Kong) Limited
0009  *    Timothy Lee <timothy.lee@siriushk.com> (for initial work on LGS8GL5)
0010  */
0011 
0012 #ifndef LGS8913_PRIV_H
0013 #define LGS8913_PRIV_H
0014 
0015 struct lgs8gxx_state {
0016     struct i2c_adapter *i2c;
0017     /* configuration settings */
0018     const struct lgs8gxx_config *config;
0019     struct dvb_frontend frontend;
0020     u16 curr_gi; /* current guard interval */
0021 };
0022 
0023 #define SC_MASK     0x1C    /* Sub-Carrier Modulation Mask */
0024 #define SC_QAM64    0x10    /* 64QAM modulation */
0025 #define SC_QAM32    0x0C    /* 32QAM modulation */
0026 #define SC_QAM16    0x08    /* 16QAM modulation */
0027 #define SC_QAM4NR   0x04    /* 4QAM-NR modulation */
0028 #define SC_QAM4     0x00    /* 4QAM modulation */
0029 
0030 #define LGS_FEC_MASK    0x03    /* FEC Rate Mask */
0031 #define LGS_FEC_0_4 0x00    /* FEC Rate 0.4 */
0032 #define LGS_FEC_0_6 0x01    /* FEC Rate 0.6 */
0033 #define LGS_FEC_0_8 0x02    /* FEC Rate 0.8 */
0034 
0035 #define TIM_MASK      0x20  /* Time Interleave Length Mask */
0036 #define TIM_LONG      0x20  /* Time Interleave Length = 720 */
0037 #define TIM_MIDDLE     0x00   /* Time Interleave Length = 240 */
0038 
0039 #define CF_MASK 0x80    /* Control Frame Mask */
0040 #define CF_EN   0x80    /* Control Frame On */
0041 
0042 #define GI_MASK 0x03    /* Guard Interval Mask */
0043 #define GI_420  0x00    /* 1/9 Guard Interval */
0044 #define GI_595  0x01    /* */
0045 #define GI_945  0x02    /* 1/4 Guard Interval */
0046 
0047 
0048 #define TS_PARALLEL 0x00    /* Parallel TS Output a.k.a. SPI */
0049 #define TS_SERIAL   0x01    /* Serial TS Output a.k.a. SSI */
0050 #define TS_CLK_NORMAL       0x00    /* MPEG Clock Normal */
0051 #define TS_CLK_INVERTED     0x02    /* MPEG Clock Inverted */
0052 #define TS_CLK_GATED        0x00    /* MPEG clock gated */
0053 #define TS_CLK_FREERUN      0x04    /* MPEG clock free running*/
0054 
0055 
0056 #endif