media/dvb-frontends/lgs8gl5.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003     Legend Silicon LGS-8GL5 DMB-TH OFDM demodulator driver
0004
0005     Copyright (C) 2008 Sirius International (Hong Kong) Limited
0006     Timothy Lee <timothy.lee@siriushk.com>
0007
0008
0009 */
0010
0011 #include <linux/kernel.h>
0012 #include <linux/init.h>
0013 #include <linux/module.h>
0014 #include <linux/string.h>
0015 #include <linux/slab.h>
0016 #include <media/dvb_frontend.h>
0017 #include "lgs8gl5.h"
0018
0019
0020 #define REG_RESET       0x02
0021 #define REG_RESET_OFF           0x01
0022 #define REG_03          0x03
0023 #define REG_04          0x04
0024 #define REG_07          0x07
0025 #define REG_09          0x09
0026 #define REG_0A          0x0a
0027 #define REG_0B          0x0b
0028 #define REG_0C          0x0c
0029 #define REG_37          0x37
0030 #define REG_STRENGTH        0x4b
0031 #define REG_STRENGTH_MASK       0x7f
0032 #define REG_STRENGTH_CARRIER        0x80
0033 #define REG_INVERSION       0x7c
0034 #define REG_INVERSION_ON        0x80
0035 #define REG_7D          0x7d
0036 #define REG_7E          0x7e
0037 #define REG_A2          0xa2
0038 #define REG_STATUS      0xa4
0039 #define REG_STATUS_SYNC     0x04
0040 #define REG_STATUS_LOCK     0x01
0041
0042
0043 struct lgs8gl5_state {
0044     struct i2c_adapter *i2c;
0045     const struct lgs8gl5_config *config;
0046     struct dvb_frontend frontend;
0047 };
0048
0049
0050 static int debug;
0051 #define dprintk(args...) \
0052     do { \
0053         if (debug) \
0054             printk(KERN_DEBUG "lgs8gl5: " args); \
0055     } while (0)
0056
0057
0058 /* Writes into demod's register */
0059 static int
0060 lgs8gl5_write_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
0061 {
0062     int ret;
0063     u8 buf[] = {reg, data};
0064     struct i2c_msg msg = {
0065         .addr  = state->config->demod_address,
0066         .flags = 0,
0067         .buf   = buf,
0068         .len   = 2
0069     };
0070
0071     ret = i2c_transfer(state->i2c, &msg, 1);
0072     if (ret != 1)
0073         dprintk("%s: error (reg=0x%02x, val=0x%02x, ret=%i)\n",
0074             __func__, reg, data, ret);
0075     return (ret != 1) ? -1 : 0;
0076 }
0077
0078
0079 /* Reads from demod's register */
0080 static int
0081 lgs8gl5_read_reg(struct lgs8gl5_state *state, u8 reg)
0082 {
0083     int ret;
0084     u8 b0[] = {reg};
0085     u8 b1[] = {0};
0086     struct i2c_msg msg[2] = {
0087         {
0088             .addr  = state->config->demod_address,
0089             .flags = 0,
0090             .buf   = b0,
0091             .len   = 1
0092         },
0093         {
0094             .addr  = state->config->demod_address,
0095             .flags = I2C_M_RD,
0096             .buf   = b1,
0097             .len   = 1
0098         }
0099     };
0100
0101     ret = i2c_transfer(state->i2c, msg, 2);
0102     if (ret != 2)
0103         return -EIO;
0104
0105     return b1[0];
0106 }
0107
0108
0109 static int
0110 lgs8gl5_update_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
0111 {
0112     lgs8gl5_read_reg(state, reg);
0113     lgs8gl5_write_reg(state, reg, data);
0114     return 0;
0115 }
0116
0117
0118 /* Writes into alternate device's register */
0119 /* TODO:  Find out what that device is for! */
0120 static int
0121 lgs8gl5_update_alt_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
0122 {
0123     int ret;
0124     u8 b0[] = {reg};
0125     u8 b1[] = {0};
0126     u8 b2[] = {reg, data};
0127     struct i2c_msg msg[3] = {
0128         {
0129             .addr  = state->config->demod_address + 2,
0130             .flags = 0,
0131             .buf   = b0,
0132             .len   = 1
0133         },
0134         {
0135             .addr  = state->config->demod_address + 2,
0136             .flags = I2C_M_RD,
0137             .buf   = b1,
0138             .len   = 1
0139         },
0140         {
0141             .addr  = state->config->demod_address + 2,
0142             .flags = 0,
0143             .buf   = b2,
0144             .len   = 2
0145         },
0146     };
0147
0148     ret = i2c_transfer(state->i2c, msg, 3);
0149     return (ret != 3) ? -1 : 0;
0150 }
0151
0152
0153 static void
0154 lgs8gl5_soft_reset(struct lgs8gl5_state *state)
0155 {
0156     u8 val;
0157
0158     dprintk("%s\n", __func__);
0159
0160     val = lgs8gl5_read_reg(state, REG_RESET);
0161     lgs8gl5_write_reg(state, REG_RESET, val & ~REG_RESET_OFF);
0162     lgs8gl5_write_reg(state, REG_RESET, val | REG_RESET_OFF);
0163     msleep(5);
0164 }
0165
0166
0167 /* Starts demodulation */
0168 static void
0169 lgs8gl5_start_demod(struct lgs8gl5_state *state)
0170 {
0171     u8  val;
0172     int n;
0173
0174     dprintk("%s\n", __func__);
0175
0176     lgs8gl5_update_alt_reg(state, 0xc2, 0x28);
0177     lgs8gl5_soft_reset(state);
0178     lgs8gl5_update_reg(state, REG_07, 0x10);
0179     lgs8gl5_update_reg(state, REG_07, 0x10);
0180     lgs8gl5_write_reg(state, REG_09, 0x0e);
0181     lgs8gl5_write_reg(state, REG_0A, 0xe5);
0182     lgs8gl5_write_reg(state, REG_0B, 0x35);
0183     lgs8gl5_write_reg(state, REG_0C, 0x30);
0184
0185     lgs8gl5_update_reg(state, REG_03, 0x00);
0186     lgs8gl5_update_reg(state, REG_7E, 0x01);
0187     lgs8gl5_update_alt_reg(state, 0xc5, 0x00);
0188     lgs8gl5_update_reg(state, REG_04, 0x02);
0189     lgs8gl5_update_reg(state, REG_37, 0x01);
0190     lgs8gl5_soft_reset(state);
0191
0192     /* Wait for carrier */
0193     for (n = 0;  n < 10;  n++) {
0194         val = lgs8gl5_read_reg(state, REG_STRENGTH);
0195         dprintk("Wait for carrier[%d] 0x%02X\n", n, val);
0196         if (val & REG_STRENGTH_CARRIER)
0197             break;
0198         msleep(4);
0199     }
0200     if (!(val & REG_STRENGTH_CARRIER))
0201         return;
0202
0203     /* Wait for lock */
0204     for (n = 0;  n < 20;  n++) {
0205         val = lgs8gl5_read_reg(state, REG_STATUS);
0206         dprintk("Wait for lock[%d] 0x%02X\n", n, val);
0207         if (val & REG_STATUS_LOCK)
0208             break;
0209         msleep(12);
0210     }
0211     if (!(val & REG_STATUS_LOCK))
0212         return;
0213
0214     lgs8gl5_write_reg(state, REG_7D, lgs8gl5_read_reg(state, REG_A2));
0215     lgs8gl5_soft_reset(state);
0216 }
0217
0218
0219 static int
0220 lgs8gl5_init(struct dvb_frontend *fe)
0221 {
0222     struct lgs8gl5_state *state = fe->demodulator_priv;
0223
0224     dprintk("%s\n", __func__);
0225
0226     lgs8gl5_update_alt_reg(state, 0xc2, 0x28);
0227     lgs8gl5_soft_reset(state);
0228     lgs8gl5_update_reg(state, REG_07, 0x10);
0229     lgs8gl5_update_reg(state, REG_07, 0x10);
0230     lgs8gl5_write_reg(state, REG_09, 0x0e);
0231     lgs8gl5_write_reg(state, REG_0A, 0xe5);
0232     lgs8gl5_write_reg(state, REG_0B, 0x35);
0233     lgs8gl5_write_reg(state, REG_0C, 0x30);
0234
0235     return 0;
0236 }
0237
0238
0239 static int
0240 lgs8gl5_read_status(struct dvb_frontend *fe, enum fe_status *status)
0241 {
0242     struct lgs8gl5_state *state = fe->demodulator_priv;
0243     u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
0244     u8 flags = lgs8gl5_read_reg(state, REG_STATUS);
0245
0246     *status = 0;
0247
0248     if ((level & REG_STRENGTH_MASK) > 0)
0249         *status |= FE_HAS_SIGNAL;
0250     if (level & REG_STRENGTH_CARRIER)
0251         *status |= FE_HAS_CARRIER;
0252     if (flags & REG_STATUS_SYNC)
0253         *status |= FE_HAS_SYNC;
0254     if (flags & REG_STATUS_LOCK)
0255         *status |= FE_HAS_LOCK;
0256
0257     return 0;
0258 }
0259
0260
0261 static int
0262 lgs8gl5_read_ber(struct dvb_frontend *fe, u32 *ber)
0263 {
0264     *ber = 0;
0265
0266     return 0;
0267 }
0268
0269
0270 static int
0271 lgs8gl5_read_signal_strength(struct dvb_frontend *fe, u16 *signal_strength)
0272 {
0273     struct lgs8gl5_state *state = fe->demodulator_priv;
0274     u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
0275     *signal_strength = (level & REG_STRENGTH_MASK) << 8;
0276
0277     return 0;
0278 }
0279
0280
0281 static int
0282 lgs8gl5_read_snr(struct dvb_frontend *fe, u16 *snr)
0283 {
0284     struct lgs8gl5_state *state = fe->demodulator_priv;
0285     u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
0286     *snr = (level & REG_STRENGTH_MASK) << 8;
0287
0288     return 0;
0289 }
0290
0291
0292 static int
0293 lgs8gl5_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
0294 {
0295     *ucblocks = 0;
0296
0297     return 0;
0298 }
0299
0300
0301 static int
0302 lgs8gl5_set_frontend(struct dvb_frontend *fe)
0303 {
0304     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0305     struct lgs8gl5_state *state = fe->demodulator_priv;
0306
0307     dprintk("%s\n", __func__);
0308
0309     if (p->bandwidth_hz != 8000000)
0310         return -EINVAL;
0311
0312     if (fe->ops.tuner_ops.set_params) {
0313         fe->ops.tuner_ops.set_params(fe);
0314         if (fe->ops.i2c_gate_ctrl)
0315             fe->ops.i2c_gate_ctrl(fe, 0);
0316     }
0317
0318     /* lgs8gl5_set_inversion(state, p->inversion); */
0319
0320     lgs8gl5_start_demod(state);
0321
0322     return 0;
0323 }
0324
0325
0326 static int
0327 lgs8gl5_get_frontend(struct dvb_frontend *fe,
0328              struct dtv_frontend_properties *p)
0329 {
0330     struct lgs8gl5_state *state = fe->demodulator_priv;
0331
0332     u8 inv = lgs8gl5_read_reg(state, REG_INVERSION);
0333
0334     p->inversion = (inv & REG_INVERSION_ON) ? INVERSION_ON : INVERSION_OFF;
0335
0336     p->code_rate_HP = FEC_1_2;
0337     p->code_rate_LP = FEC_7_8;
0338     p->guard_interval = GUARD_INTERVAL_1_32;
0339     p->transmission_mode = TRANSMISSION_MODE_2K;
0340     p->modulation = QAM_64;
0341     p->hierarchy = HIERARCHY_NONE;
0342     p->bandwidth_hz = 8000000;
0343
0344     return 0;
0345 }
0346
0347
0348 static int
0349 lgs8gl5_get_tune_settings(struct dvb_frontend *fe,
0350         struct dvb_frontend_tune_settings *fesettings)
0351 {
0352     fesettings->min_delay_ms = 240;
0353     fesettings->step_size    = 0;
0354     fesettings->max_drift    = 0;
0355     return 0;
0356 }
0357
0358
0359 static void
0360 lgs8gl5_release(struct dvb_frontend *fe)
0361 {
0362     struct lgs8gl5_state *state = fe->demodulator_priv;
0363     kfree(state);
0364 }
0365
0366
0367 static const struct dvb_frontend_ops lgs8gl5_ops;
0368
0369
0370 struct dvb_frontend*
0371 lgs8gl5_attach(const struct lgs8gl5_config *config, struct i2c_adapter *i2c)
0372 {
0373     struct lgs8gl5_state *state = NULL;
0374
0375     dprintk("%s\n", __func__);
0376
0377     /* Allocate memory for the internal state */
0378     state = kzalloc(sizeof(struct lgs8gl5_state), GFP_KERNEL);
0379     if (state == NULL)
0380         goto error;
0381
0382     /* Setup the state */
0383     state->config = config;
0384     state->i2c    = i2c;
0385
0386     /* Check if the demod is there */
0387     if (lgs8gl5_read_reg(state, REG_RESET) < 0)
0388         goto error;
0389
0390     /* Create dvb_frontend */
0391     memcpy(&state->frontend.ops, &lgs8gl5_ops,
0392         sizeof(struct dvb_frontend_ops));
0393     state->frontend.demodulator_priv = state;
0394     return &state->frontend;
0395
0396 error:
0397     kfree(state);
0398     return NULL;
0399 }
0400 EXPORT_SYMBOL(lgs8gl5_attach);
0401
0402
0403 static const struct dvb_frontend_ops lgs8gl5_ops = {
0404     .delsys = { SYS_DTMB },
0405     .info = {
0406         .name           = "Legend Silicon LGS-8GL5 DMB-TH",
0407         .frequency_min_hz   = 474 * MHz,
0408         .frequency_max_hz   = 858 * MHz,
0409         .frequency_stepsize_hz  =  10 * kHz,
0410         .caps = FE_CAN_FEC_AUTO |
0411             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_32 |
0412             FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
0413             FE_CAN_TRANSMISSION_MODE_AUTO |
0414             FE_CAN_BANDWIDTH_AUTO |
0415             FE_CAN_GUARD_INTERVAL_AUTO |
0416             FE_CAN_HIERARCHY_AUTO |
0417             FE_CAN_RECOVER
0418     },
0419
0420     .release = lgs8gl5_release,
0421
0422     .init = lgs8gl5_init,
0423
0424     .set_frontend = lgs8gl5_set_frontend,
0425     .get_frontend = lgs8gl5_get_frontend,
0426     .get_tune_settings = lgs8gl5_get_tune_settings,
0427
0428     .read_status = lgs8gl5_read_status,
0429     .read_ber = lgs8gl5_read_ber,
0430     .read_signal_strength = lgs8gl5_read_signal_strength,
0431     .read_snr = lgs8gl5_read_snr,
0432     .read_ucblocks = lgs8gl5_read_ucblocks,
0433 };
0434
0435
0436 module_param(debug, int, 0644);
0437 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
0438
0439 MODULE_DESCRIPTION("Legend Silicon LGS-8GL5 DMB-TH Demodulator driver");
0440 MODULE_AUTHOR("Timothy Lee");
0441 MODULE_LICENSE("GPL");