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0008 #ifndef _LGDT330X_PRIV_
0009 #define _LGDT330X_PRIV_
0010
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0012 enum I2C_REG {
0013 TOP_CONTROL= 0x00,
0014 IRQ_MASK= 0x01,
0015 IRQ_STATUS= 0x02,
0016 VSB_CARRIER_FREQ0= 0x16,
0017 VSB_CARRIER_FREQ1= 0x17,
0018 VSB_CARRIER_FREQ2= 0x18,
0019 VSB_CARRIER_FREQ3= 0x19,
0020 CARRIER_MSEQAM1= 0x1a,
0021 CARRIER_MSEQAM2= 0x1b,
0022 CARRIER_LOCK= 0x1c,
0023 TIMING_RECOVERY= 0x1d,
0024 AGC_DELAY0= 0x2a,
0025 AGC_DELAY1= 0x2b,
0026 AGC_DELAY2= 0x2c,
0027 AGC_RF_BANDWIDTH0= 0x2d,
0028 AGC_RF_BANDWIDTH1= 0x2e,
0029 AGC_RF_BANDWIDTH2= 0x2f,
0030 AGC_LOOP_BANDWIDTH0= 0x30,
0031 AGC_LOOP_BANDWIDTH1= 0x31,
0032 AGC_FUNC_CTRL1= 0x32,
0033 AGC_FUNC_CTRL2= 0x33,
0034 AGC_FUNC_CTRL3= 0x34,
0035 AGC_RFIF_ACC0= 0x39,
0036 AGC_RFIF_ACC1= 0x3a,
0037 AGC_RFIF_ACC2= 0x3b,
0038 AGC_STATUS= 0x3f,
0039 SYNC_STATUS_VSB= 0x43,
0040 DEMUX_CONTROL= 0x66,
0041 LGDT3302_EQPH_ERR0= 0x47,
0042 LGDT3302_EQ_ERR1= 0x48,
0043 LGDT3302_EQ_ERR2= 0x49,
0044 LGDT3302_PH_ERR1= 0x4a,
0045 LGDT3302_PH_ERR2= 0x4b,
0046 LGDT3302_PACKET_ERR_COUNTER1= 0x6a,
0047 LGDT3302_PACKET_ERR_COUNTER2= 0x6b,
0048 LGDT3303_EQPH_ERR0= 0x6e,
0049 LGDT3303_EQ_ERR1= 0x6f,
0050 LGDT3303_EQ_ERR2= 0x70,
0051 LGDT3303_PH_ERR1= 0x71,
0052 LGDT3303_PH_ERR2= 0x72,
0053 LGDT3303_PACKET_ERR_COUNTER1= 0x8b,
0054 LGDT3303_PACKET_ERR_COUNTER2= 0x8c,
0055 };
0056
0057 #endif