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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *    Support for LGDT3306A - 8VSB/QAM-B
0004  *
0005  *    Copyright (C) 2013 Fred Richter <frichter@hauppauge.com>
0006  *    - driver structure based on lgdt3305.[ch] by Michael Krufky
0007  *    - code based on LG3306_V0.35 API by LG Electronics Inc.
0008  */
0009 
0010 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0011 
0012 #include <asm/div64.h>
0013 #include <linux/kernel.h>
0014 #include <linux/dvb/frontend.h>
0015 #include <media/dvb_math.h>
0016 #include "lgdt3306a.h"
0017 #include <linux/i2c-mux.h>
0018 
0019 
0020 static int debug;
0021 module_param(debug, int, 0644);
0022 MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
0023 
0024 /*
0025  * Older drivers treated QAM64 and QAM256 the same; that is the HW always
0026  * used "Auto" mode during detection.  Setting "forced_manual"=1 allows
0027  * the user to treat these modes as separate.  For backwards compatibility,
0028  * it's off by default.  QAM_AUTO can now be specified to achive that
0029  * effect even if "forced_manual"=1
0030  */
0031 static int forced_manual;
0032 module_param(forced_manual, int, 0644);
0033 MODULE_PARM_DESC(forced_manual, "if set, QAM64 and QAM256 will only lock to modulation specified");
0034 
0035 #define DBG_INFO 1
0036 #define DBG_REG  2
0037 #define DBG_DUMP 4 /* FGR - comment out to remove dump code */
0038 
0039 #define lg_debug(fmt, arg...) \
0040     printk(KERN_DEBUG pr_fmt(fmt), ## arg)
0041 
0042 #define dbg_info(fmt, arg...)                   \
0043     do {                            \
0044         if (debug & DBG_INFO)               \
0045             lg_debug(fmt, ## arg);          \
0046     } while (0)
0047 
0048 #define dbg_reg(fmt, arg...)                    \
0049     do {                            \
0050         if (debug & DBG_REG)                \
0051             lg_debug(fmt, ## arg);          \
0052     } while (0)
0053 
0054 #define lg_chkerr(ret)                          \
0055 ({                                  \
0056     int __ret;                          \
0057     __ret = (ret < 0);                      \
0058     if (__ret)                          \
0059         pr_err("error %d on line %d\n", ret, __LINE__);     \
0060     __ret;                              \
0061 })
0062 
0063 struct lgdt3306a_state {
0064     struct i2c_adapter *i2c_adap;
0065     const struct lgdt3306a_config *cfg;
0066 
0067     struct dvb_frontend frontend;
0068 
0069     enum fe_modulation current_modulation;
0070     u32 current_frequency;
0071     u32 snr;
0072 
0073     struct i2c_mux_core *muxc;
0074 };
0075 
0076 /*
0077  * LG3306A Register Usage
0078  *  (LG does not really name the registers, so this code does not either)
0079  *
0080  * 0000 -> 00FF Common control and status
0081  * 1000 -> 10FF Synchronizer control and status
0082  * 1F00 -> 1FFF Smart Antenna control and status
0083  * 2100 -> 21FF VSB Equalizer control and status
0084  * 2800 -> 28FF QAM Equalizer control and status
0085  * 3000 -> 30FF FEC control and status
0086  */
0087 
0088 enum lgdt3306a_lock_status {
0089     LG3306_UNLOCK       = 0x00,
0090     LG3306_LOCK         = 0x01,
0091     LG3306_UNKNOWN_LOCK = 0xff
0092 };
0093 
0094 enum lgdt3306a_neverlock_status {
0095     LG3306_NL_INIT    = 0x00,
0096     LG3306_NL_PROCESS = 0x01,
0097     LG3306_NL_LOCK    = 0x02,
0098     LG3306_NL_FAIL    = 0x03,
0099     LG3306_NL_UNKNOWN = 0xff
0100 };
0101 
0102 enum lgdt3306a_modulation {
0103     LG3306_VSB          = 0x00,
0104     LG3306_QAM64        = 0x01,
0105     LG3306_QAM256       = 0x02,
0106     LG3306_UNKNOWN_MODE = 0xff
0107 };
0108 
0109 enum lgdt3306a_lock_check {
0110     LG3306_SYNC_LOCK,
0111     LG3306_FEC_LOCK,
0112     LG3306_TR_LOCK,
0113     LG3306_AGC_LOCK,
0114 };
0115 
0116 
0117 #ifdef DBG_DUMP
0118 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
0119 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
0120 #endif
0121 
0122 
0123 static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
0124 {
0125     int ret;
0126     u8 buf[] = { reg >> 8, reg & 0xff, val };
0127     struct i2c_msg msg = {
0128         .addr = state->cfg->i2c_addr, .flags = 0,
0129         .buf = buf, .len = 3,
0130     };
0131 
0132     dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
0133 
0134     ret = i2c_transfer(state->i2c_adap, &msg, 1);
0135 
0136     if (ret != 1) {
0137         pr_err("error (addr %02x %02x <- %02x, err = %i)\n",
0138                msg.buf[0], msg.buf[1], msg.buf[2], ret);
0139         if (ret < 0)
0140             return ret;
0141         else
0142             return -EREMOTEIO;
0143     }
0144     return 0;
0145 }
0146 
0147 static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
0148 {
0149     int ret;
0150     u8 reg_buf[] = { reg >> 8, reg & 0xff };
0151     struct i2c_msg msg[] = {
0152         { .addr = state->cfg->i2c_addr,
0153           .flags = 0, .buf = reg_buf, .len = 2 },
0154         { .addr = state->cfg->i2c_addr,
0155           .flags = I2C_M_RD, .buf = val, .len = 1 },
0156     };
0157 
0158     ret = i2c_transfer(state->i2c_adap, msg, 2);
0159 
0160     if (ret != 2) {
0161         pr_err("error (addr %02x reg %04x error (ret == %i)\n",
0162                state->cfg->i2c_addr, reg, ret);
0163         if (ret < 0)
0164             return ret;
0165         else
0166             return -EREMOTEIO;
0167     }
0168     dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
0169 
0170     return 0;
0171 }
0172 
0173 #define read_reg(state, reg)                        \
0174 ({                                  \
0175     u8 __val;                           \
0176     int ret = lgdt3306a_read_reg(state, reg, &__val);       \
0177     if (lg_chkerr(ret))                     \
0178         __val = 0;                      \
0179     __val;                              \
0180 })
0181 
0182 static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
0183                 u16 reg, int bit, int onoff)
0184 {
0185     u8 val;
0186     int ret;
0187 
0188     dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
0189 
0190     ret = lgdt3306a_read_reg(state, reg, &val);
0191     if (lg_chkerr(ret))
0192         goto fail;
0193 
0194     val &= ~(1 << bit);
0195     val |= (onoff & 1) << bit;
0196 
0197     ret = lgdt3306a_write_reg(state, reg, val);
0198     lg_chkerr(ret);
0199 fail:
0200     return ret;
0201 }
0202 
0203 /* ------------------------------------------------------------------------ */
0204 
0205 static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
0206 {
0207     int ret;
0208 
0209     dbg_info("\n");
0210 
0211     ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
0212     if (lg_chkerr(ret))
0213         goto fail;
0214 
0215     msleep(20);
0216     ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
0217     lg_chkerr(ret);
0218 
0219 fail:
0220     return ret;
0221 }
0222 
0223 static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
0224                      enum lgdt3306a_mpeg_mode mode)
0225 {
0226     u8 val;
0227     int ret;
0228 
0229     dbg_info("(%d)\n", mode);
0230     /* transport packet format - TPSENB=0x80 */
0231     ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
0232                      mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0);
0233     if (lg_chkerr(ret))
0234         goto fail;
0235 
0236     /*
0237      * start of packet signal duration
0238      * TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration
0239      */
0240     ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
0241     if (lg_chkerr(ret))
0242         goto fail;
0243 
0244     ret = lgdt3306a_read_reg(state, 0x0070, &val);
0245     if (lg_chkerr(ret))
0246         goto fail;
0247 
0248     val |= 0x10; /* TPCLKSUPB=0x10 */
0249 
0250     if (mode == LGDT3306A_MPEG_PARALLEL)
0251         val &= ~0x10;
0252 
0253     ret = lgdt3306a_write_reg(state, 0x0070, val);
0254     lg_chkerr(ret);
0255 
0256 fail:
0257     return ret;
0258 }
0259 
0260 static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
0261                        enum lgdt3306a_tp_clock_edge edge,
0262                        enum lgdt3306a_tp_valid_polarity valid)
0263 {
0264     u8 val;
0265     int ret;
0266 
0267     dbg_info("edge=%d, valid=%d\n", edge, valid);
0268 
0269     ret = lgdt3306a_read_reg(state, 0x0070, &val);
0270     if (lg_chkerr(ret))
0271         goto fail;
0272 
0273     val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
0274 
0275     if (edge == LGDT3306A_TPCLK_RISING_EDGE)
0276         val |= 0x04;
0277     if (valid == LGDT3306A_TP_VALID_HIGH)
0278         val |= 0x02;
0279 
0280     ret = lgdt3306a_write_reg(state, 0x0070, val);
0281     lg_chkerr(ret);
0282 
0283 fail:
0284     return ret;
0285 }
0286 
0287 static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
0288                      int mode)
0289 {
0290     u8 val;
0291     int ret;
0292 
0293     dbg_info("(%d)\n", mode);
0294 
0295     if (mode) {
0296         ret = lgdt3306a_read_reg(state, 0x0070, &val);
0297         if (lg_chkerr(ret))
0298             goto fail;
0299         /*
0300          * Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20,
0301          * TPDATAOUTEN=0x08
0302          */
0303         val &= ~0xa8;
0304         ret = lgdt3306a_write_reg(state, 0x0070, val);
0305         if (lg_chkerr(ret))
0306             goto fail;
0307 
0308         /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
0309         ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
0310         if (lg_chkerr(ret))
0311             goto fail;
0312 
0313     } else {
0314         /* enable IFAGC pin */
0315         ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
0316         if (lg_chkerr(ret))
0317             goto fail;
0318 
0319         ret = lgdt3306a_read_reg(state, 0x0070, &val);
0320         if (lg_chkerr(ret))
0321             goto fail;
0322 
0323         val |= 0xa8; /* enable bus */
0324         ret = lgdt3306a_write_reg(state, 0x0070, val);
0325         if (lg_chkerr(ret))
0326             goto fail;
0327     }
0328 
0329 fail:
0330     return ret;
0331 }
0332 
0333 static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
0334 {
0335     struct lgdt3306a_state *state = fe->demodulator_priv;
0336 
0337     dbg_info("acquire=%d\n", acquire);
0338 
0339     return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
0340 
0341 }
0342 
0343 static int lgdt3306a_power(struct lgdt3306a_state *state,
0344                      int mode)
0345 {
0346     int ret;
0347 
0348     dbg_info("(%d)\n", mode);
0349 
0350     if (mode == 0) {
0351         /* into reset */
0352         ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
0353         if (lg_chkerr(ret))
0354             goto fail;
0355 
0356         /* power down */
0357         ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
0358         if (lg_chkerr(ret))
0359             goto fail;
0360 
0361     } else {
0362         /* out of reset */
0363         ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
0364         if (lg_chkerr(ret))
0365             goto fail;
0366 
0367         /* power up */
0368         ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
0369         if (lg_chkerr(ret))
0370             goto fail;
0371     }
0372 
0373 #ifdef DBG_DUMP
0374     lgdt3306a_DumpAllRegs(state);
0375 #endif
0376 fail:
0377     return ret;
0378 }
0379 
0380 
0381 static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
0382 {
0383     u8 val;
0384     int ret;
0385 
0386     dbg_info("\n");
0387 
0388     /* 0. Spectrum inversion detection manual; spectrum inverted */
0389     ret = lgdt3306a_read_reg(state, 0x0002, &val);
0390     val &= 0xf7; /* SPECINVAUTO Off */
0391     val |= 0x04; /* SPECINV On */
0392     ret = lgdt3306a_write_reg(state, 0x0002, val);
0393     if (lg_chkerr(ret))
0394         goto fail;
0395 
0396     /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
0397     ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
0398     if (lg_chkerr(ret))
0399         goto fail;
0400 
0401     /* 2. Bandwidth mode for VSB(6MHz) */
0402     ret = lgdt3306a_read_reg(state, 0x0009, &val);
0403     val &= 0xe3;
0404     val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
0405     ret = lgdt3306a_write_reg(state, 0x0009, val);
0406     if (lg_chkerr(ret))
0407         goto fail;
0408 
0409     /* 3. QAM mode detection mode(None) */
0410     ret = lgdt3306a_read_reg(state, 0x0009, &val);
0411     val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
0412     ret = lgdt3306a_write_reg(state, 0x0009, val);
0413     if (lg_chkerr(ret))
0414         goto fail;
0415 
0416     /* 4. ADC sampling frequency rate(2x sampling) */
0417     ret = lgdt3306a_read_reg(state, 0x000d, &val);
0418     val &= 0xbf; /* SAMPLING4XFEN=0 */
0419     ret = lgdt3306a_write_reg(state, 0x000d, val);
0420     if (lg_chkerr(ret))
0421         goto fail;
0422 
0423 #if 0
0424     /* FGR - disable any AICC filtering, testing only */
0425 
0426     ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
0427     if (lg_chkerr(ret))
0428         goto fail;
0429 
0430     /* AICCFIXFREQ0 NT N-1(Video rejection) */
0431     ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
0432     ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
0433     ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
0434 
0435     /* AICCFIXFREQ1 NT N-1(Audio rejection) */
0436     ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
0437     ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
0438     ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
0439 
0440     /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
0441     ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
0442     ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
0443     ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
0444 
0445     /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
0446     ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
0447     ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
0448     ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
0449 
0450 #else
0451     /* FGR - this works well for HVR-1955,1975 */
0452 
0453     /* 5. AICCOPMODE  NT N-1 Adj. */
0454     ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
0455     if (lg_chkerr(ret))
0456         goto fail;
0457 
0458     /* AICCFIXFREQ0 NT N-1(Video rejection) */
0459     ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
0460     ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
0461     ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
0462 
0463     /* AICCFIXFREQ1 NT N-1(Audio rejection) */
0464     ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
0465     ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
0466     ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
0467 
0468     /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
0469     ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
0470     ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
0471     ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
0472 
0473     /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
0474     ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
0475     ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
0476     ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
0477 #endif
0478 
0479     ret = lgdt3306a_read_reg(state, 0x001e, &val);
0480     val &= 0x0f;
0481     val |= 0xa0;
0482     ret = lgdt3306a_write_reg(state, 0x001e, val);
0483 
0484     ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
0485 
0486     ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
0487 
0488     ret = lgdt3306a_read_reg(state, 0x211f, &val);
0489     val &= 0xef;
0490     ret = lgdt3306a_write_reg(state, 0x211f, val);
0491 
0492     ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
0493 
0494     ret = lgdt3306a_read_reg(state, 0x1061, &val);
0495     val &= 0xf8;
0496     val |= 0x04;
0497     ret = lgdt3306a_write_reg(state, 0x1061, val);
0498 
0499     ret = lgdt3306a_read_reg(state, 0x103d, &val);
0500     val &= 0xcf;
0501     ret = lgdt3306a_write_reg(state, 0x103d, val);
0502 
0503     ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
0504 
0505     ret = lgdt3306a_read_reg(state, 0x2141, &val);
0506     val &= 0x3f;
0507     ret = lgdt3306a_write_reg(state, 0x2141, val);
0508 
0509     ret = lgdt3306a_read_reg(state, 0x2135, &val);
0510     val &= 0x0f;
0511     val |= 0x70;
0512     ret = lgdt3306a_write_reg(state, 0x2135, val);
0513 
0514     ret = lgdt3306a_read_reg(state, 0x0003, &val);
0515     val &= 0xf7;
0516     ret = lgdt3306a_write_reg(state, 0x0003, val);
0517 
0518     ret = lgdt3306a_read_reg(state, 0x001c, &val);
0519     val &= 0x7f;
0520     ret = lgdt3306a_write_reg(state, 0x001c, val);
0521 
0522     /* 6. EQ step size */
0523     ret = lgdt3306a_read_reg(state, 0x2179, &val);
0524     val &= 0xf8;
0525     ret = lgdt3306a_write_reg(state, 0x2179, val);
0526 
0527     ret = lgdt3306a_read_reg(state, 0x217a, &val);
0528     val &= 0xf8;
0529     ret = lgdt3306a_write_reg(state, 0x217a, val);
0530 
0531     /* 7. Reset */
0532     ret = lgdt3306a_soft_reset(state);
0533     if (lg_chkerr(ret))
0534         goto fail;
0535 
0536     dbg_info("complete\n");
0537 fail:
0538     return ret;
0539 }
0540 
0541 static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
0542 {
0543     u8 val;
0544     int ret;
0545 
0546     dbg_info("modulation=%d\n", modulation);
0547 
0548     /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
0549     ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
0550     if (lg_chkerr(ret))
0551         goto fail;
0552 
0553     /* 1a. Spectrum inversion detection to Auto */
0554     ret = lgdt3306a_read_reg(state, 0x0002, &val);
0555     val &= 0xfb; /* SPECINV Off */
0556     val |= 0x08; /* SPECINVAUTO On */
0557     ret = lgdt3306a_write_reg(state, 0x0002, val);
0558     if (lg_chkerr(ret))
0559         goto fail;
0560 
0561     /* 2. Bandwidth mode for QAM */
0562     ret = lgdt3306a_read_reg(state, 0x0009, &val);
0563     val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
0564     ret = lgdt3306a_write_reg(state, 0x0009, val);
0565     if (lg_chkerr(ret))
0566         goto fail;
0567 
0568     /* 3. : 64QAM/256QAM detection(manual, auto) */
0569     ret = lgdt3306a_read_reg(state, 0x0009, &val);
0570     val &= 0xfc;
0571     /* Check for forced Manual modulation modes; otherwise always "auto" */
0572     if(forced_manual && (modulation != QAM_AUTO)){
0573         val |= 0x01; /* STDOPDETCMODE[1:0]= 1=Manual */
0574     } else {
0575         val |= 0x02; /* STDOPDETCMODE[1:0]= 2=Auto */
0576     }
0577     ret = lgdt3306a_write_reg(state, 0x0009, val);
0578     if (lg_chkerr(ret))
0579         goto fail;
0580 
0581     /* 3a. : 64QAM/256QAM selection for manual */
0582     ret = lgdt3306a_read_reg(state, 0x101a, &val);
0583     val &= 0xf8;
0584     if (modulation == QAM_64)
0585         val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
0586     else
0587         val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
0588 
0589     ret = lgdt3306a_write_reg(state, 0x101a, val);
0590     if (lg_chkerr(ret))
0591         goto fail;
0592 
0593     /* 4. ADC sampling frequency rate(4x sampling) */
0594     ret = lgdt3306a_read_reg(state, 0x000d, &val);
0595     val &= 0xbf;
0596     val |= 0x40; /* SAMPLING4XFEN=1 */
0597     ret = lgdt3306a_write_reg(state, 0x000d, val);
0598     if (lg_chkerr(ret))
0599         goto fail;
0600 
0601     /* 5. No AICC operation in QAM mode */
0602     ret = lgdt3306a_read_reg(state, 0x0024, &val);
0603     val &= 0x00;
0604     ret = lgdt3306a_write_reg(state, 0x0024, val);
0605     if (lg_chkerr(ret))
0606         goto fail;
0607 
0608     /* 5.1 V0.36 SRDCHKALWAYS : For better QAM detection */
0609     ret = lgdt3306a_read_reg(state, 0x000a, &val);
0610     val &= 0xfd;
0611     val |= 0x02;
0612     ret = lgdt3306a_write_reg(state, 0x000a, val);
0613     if (lg_chkerr(ret))
0614         goto fail;
0615 
0616     /* 5.2 V0.36 Control of "no signal" detector function */
0617     ret = lgdt3306a_read_reg(state, 0x2849, &val);
0618     val &= 0xdf;
0619     ret = lgdt3306a_write_reg(state, 0x2849, val);
0620     if (lg_chkerr(ret))
0621         goto fail;
0622 
0623     /* 5.3 Fix for Blonder Tongue HDE-2H-QAM and AQM modulators */
0624     ret = lgdt3306a_read_reg(state, 0x302b, &val);
0625     val &= 0x7f;  /* SELFSYNCFINDEN_CQS=0; disable auto reset */
0626     ret = lgdt3306a_write_reg(state, 0x302b, val);
0627     if (lg_chkerr(ret))
0628         goto fail;
0629 
0630     /* 6. Reset */
0631     ret = lgdt3306a_soft_reset(state);
0632     if (lg_chkerr(ret))
0633         goto fail;
0634 
0635     dbg_info("complete\n");
0636 fail:
0637     return ret;
0638 }
0639 
0640 static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
0641                    struct dtv_frontend_properties *p)
0642 {
0643     int ret;
0644 
0645     dbg_info("\n");
0646 
0647     switch (p->modulation) {
0648     case VSB_8:
0649         ret = lgdt3306a_set_vsb(state);
0650         break;
0651     case QAM_64:
0652     case QAM_256:
0653     case QAM_AUTO:
0654         ret = lgdt3306a_set_qam(state, p->modulation);
0655         break;
0656     default:
0657         return -EINVAL;
0658     }
0659     if (lg_chkerr(ret))
0660         goto fail;
0661 
0662     state->current_modulation = p->modulation;
0663 
0664 fail:
0665     return ret;
0666 }
0667 
0668 /* ------------------------------------------------------------------------ */
0669 
0670 static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
0671                   struct dtv_frontend_properties *p)
0672 {
0673     /* TODO: anything we want to do here??? */
0674     dbg_info("\n");
0675 
0676     switch (p->modulation) {
0677     case VSB_8:
0678         break;
0679     case QAM_64:
0680     case QAM_256:
0681     case QAM_AUTO:
0682         break;
0683     default:
0684         return -EINVAL;
0685     }
0686     return 0;
0687 }
0688 
0689 /* ------------------------------------------------------------------------ */
0690 
0691 static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
0692                        int inversion)
0693 {
0694     int ret;
0695 
0696     dbg_info("(%d)\n", inversion);
0697 
0698     ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
0699     return ret;
0700 }
0701 
0702 static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
0703                        int enabled)
0704 {
0705     int ret;
0706 
0707     dbg_info("(%d)\n", enabled);
0708 
0709     /* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */
0710     ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
0711     return ret;
0712 }
0713 
0714 static int lgdt3306a_set_if(struct lgdt3306a_state *state,
0715                struct dtv_frontend_properties *p)
0716 {
0717     int ret;
0718     u16 if_freq_khz;
0719     u8 nco1, nco2;
0720 
0721     switch (p->modulation) {
0722     case VSB_8:
0723         if_freq_khz = state->cfg->vsb_if_khz;
0724         break;
0725     case QAM_64:
0726     case QAM_256:
0727     case QAM_AUTO:
0728         if_freq_khz = state->cfg->qam_if_khz;
0729         break;
0730     default:
0731         return -EINVAL;
0732     }
0733 
0734     switch (if_freq_khz) {
0735     default:
0736         pr_warn("IF=%d KHz is not supported, 3250 assumed\n",
0737             if_freq_khz);
0738         fallthrough;
0739     case 3250: /* 3.25Mhz */
0740         nco1 = 0x34;
0741         nco2 = 0x00;
0742         break;
0743     case 3500: /* 3.50Mhz */
0744         nco1 = 0x38;
0745         nco2 = 0x00;
0746         break;
0747     case 4000: /* 4.00Mhz */
0748         nco1 = 0x40;
0749         nco2 = 0x00;
0750         break;
0751     case 5000: /* 5.00Mhz */
0752         nco1 = 0x50;
0753         nco2 = 0x00;
0754         break;
0755     case 5380: /* 5.38Mhz */
0756         nco1 = 0x56;
0757         nco2 = 0x14;
0758         break;
0759     }
0760     ret = lgdt3306a_write_reg(state, 0x0010, nco1);
0761     if (ret)
0762         return ret;
0763     ret = lgdt3306a_write_reg(state, 0x0011, nco2);
0764     if (ret)
0765         return ret;
0766 
0767     dbg_info("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
0768 
0769     return 0;
0770 }
0771 
0772 /* ------------------------------------------------------------------------ */
0773 
0774 static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
0775 {
0776     struct lgdt3306a_state *state = fe->demodulator_priv;
0777 
0778     if (state->cfg->deny_i2c_rptr) {
0779         dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
0780         return 0;
0781     }
0782     dbg_info("(%d)\n", enable);
0783 
0784     /* NI2CRPTEN=0x80 */
0785     return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1);
0786 }
0787 
0788 static int lgdt3306a_sleep(struct lgdt3306a_state *state)
0789 {
0790     int ret;
0791 
0792     dbg_info("\n");
0793     state->current_frequency = -1; /* force re-tune, when we wake */
0794 
0795     ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
0796     if (lg_chkerr(ret))
0797         goto fail;
0798 
0799     ret = lgdt3306a_power(state, 0); /* power down */
0800     lg_chkerr(ret);
0801 
0802 fail:
0803     return 0;
0804 }
0805 
0806 static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
0807 {
0808     struct lgdt3306a_state *state = fe->demodulator_priv;
0809 
0810     return lgdt3306a_sleep(state);
0811 }
0812 
0813 static int lgdt3306a_init(struct dvb_frontend *fe)
0814 {
0815     struct lgdt3306a_state *state = fe->demodulator_priv;
0816     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0817     u8 val;
0818     int ret;
0819 
0820     dbg_info("\n");
0821 
0822     /* 1. Normal operation mode */
0823     ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
0824     if (lg_chkerr(ret))
0825         goto fail;
0826 
0827     /* 2. Spectrum inversion auto detection (Not valid for VSB) */
0828     ret = lgdt3306a_set_inversion_auto(state, 0);
0829     if (lg_chkerr(ret))
0830         goto fail;
0831 
0832     /* 3. Spectrum inversion(According to the tuner configuration) */
0833     ret = lgdt3306a_set_inversion(state, 1);
0834     if (lg_chkerr(ret))
0835         goto fail;
0836 
0837     /* 4. Peak-to-peak voltage of ADC input signal */
0838 
0839     /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
0840     ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
0841     if (lg_chkerr(ret))
0842         goto fail;
0843 
0844     /* 5. ADC output data capture clock phase */
0845 
0846     /* 0=same phase as ADC clock */
0847     ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
0848     if (lg_chkerr(ret))
0849         goto fail;
0850 
0851     /* 5a. ADC sampling clock source */
0852 
0853     /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
0854     ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
0855     if (lg_chkerr(ret))
0856         goto fail;
0857 
0858     /* 6. Automatic PLL set */
0859 
0860     /* PLLSETAUTO=0x40; 0=off */
0861     ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
0862     if (lg_chkerr(ret))
0863         goto fail;
0864 
0865     if (state->cfg->xtalMHz == 24) {    /* 24MHz */
0866         /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
0867         ret = lgdt3306a_read_reg(state, 0x0005, &val);
0868         if (lg_chkerr(ret))
0869             goto fail;
0870         val &= 0xc0;
0871         val |= 0x25;
0872         ret = lgdt3306a_write_reg(state, 0x0005, val);
0873         if (lg_chkerr(ret))
0874             goto fail;
0875         ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
0876         if (lg_chkerr(ret))
0877             goto fail;
0878 
0879         /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
0880         ret = lgdt3306a_read_reg(state, 0x000d, &val);
0881         if (lg_chkerr(ret))
0882             goto fail;
0883         val &= 0xc0;
0884         val |= 0x18;
0885         ret = lgdt3306a_write_reg(state, 0x000d, val);
0886         if (lg_chkerr(ret))
0887             goto fail;
0888 
0889     } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
0890         /* 7. Frequency for PLL output */
0891         ret = lgdt3306a_read_reg(state, 0x0005, &val);
0892         if (lg_chkerr(ret))
0893             goto fail;
0894         val &= 0xc0;
0895         val |= 0x25;
0896         ret = lgdt3306a_write_reg(state, 0x0005, val);
0897         if (lg_chkerr(ret))
0898             goto fail;
0899         ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
0900         if (lg_chkerr(ret))
0901             goto fail;
0902 
0903         /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
0904         ret = lgdt3306a_read_reg(state, 0x000d, &val);
0905         if (lg_chkerr(ret))
0906             goto fail;
0907         val &= 0xc0;
0908         val |= 0x19;
0909         ret = lgdt3306a_write_reg(state, 0x000d, val);
0910         if (lg_chkerr(ret))
0911             goto fail;
0912     } else {
0913         pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
0914     }
0915 #if 0
0916     ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
0917     ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
0918 #endif
0919 
0920     /* 9. Center frequency of input signal of ADC */
0921     ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
0922     ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
0923 
0924     /* 10. Fixed gain error value */
0925     ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
0926 
0927     /* 10a. VSB TR BW gear shift initial step */
0928     ret = lgdt3306a_read_reg(state, 0x103c, &val);
0929     val &= 0x0f;
0930     val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
0931     ret = lgdt3306a_write_reg(state, 0x103c, val);
0932 
0933     /* 10b. Timing offset calibration in low temperature for VSB */
0934     ret = lgdt3306a_read_reg(state, 0x103d, &val);
0935     val &= 0xfc;
0936     val |= 0x03;
0937     ret = lgdt3306a_write_reg(state, 0x103d, val);
0938 
0939     /* 10c. Timing offset calibration in low temperature for QAM */
0940     ret = lgdt3306a_read_reg(state, 0x1036, &val);
0941     val &= 0xf0;
0942     val |= 0x0c;
0943     ret = lgdt3306a_write_reg(state, 0x1036, val);
0944 
0945     /* 11. Using the imaginary part of CIR in CIR loading */
0946     ret = lgdt3306a_read_reg(state, 0x211f, &val);
0947     val &= 0xef; /* do not use imaginary of CIR */
0948     ret = lgdt3306a_write_reg(state, 0x211f, val);
0949 
0950     /* 12. Control of no signal detector function */
0951     ret = lgdt3306a_read_reg(state, 0x2849, &val);
0952     val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
0953     ret = lgdt3306a_write_reg(state, 0x2849, val);
0954 
0955     /* FGR - put demod in some known mode */
0956     ret = lgdt3306a_set_vsb(state);
0957 
0958     /* 13. TP stream format */
0959     ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
0960 
0961     /* 14. disable output buses */
0962     ret = lgdt3306a_mpeg_tristate(state, 1);
0963 
0964     /* 15. Sleep (in reset) */
0965     ret = lgdt3306a_sleep(state);
0966     lg_chkerr(ret);
0967 
0968     c->cnr.len = 1;
0969     c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0970 
0971 fail:
0972     return ret;
0973 }
0974 
0975 static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
0976 {
0977     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0978     struct lgdt3306a_state *state = fe->demodulator_priv;
0979     int ret;
0980 
0981     dbg_info("(%d, %d)\n", p->frequency, p->modulation);
0982 
0983     if (state->current_frequency  == p->frequency &&
0984        state->current_modulation == p->modulation) {
0985         dbg_info(" (already set, skipping ...)\n");
0986         return 0;
0987     }
0988     state->current_frequency = -1;
0989     state->current_modulation = -1;
0990 
0991     ret = lgdt3306a_power(state, 1); /* power up */
0992     if (lg_chkerr(ret))
0993         goto fail;
0994 
0995     if (fe->ops.tuner_ops.set_params) {
0996         ret = fe->ops.tuner_ops.set_params(fe);
0997         if (fe->ops.i2c_gate_ctrl)
0998             fe->ops.i2c_gate_ctrl(fe, 0);
0999 #if 0
1000         if (lg_chkerr(ret))
1001             goto fail;
1002         state->current_frequency = p->frequency;
1003 #endif
1004     }
1005 
1006     ret = lgdt3306a_set_modulation(state, p);
1007     if (lg_chkerr(ret))
1008         goto fail;
1009 
1010     ret = lgdt3306a_agc_setup(state, p);
1011     if (lg_chkerr(ret))
1012         goto fail;
1013 
1014     ret = lgdt3306a_set_if(state, p);
1015     if (lg_chkerr(ret))
1016         goto fail;
1017 
1018     /* spectral_inversion defaults already set for VSB and QAM */
1019 
1020     ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
1021     if (lg_chkerr(ret))
1022         goto fail;
1023 
1024     ret = lgdt3306a_mpeg_mode_polarity(state,
1025                       state->cfg->tpclk_edge,
1026                       state->cfg->tpvalid_polarity);
1027     if (lg_chkerr(ret))
1028         goto fail;
1029 
1030     ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
1031     if (lg_chkerr(ret))
1032         goto fail;
1033 
1034     ret = lgdt3306a_soft_reset(state);
1035     if (lg_chkerr(ret))
1036         goto fail;
1037 
1038 #ifdef DBG_DUMP
1039     lgdt3306a_DumpAllRegs(state);
1040 #endif
1041     state->current_frequency = p->frequency;
1042 fail:
1043     return ret;
1044 }
1045 
1046 static int lgdt3306a_get_frontend(struct dvb_frontend *fe,
1047                   struct dtv_frontend_properties *p)
1048 {
1049     struct lgdt3306a_state *state = fe->demodulator_priv;
1050 
1051     dbg_info("(%u, %d)\n",
1052          state->current_frequency, state->current_modulation);
1053 
1054     p->modulation = state->current_modulation;
1055     p->frequency = state->current_frequency;
1056     return 0;
1057 }
1058 
1059 static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
1060 {
1061 #if 1
1062     return DVBFE_ALGO_CUSTOM;
1063 #else
1064     return DVBFE_ALGO_HW;
1065 #endif
1066 }
1067 
1068 /* ------------------------------------------------------------------------ */
1069 static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
1070 {
1071     u8 val;
1072     int ret;
1073     u8 snrRef, maxPowerMan, nCombDet;
1074     u16 fbDlyCir;
1075 
1076     ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1077     if (ret)
1078         return ret;
1079     snrRef = val & 0x3f;
1080 
1081     ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
1082     if (ret)
1083         return ret;
1084 
1085     ret = lgdt3306a_read_reg(state, 0x2191, &val);
1086     if (ret)
1087         return ret;
1088     nCombDet = (val & 0x80) >> 7;
1089 
1090     ret = lgdt3306a_read_reg(state, 0x2180, &val);
1091     if (ret)
1092         return ret;
1093     fbDlyCir = (val & 0x03) << 8;
1094 
1095     ret = lgdt3306a_read_reg(state, 0x2181, &val);
1096     if (ret)
1097         return ret;
1098     fbDlyCir |= val;
1099 
1100     dbg_info("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
1101         snrRef, maxPowerMan, nCombDet, fbDlyCir);
1102 
1103     /* Carrier offset sub loop bandwidth */
1104     ret = lgdt3306a_read_reg(state, 0x1061, &val);
1105     if (ret)
1106         return ret;
1107     val &= 0xf8;
1108     if ((snrRef > 18) && (maxPowerMan > 0x68)
1109         && (nCombDet == 0x01)
1110         && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
1111         /* SNR is over 18dB and no ghosting */
1112         val |= 0x00; /* final bandwidth = 0 */
1113     } else {
1114         val |= 0x04; /* final bandwidth = 4 */
1115     }
1116     ret = lgdt3306a_write_reg(state, 0x1061, val);
1117     if (ret)
1118         return ret;
1119 
1120     /* Adjust Notch Filter */
1121     ret = lgdt3306a_read_reg(state, 0x0024, &val);
1122     if (ret)
1123         return ret;
1124     val &= 0x0f;
1125     if (nCombDet == 0) { /* Turn on the Notch Filter */
1126         val |= 0x50;
1127     }
1128     ret = lgdt3306a_write_reg(state, 0x0024, val);
1129     if (ret)
1130         return ret;
1131 
1132     /* VSB Timing Recovery output normalization */
1133     ret = lgdt3306a_read_reg(state, 0x103d, &val);
1134     if (ret)
1135         return ret;
1136     val &= 0xcf;
1137     val |= 0x20;
1138     ret = lgdt3306a_write_reg(state, 0x103d, val);
1139 
1140     return ret;
1141 }
1142 
1143 static enum lgdt3306a_modulation
1144 lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
1145 {
1146     u8 val = 0;
1147     int ret;
1148 
1149     ret = lgdt3306a_read_reg(state, 0x0081, &val);
1150     if (ret)
1151         goto err;
1152 
1153     if (val & 0x80) {
1154         dbg_info("VSB\n");
1155         return LG3306_VSB;
1156     }
1157     if (val & 0x08) {
1158         ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1159         if (ret)
1160             goto err;
1161         val = val >> 2;
1162         if (val & 0x01) {
1163             dbg_info("QAM256\n");
1164             return LG3306_QAM256;
1165         }
1166         dbg_info("QAM64\n");
1167         return LG3306_QAM64;
1168     }
1169 err:
1170     pr_warn("UNKNOWN\n");
1171     return LG3306_UNKNOWN_MODE;
1172 }
1173 
1174 static enum lgdt3306a_lock_status
1175 lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
1176                 enum lgdt3306a_lock_check whatLock)
1177 {
1178     u8 val = 0;
1179     int ret;
1180     enum lgdt3306a_modulation   modeOper;
1181     enum lgdt3306a_lock_status lockStatus;
1182 
1183     modeOper = LG3306_UNKNOWN_MODE;
1184 
1185     switch (whatLock) {
1186     case LG3306_SYNC_LOCK:
1187     {
1188         ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1189         if (ret)
1190             return ret;
1191 
1192         if ((val & 0x80) == 0x80)
1193             lockStatus = LG3306_LOCK;
1194         else
1195             lockStatus = LG3306_UNLOCK;
1196 
1197         dbg_info("SYNC_LOCK=%x\n", lockStatus);
1198         break;
1199     }
1200     case LG3306_AGC_LOCK:
1201     {
1202         ret = lgdt3306a_read_reg(state, 0x0080, &val);
1203         if (ret)
1204             return ret;
1205 
1206         if ((val & 0x40) == 0x40)
1207             lockStatus = LG3306_LOCK;
1208         else
1209             lockStatus = LG3306_UNLOCK;
1210 
1211         dbg_info("AGC_LOCK=%x\n", lockStatus);
1212         break;
1213     }
1214     case LG3306_TR_LOCK:
1215     {
1216         modeOper = lgdt3306a_check_oper_mode(state);
1217         if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1218             ret = lgdt3306a_read_reg(state, 0x1094, &val);
1219             if (ret)
1220                 return ret;
1221 
1222             if ((val & 0x80) == 0x80)
1223                 lockStatus = LG3306_LOCK;
1224             else
1225                 lockStatus = LG3306_UNLOCK;
1226         } else
1227             lockStatus = LG3306_UNKNOWN_LOCK;
1228 
1229         dbg_info("TR_LOCK=%x\n", lockStatus);
1230         break;
1231     }
1232     case LG3306_FEC_LOCK:
1233     {
1234         modeOper = lgdt3306a_check_oper_mode(state);
1235         if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1236             ret = lgdt3306a_read_reg(state, 0x0080, &val);
1237             if (ret)
1238                 return ret;
1239 
1240             if ((val & 0x10) == 0x10)
1241                 lockStatus = LG3306_LOCK;
1242             else
1243                 lockStatus = LG3306_UNLOCK;
1244         } else
1245             lockStatus = LG3306_UNKNOWN_LOCK;
1246 
1247         dbg_info("FEC_LOCK=%x\n", lockStatus);
1248         break;
1249     }
1250 
1251     default:
1252         lockStatus = LG3306_UNKNOWN_LOCK;
1253         pr_warn("UNKNOWN whatLock=%d\n", whatLock);
1254         break;
1255     }
1256 
1257     return lockStatus;
1258 }
1259 
1260 static enum lgdt3306a_neverlock_status
1261 lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
1262 {
1263     u8 val = 0;
1264     int ret;
1265     enum lgdt3306a_neverlock_status lockStatus;
1266 
1267     ret = lgdt3306a_read_reg(state, 0x0080, &val);
1268     if (ret)
1269         return ret;
1270     lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
1271 
1272     dbg_info("NeverLock=%d", lockStatus);
1273 
1274     return lockStatus;
1275 }
1276 
1277 static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
1278 {
1279     u8 val = 0;
1280     int ret;
1281     u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
1282 
1283     /* Channel variation */
1284     ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
1285     if (ret)
1286         return ret;
1287 
1288     /* SNR of Frame sync */
1289     ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1290     if (ret)
1291         return ret;
1292     snrRef = val & 0x3f;
1293 
1294     /* Strong Main CIR */
1295     ret = lgdt3306a_read_reg(state, 0x2199, &val);
1296     if (ret)
1297         return ret;
1298     mainStrong = (val & 0x40) >> 6;
1299 
1300     ret = lgdt3306a_read_reg(state, 0x0090, &val);
1301     if (ret)
1302         return ret;
1303     aiccrejStatus = (val & 0xf0) >> 4;
1304 
1305     dbg_info("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
1306         snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
1307 
1308 #if 0
1309     /* Dynamic ghost exists */
1310     if ((mainStrong == 0) && (currChDiffACQ > 0x70))
1311 #endif
1312     if (mainStrong == 0) {
1313         ret = lgdt3306a_read_reg(state, 0x2135, &val);
1314         if (ret)
1315             return ret;
1316         val &= 0x0f;
1317         val |= 0xa0;
1318         ret = lgdt3306a_write_reg(state, 0x2135, val);
1319         if (ret)
1320             return ret;
1321 
1322         ret = lgdt3306a_read_reg(state, 0x2141, &val);
1323         if (ret)
1324             return ret;
1325         val &= 0x3f;
1326         val |= 0x80;
1327         ret = lgdt3306a_write_reg(state, 0x2141, val);
1328         if (ret)
1329             return ret;
1330 
1331         ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
1332         if (ret)
1333             return ret;
1334     } else { /* Weak ghost or static channel */
1335         ret = lgdt3306a_read_reg(state, 0x2135, &val);
1336         if (ret)
1337             return ret;
1338         val &= 0x0f;
1339         val |= 0x70;
1340         ret = lgdt3306a_write_reg(state, 0x2135, val);
1341         if (ret)
1342             return ret;
1343 
1344         ret = lgdt3306a_read_reg(state, 0x2141, &val);
1345         if (ret)
1346             return ret;
1347         val &= 0x3f;
1348         val |= 0x40;
1349         ret = lgdt3306a_write_reg(state, 0x2141, val);
1350         if (ret)
1351             return ret;
1352 
1353         ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
1354         if (ret)
1355             return ret;
1356     }
1357     return 0;
1358 }
1359 
1360 static enum lgdt3306a_lock_status
1361 lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
1362 {
1363     enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
1364     int i;
1365 
1366     for (i = 0; i < 2; i++) {
1367         msleep(30);
1368 
1369         syncLockStatus = lgdt3306a_check_lock_status(state,
1370                                  LG3306_SYNC_LOCK);
1371 
1372         if (syncLockStatus == LG3306_LOCK) {
1373             dbg_info("locked(%d)\n", i);
1374             return LG3306_LOCK;
1375         }
1376     }
1377     dbg_info("not locked\n");
1378     return LG3306_UNLOCK;
1379 }
1380 
1381 static enum lgdt3306a_lock_status
1382 lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
1383 {
1384     enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
1385     int i;
1386 
1387     for (i = 0; i < 2; i++) {
1388         msleep(30);
1389 
1390         FECLockStatus = lgdt3306a_check_lock_status(state,
1391                                 LG3306_FEC_LOCK);
1392 
1393         if (FECLockStatus == LG3306_LOCK) {
1394             dbg_info("locked(%d)\n", i);
1395             return FECLockStatus;
1396         }
1397     }
1398     dbg_info("not locked\n");
1399     return FECLockStatus;
1400 }
1401 
1402 static enum lgdt3306a_neverlock_status
1403 lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
1404 {
1405     enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
1406     int i;
1407 
1408     for (i = 0; i < 5; i++) {
1409         msleep(30);
1410 
1411         NLLockStatus = lgdt3306a_check_neverlock_status(state);
1412 
1413         if (NLLockStatus == LG3306_NL_LOCK) {
1414             dbg_info("NL_LOCK(%d)\n", i);
1415             return NLLockStatus;
1416         }
1417     }
1418     dbg_info("NLLockStatus=%d\n", NLLockStatus);
1419     return NLLockStatus;
1420 }
1421 
1422 static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
1423 {
1424     u8 val;
1425     int ret;
1426 
1427     ret = lgdt3306a_read_reg(state, 0x00fa, &val);
1428     if (ret)
1429         return ret;
1430 
1431     return val;
1432 }
1433 
1434 static const u32 valx_x10[] = {
1435     10,  11,  13,  15,  17,  20,  25,  33,  41,  50,  59,  73,  87,  100
1436 };
1437 static const u32 log10x_x1000[] = {
1438     0,   41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000
1439 };
1440 
1441 static u32 log10_x1000(u32 x)
1442 {
1443     u32 diff_val, step_val, step_log10;
1444     u32 log_val = 0;
1445     u32 i;
1446 
1447     if (x <= 0)
1448         return -1000000; /* signal error */
1449 
1450     if (x == 10)
1451         return 0; /* log(1)=0 */
1452 
1453     if (x < 10) {
1454         while (x < 10) {
1455             x = x * 10;
1456             log_val--;
1457         }
1458     } else {    /* x > 10 */
1459         while (x >= 100) {
1460             x = x / 10;
1461             log_val++;
1462         }
1463     }
1464     log_val *= 1000;
1465 
1466     if (x == 10) /* was our input an exact multiple of 10 */
1467         return log_val; /* don't need to interpolate */
1468 
1469     /* find our place on the log curve */
1470     for (i = 1; i < ARRAY_SIZE(valx_x10); i++) {
1471         if (valx_x10[i] >= x)
1472             break;
1473     }
1474     if (i == ARRAY_SIZE(valx_x10))
1475         return log_val + log10x_x1000[i - 1];
1476 
1477     diff_val   = x - valx_x10[i-1];
1478     step_val   = valx_x10[i] - valx_x10[i - 1];
1479     step_log10 = log10x_x1000[i] - log10x_x1000[i - 1];
1480 
1481     /* do a linear interpolation to get in-between values */
1482     return log_val + log10x_x1000[i - 1] +
1483         ((diff_val*step_log10) / step_val);
1484 }
1485 
1486 static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
1487 {
1488     u32 mse; /* Mean-Square Error */
1489     u32 pwr; /* Constelation power */
1490     u32 snr_x100;
1491 
1492     mse = (read_reg(state, 0x00ec) << 8) |
1493           (read_reg(state, 0x00ed));
1494     pwr = (read_reg(state, 0x00e8) << 8) |
1495           (read_reg(state, 0x00e9));
1496 
1497     if (mse == 0) /* no signal */
1498         return 0;
1499 
1500     snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
1501     dbg_info("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
1502 
1503     return snr_x100;
1504 }
1505 
1506 static enum lgdt3306a_lock_status
1507 lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
1508 {
1509     int ret;
1510     u8 cnt = 0;
1511     u8 packet_error;
1512     u32 snr;
1513 
1514     for (cnt = 0; cnt < 10; cnt++) {
1515         if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
1516             dbg_info("no sync lock!\n");
1517             return LG3306_UNLOCK;
1518         }
1519 
1520         msleep(20);
1521         ret = lgdt3306a_pre_monitoring(state);
1522         if (ret)
1523             break;
1524 
1525         packet_error = lgdt3306a_get_packet_error(state);
1526         snr = lgdt3306a_calculate_snr_x100(state);
1527         dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
1528 
1529         if ((snr >= 1500) && (packet_error < 0xff))
1530             return LG3306_LOCK;
1531     }
1532 
1533     dbg_info("not locked!\n");
1534     return LG3306_UNLOCK;
1535 }
1536 
1537 static enum lgdt3306a_lock_status
1538 lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
1539 {
1540     u8 cnt;
1541     u8 packet_error;
1542     u32 snr;
1543 
1544     for (cnt = 0; cnt < 10; cnt++) {
1545         if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
1546             dbg_info("no fec lock!\n");
1547             return LG3306_UNLOCK;
1548         }
1549 
1550         msleep(20);
1551 
1552         packet_error = lgdt3306a_get_packet_error(state);
1553         snr = lgdt3306a_calculate_snr_x100(state);
1554         dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
1555 
1556         if ((snr >= 1500) && (packet_error < 0xff))
1557             return LG3306_LOCK;
1558     }
1559 
1560     dbg_info("not locked!\n");
1561     return LG3306_UNLOCK;
1562 }
1563 
1564 static int lgdt3306a_read_status(struct dvb_frontend *fe,
1565                  enum fe_status *status)
1566 {
1567     struct lgdt3306a_state *state = fe->demodulator_priv;
1568     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1569     u16 strength = 0;
1570     int ret = 0;
1571 
1572     if (fe->ops.tuner_ops.get_rf_strength) {
1573         ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
1574         if (ret == 0)
1575             dbg_info("strength=%d\n", strength);
1576         else
1577             dbg_info("fe->ops.tuner_ops.get_rf_strength() failed\n");
1578     }
1579 
1580     *status = 0;
1581     if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
1582         *status |= FE_HAS_SIGNAL;
1583         *status |= FE_HAS_CARRIER;
1584 
1585         switch (state->current_modulation) {
1586         case QAM_256:
1587         case QAM_64:
1588         case QAM_AUTO:
1589             if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
1590                 *status |= FE_HAS_VITERBI;
1591                 *status |= FE_HAS_SYNC;
1592 
1593                 *status |= FE_HAS_LOCK;
1594             }
1595             break;
1596         case VSB_8:
1597             if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
1598                 *status |= FE_HAS_VITERBI;
1599                 *status |= FE_HAS_SYNC;
1600 
1601                 *status |= FE_HAS_LOCK;
1602 
1603                 ret = lgdt3306a_monitor_vsb(state);
1604             }
1605             break;
1606         default:
1607             ret = -EINVAL;
1608         }
1609 
1610         if (*status & FE_HAS_SYNC) {
1611             c->cnr.len = 1;
1612             c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1613             c->cnr.stat[0].svalue = lgdt3306a_calculate_snr_x100(state) * 10;
1614         } else {
1615             c->cnr.len = 1;
1616             c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1617         }
1618     }
1619     return ret;
1620 }
1621 
1622 
1623 static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
1624 {
1625     struct lgdt3306a_state *state = fe->demodulator_priv;
1626 
1627     state->snr = lgdt3306a_calculate_snr_x100(state);
1628     /* report SNR in dB * 10 */
1629     *snr = state->snr/10;
1630 
1631     return 0;
1632 }
1633 
1634 static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
1635                      u16 *strength)
1636 {
1637     /*
1638      * Calculate some sort of "strength" from SNR
1639      */
1640     struct lgdt3306a_state *state = fe->demodulator_priv;
1641     u8 val;
1642     u16 snr; /* snr_x10 */
1643     int ret;
1644     u32 ref_snr; /* snr*100 */
1645     u32 str;
1646 
1647     *strength = 0;
1648 
1649     switch (state->current_modulation) {
1650     case VSB_8:
1651          ref_snr = 1600; /* 16dB */
1652          break;
1653     case QAM_64:
1654     case QAM_256:
1655     case QAM_AUTO:
1656         /* need to know actual modulation to set proper SNR baseline */
1657         ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1658         if (lg_chkerr(ret))
1659             goto fail;
1660 
1661         if(val & 0x04)
1662             ref_snr = 2800; /* QAM-256 28dB */
1663         else
1664             ref_snr = 2200; /* QAM-64  22dB */
1665         break;
1666     default:
1667         return -EINVAL;
1668     }
1669 
1670     ret = fe->ops.read_snr(fe, &snr);
1671     if (lg_chkerr(ret))
1672         goto fail;
1673 
1674     if (state->snr <= (ref_snr - 100))
1675         str = 0;
1676     else if (state->snr <= ref_snr)
1677         str = (0xffff * 65) / 100; /* 65% */
1678     else {
1679         str = state->snr - ref_snr;
1680         str /= 50;
1681         str += 78; /* 78%-100% */
1682         if (str > 100)
1683             str = 100;
1684         str = (0xffff * str) / 100;
1685     }
1686     *strength = (u16)str;
1687     dbg_info("strength=%u\n", *strength);
1688 
1689 fail:
1690     return ret;
1691 }
1692 
1693 /* ------------------------------------------------------------------------ */
1694 
1695 static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
1696 {
1697     struct lgdt3306a_state *state = fe->demodulator_priv;
1698     u32 tmp;
1699 
1700     *ber = 0;
1701 #if 1
1702     /* FGR - FIXME - I don't know what value is expected by dvb_core
1703      * what is the scale of the value?? */
1704     tmp =              read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
1705     tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
1706     tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
1707     tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
1708     *ber = tmp;
1709     dbg_info("ber=%u\n", tmp);
1710 #endif
1711     return 0;
1712 }
1713 
1714 static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1715 {
1716     struct lgdt3306a_state *state = fe->demodulator_priv;
1717 
1718     *ucblocks = 0;
1719 #if 1
1720     /* FGR - FIXME - I don't know what value is expected by dvb_core
1721      * what happens when value wraps? */
1722     *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
1723     dbg_info("ucblocks=%u\n", *ucblocks);
1724 #endif
1725 
1726     return 0;
1727 }
1728 
1729 static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune,
1730               unsigned int mode_flags, unsigned int *delay,
1731               enum fe_status *status)
1732 {
1733     int ret = 0;
1734     struct lgdt3306a_state *state = fe->demodulator_priv;
1735 
1736     dbg_info("re_tune=%u\n", re_tune);
1737 
1738     if (re_tune) {
1739         state->current_frequency = -1; /* force re-tune */
1740         ret = lgdt3306a_set_parameters(fe);
1741         if (ret != 0)
1742             return ret;
1743     }
1744     *delay = 125;
1745     ret = lgdt3306a_read_status(fe, status);
1746 
1747     return ret;
1748 }
1749 
1750 static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
1751                        struct dvb_frontend_tune_settings
1752                        *fe_tune_settings)
1753 {
1754     fe_tune_settings->min_delay_ms = 100;
1755     dbg_info("\n");
1756     return 0;
1757 }
1758 
1759 static enum dvbfe_search lgdt3306a_search(struct dvb_frontend *fe)
1760 {
1761     enum fe_status status = 0;
1762     int ret;
1763 
1764     /* set frontend */
1765     ret = lgdt3306a_set_parameters(fe);
1766     if (ret)
1767         goto error;
1768 
1769     ret = lgdt3306a_read_status(fe, &status);
1770     if (ret)
1771         goto error;
1772 
1773     /* check if we have a valid signal */
1774     if (status & FE_HAS_LOCK)
1775         return DVBFE_ALGO_SEARCH_SUCCESS;
1776     else
1777         return DVBFE_ALGO_SEARCH_AGAIN;
1778 
1779 error:
1780     dbg_info("failed (%d)\n", ret);
1781     return DVBFE_ALGO_SEARCH_ERROR;
1782 }
1783 
1784 static void lgdt3306a_release(struct dvb_frontend *fe)
1785 {
1786     struct lgdt3306a_state *state = fe->demodulator_priv;
1787 
1788     dbg_info("\n");
1789     kfree(state);
1790 }
1791 
1792 static const struct dvb_frontend_ops lgdt3306a_ops;
1793 
1794 struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
1795                       struct i2c_adapter *i2c_adap)
1796 {
1797     struct lgdt3306a_state *state = NULL;
1798     int ret;
1799     u8 val;
1800 
1801     dbg_info("(%d-%04x)\n",
1802            i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1803            config ? config->i2c_addr : 0);
1804 
1805     state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
1806     if (state == NULL)
1807         goto fail;
1808 
1809     state->cfg = config;
1810     state->i2c_adap = i2c_adap;
1811 
1812     memcpy(&state->frontend.ops, &lgdt3306a_ops,
1813            sizeof(struct dvb_frontend_ops));
1814     state->frontend.demodulator_priv = state;
1815 
1816     /* verify that we're talking to a lg3306a */
1817     /* FGR - NOTE - there is no obvious ChipId to check; we check
1818      * some "known" bits after reset, but it's still just a guess */
1819     ret = lgdt3306a_read_reg(state, 0x0000, &val);
1820     if (lg_chkerr(ret))
1821         goto fail;
1822     if ((val & 0x74) != 0x74) {
1823         pr_warn("expected 0x74, got 0x%x\n", (val & 0x74));
1824 #if 0
1825         /* FIXME - re-enable when we know this is right */
1826         goto fail;
1827 #endif
1828     }
1829     ret = lgdt3306a_read_reg(state, 0x0001, &val);
1830     if (lg_chkerr(ret))
1831         goto fail;
1832     if ((val & 0xf6) != 0xc6) {
1833         pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
1834 #if 0
1835         /* FIXME - re-enable when we know this is right */
1836         goto fail;
1837 #endif
1838     }
1839     ret = lgdt3306a_read_reg(state, 0x0002, &val);
1840     if (lg_chkerr(ret))
1841         goto fail;
1842     if ((val & 0x73) != 0x03) {
1843         pr_warn("expected 0x03, got 0x%x\n", (val & 0x73));
1844 #if 0
1845         /* FIXME - re-enable when we know this is right */
1846         goto fail;
1847 #endif
1848     }
1849 
1850     state->current_frequency = -1;
1851     state->current_modulation = -1;
1852 
1853     lgdt3306a_sleep(state);
1854 
1855     return &state->frontend;
1856 
1857 fail:
1858     pr_warn("unable to detect LGDT3306A hardware\n");
1859     kfree(state);
1860     return NULL;
1861 }
1862 EXPORT_SYMBOL(lgdt3306a_attach);
1863 
1864 #ifdef DBG_DUMP
1865 
1866 static const short regtab[] = {
1867     0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
1868     0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
1869     0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
1870     0x0003, /* AGCRFOUT */
1871     0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
1872     0x0005, /* PLLINDIVSE */
1873     0x0006, /* PLLCTRL[7:0] 11100001 */
1874     0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
1875     0x0008, /* STDOPMODE[7:0] 10000000 */
1876     0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
1877     0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
1878     0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
1879     0x000d, /* x SAMPLING4 */
1880     0x000e, /* SAMFREQ[15:8] 00000000 */
1881     0x000f, /* SAMFREQ[7:0] 00000000 */
1882     0x0010, /* IFFREQ[15:8] 01100000 */
1883     0x0011, /* IFFREQ[7:0] 00000000 */
1884     0x0012, /* AGCEN AGCREFMO */
1885     0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
1886     0x0014, /* AGCFIXVALUE[7:0] 01111111 */
1887     0x0015, /* AGCREF[15:8] 00001010 */
1888     0x0016, /* AGCREF[7:0] 11100100 */
1889     0x0017, /* AGCDELAY[7:0] 00100000 */
1890     0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
1891     0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
1892     0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
1893     0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
1894     0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
1895     0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
1896     0x0020, /* AICCDETTH[15:8] 01111100 */
1897     0x0021, /* AICCDETTH[7:0] 00000000 */
1898     0x0022, /* AICCOFFTH[15:8] 00000101 */
1899     0x0023, /* AICCOFFTH[7:0] 11100000 */
1900     0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
1901     0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
1902     0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
1903     0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
1904     0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
1905     0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
1906     0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
1907     0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
1908     0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
1909     0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
1910     0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
1911     0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
1912     0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
1913     0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
1914     0x0032, /* DAGC1STEN DAGC1STER */
1915     0x0033, /* DAGC1STREF[15:8] 00001010 */
1916     0x0034, /* DAGC1STREF[7:0] 11100100 */
1917     0x0035, /* DAGC2NDE */
1918     0x0036, /* DAGC2NDREF[15:8] 00001010 */
1919     0x0037, /* DAGC2NDREF[7:0] 10000000 */
1920     0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
1921     0x003d, /* 1'b1 SAMGEARS */
1922     0x0040, /* SAMLFGMA */
1923     0x0041, /* SAMLFBWM */
1924     0x0044, /* 1'b1 CRGEARSHE */
1925     0x0045, /* CRLFGMAN */
1926     0x0046, /* CFLFBWMA */
1927     0x0047, /* CRLFGMAN */
1928     0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
1929     0x0049, /* CRLFBWMA */
1930     0x004a, /* CRLFBWMA */
1931     0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
1932     0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
1933     0x0071, /* TPSENB TPSSOPBITE */
1934     0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
1935     0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
1936     0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
1937     0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
1938     0x0078, /* NBERPOLY[31:24] 00000000 */
1939     0x0079, /* NBERPOLY[23:16] 00000000 */
1940     0x007a, /* NBERPOLY[15:8] 00000000 */
1941     0x007b, /* NBERPOLY[7:0] 00000000 */
1942     0x007c, /* NBERPED[31:24] 00000000 */
1943     0x007d, /* NBERPED[23:16] 00000000 */
1944     0x007e, /* NBERPED[15:8] 00000000 */
1945     0x007f, /* NBERPED[7:0] 00000000 */
1946     0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
1947     0x0085, /* SPECINVST */
1948     0x0088, /* SYSLOCKTIME[15:8] */
1949     0x0089, /* SYSLOCKTIME[7:0] */
1950     0x008c, /* FECLOCKTIME[15:8] */
1951     0x008d, /* FECLOCKTIME[7:0] */
1952     0x008e, /* AGCACCOUT[15:8] */
1953     0x008f, /* AGCACCOUT[7:0] */
1954     0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
1955     0x0091, /* AICCVSYNC */
1956     0x009c, /* CARRFREQOFFSET[15:8] */
1957     0x009d, /* CARRFREQOFFSET[7:0] */
1958     0x00a1, /* SAMFREQOFFSET[23:16] */
1959     0x00a2, /* SAMFREQOFFSET[15:8] */
1960     0x00a3, /* SAMFREQOFFSET[7:0] */
1961     0x00a6, /* SYNCLOCK SYNCLOCKH */
1962 #if 0 /* covered elsewhere */
1963     0x00e8, /* CONSTPWR[15:8] */
1964     0x00e9, /* CONSTPWR[7:0] */
1965     0x00ea, /* BMSE[15:8] */
1966     0x00eb, /* BMSE[7:0] */
1967     0x00ec, /* MSE[15:8] */
1968     0x00ed, /* MSE[7:0] */
1969     0x00ee, /* CONSTI[7:0] */
1970     0x00ef, /* CONSTQ[7:0] */
1971 #endif
1972     0x00f4, /* TPIFTPERRCNT[7:0] */
1973     0x00f5, /* TPCORREC */
1974     0x00f6, /* VBBER[15:8] */
1975     0x00f7, /* VBBER[7:0] */
1976     0x00f8, /* VABER[15:8] */
1977     0x00f9, /* VABER[7:0] */
1978     0x00fa, /* TPERRCNT[7:0] */
1979     0x00fb, /* NBERLOCK x x x x x x x */
1980     0x00fc, /* NBERVALUE[31:24] */
1981     0x00fd, /* NBERVALUE[23:16] */
1982     0x00fe, /* NBERVALUE[15:8] */
1983     0x00ff, /* NBERVALUE[7:0] */
1984     0x1000, /* 1'b0 WODAGCOU */
1985     0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
1986     0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
1987     0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
1988     0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
1989     0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
1990     0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
1991     0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
1992     0x103f, /* SAMZTEDSE */
1993     0x105d, /* EQSTATUSE */
1994     0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
1995     0x1060, /* 1'b1 EQSTATUSE */
1996     0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
1997     0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
1998     0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
1999     0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
2000     0x106e, /* x x x x x CREPHNEN_ */
2001     0x106f, /* CREPHNTH_V[7:0] 00010101 */
2002     0x1072, /* CRSWEEPN */
2003     0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
2004     0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
2005     0x1080, /* DAFTSTATUS[1:0] x x x x x x */
2006     0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
2007     0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
2008     0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
2009 #if 0 /* SMART_ANT */
2010     0x1f00, /* MODEDETE */
2011     0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
2012     0x1f03, /* NUMOFANT[7:0] 10000000 */
2013     0x1f04, /* x SELMASK[6:0] x0000000 */
2014     0x1f05, /* x SETMASK[6:0] x0000000 */
2015     0x1f06, /* x TXDATA[6:0] x0000000 */
2016     0x1f07, /* x CHNUMBER[6:0] x0000000 */
2017     0x1f09, /* AGCTIME[23:16] 10011000 */
2018     0x1f0a, /* AGCTIME[15:8] 10010110 */
2019     0x1f0b, /* AGCTIME[7:0] 10000000 */
2020     0x1f0c, /* ANTTIME[31:24] 00000000 */
2021     0x1f0d, /* ANTTIME[23:16] 00000011 */
2022     0x1f0e, /* ANTTIME[15:8] 10010000 */
2023     0x1f0f, /* ANTTIME[7:0] 10010000 */
2024     0x1f11, /* SYNCTIME[23:16] 10011000 */
2025     0x1f12, /* SYNCTIME[15:8] 10010110 */
2026     0x1f13, /* SYNCTIME[7:0] 10000000 */
2027     0x1f14, /* SNRTIME[31:24] 00000001 */
2028     0x1f15, /* SNRTIME[23:16] 01111101 */
2029     0x1f16, /* SNRTIME[15:8] 01111000 */
2030     0x1f17, /* SNRTIME[7:0] 01000000 */
2031     0x1f19, /* FECTIME[23:16] 00000000 */
2032     0x1f1a, /* FECTIME[15:8] 01110010 */
2033     0x1f1b, /* FECTIME[7:0] 01110000 */
2034     0x1f1d, /* FECTHD[7:0] 00000011 */
2035     0x1f1f, /* SNRTHD[23:16] 00001000 */
2036     0x1f20, /* SNRTHD[15:8] 01111111 */
2037     0x1f21, /* SNRTHD[7:0] 10000101 */
2038     0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
2039     0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
2040     0x1f82, /* x x x SCANOPCD[4:0] */
2041     0x1f83, /* x x x x MAINOPCD[3:0] */
2042     0x1f84, /* x x RXDATA[13:8] */
2043     0x1f85, /* RXDATA[7:0] */
2044     0x1f86, /* x x SDTDATA[13:8] */
2045     0x1f87, /* SDTDATA[7:0] */
2046     0x1f89, /* ANTSNR[23:16] */
2047     0x1f8a, /* ANTSNR[15:8] */
2048     0x1f8b, /* ANTSNR[7:0] */
2049     0x1f8c, /* x x x x ANTFEC[13:8] */
2050     0x1f8d, /* ANTFEC[7:0] */
2051     0x1f8e, /* MAXCNT[7:0] */
2052     0x1f8f, /* SCANCNT[7:0] */
2053     0x1f91, /* MAXPW[23:16] */
2054     0x1f92, /* MAXPW[15:8] */
2055     0x1f93, /* MAXPW[7:0] */
2056     0x1f95, /* CURPWMSE[23:16] */
2057     0x1f96, /* CURPWMSE[15:8] */
2058     0x1f97, /* CURPWMSE[7:0] */
2059 #endif /* SMART_ANT */
2060     0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
2061     0x212a, /* EQAUTOST */
2062     0x2122, /* CHFAST[7:0] 01100000 */
2063     0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
2064     0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
2065     0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
2066     0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
2067     0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
2068     0x2162, /* AICCCTRLE */
2069     0x2173, /* PHNCNFCNT[7:0] 00000100 */
2070     0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
2071     0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
2072     0x217e, /* CNFCNTTPIF[7:0] 00001000 */
2073     0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
2074     0x2180, /* x x x x x x FBDLYCIR[9:8] */
2075     0x2181, /* FBDLYCIR[7:0] */
2076     0x2185, /* MAXPWRMAIN[7:0] */
2077     0x2191, /* NCOMBDET x x x x x x x */
2078     0x2199, /* x MAINSTRON */
2079     0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
2080     0x21a1, /* x x SNRREF[5:0] */
2081     0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
2082     0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
2083     0x2847, /* ENNOSIGDE */
2084     0x2849, /* 1'b1 1'b1 NOUSENOSI */
2085     0x284a, /* EQINITWAITTIME[7:0] 01100100 */
2086     0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
2087     0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
2088     0x3031, /* FRAMELOC */
2089     0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
2090     0x30a9, /* VDLOCK_Q FRAMELOCK */
2091     0x30aa, /* MPEGLOCK */
2092 };
2093 
2094 #define numDumpRegs (ARRAY_SIZE(regtab))
2095 static u8 regval1[numDumpRegs] = {0, };
2096 static u8 regval2[numDumpRegs] = {0, };
2097 
2098 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
2099 {
2100         memset(regval2, 0xff, sizeof(regval2));
2101         lgdt3306a_DumpRegs(state);
2102 }
2103 
2104 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
2105 {
2106     int i;
2107     int sav_debug = debug;
2108 
2109     if ((debug & DBG_DUMP) == 0)
2110         return;
2111     debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */
2112 
2113     lg_debug("\n");
2114 
2115     for (i = 0; i < numDumpRegs; i++) {
2116         lgdt3306a_read_reg(state, regtab[i], &regval1[i]);
2117         if (regval1[i] != regval2[i]) {
2118             lg_debug(" %04X = %02X\n", regtab[i], regval1[i]);
2119             regval2[i] = regval1[i];
2120         }
2121     }
2122     debug = sav_debug;
2123 }
2124 #endif /* DBG_DUMP */
2125 
2126 
2127 
2128 static const struct dvb_frontend_ops lgdt3306a_ops = {
2129     .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
2130     .info = {
2131         .name = "LG Electronics LGDT3306A VSB/QAM Frontend",
2132         .frequency_min_hz      =  54 * MHz,
2133         .frequency_max_hz      = 858 * MHz,
2134         .frequency_stepsize_hz = 62500,
2135         .caps = FE_CAN_QAM_AUTO | FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
2136     },
2137     .i2c_gate_ctrl        = lgdt3306a_i2c_gate_ctrl,
2138     .init                 = lgdt3306a_init,
2139     .sleep                = lgdt3306a_fe_sleep,
2140     /* if this is set, it overrides the default swzigzag */
2141     .tune                 = lgdt3306a_tune,
2142     .set_frontend         = lgdt3306a_set_parameters,
2143     .get_frontend         = lgdt3306a_get_frontend,
2144     .get_frontend_algo    = lgdt3306a_get_frontend_algo,
2145     .get_tune_settings    = lgdt3306a_get_tune_settings,
2146     .read_status          = lgdt3306a_read_status,
2147     .read_ber             = lgdt3306a_read_ber,
2148     .read_signal_strength = lgdt3306a_read_signal_strength,
2149     .read_snr             = lgdt3306a_read_snr,
2150     .read_ucblocks        = lgdt3306a_read_ucblocks,
2151     .release              = lgdt3306a_release,
2152     .ts_bus_ctrl          = lgdt3306a_ts_bus_ctrl,
2153     .search               = lgdt3306a_search,
2154 };
2155 
2156 static int lgdt3306a_select(struct i2c_mux_core *muxc, u32 chan)
2157 {
2158     struct i2c_client *client = i2c_mux_priv(muxc);
2159     struct lgdt3306a_state *state = i2c_get_clientdata(client);
2160 
2161     return lgdt3306a_i2c_gate_ctrl(&state->frontend, 1);
2162 }
2163 
2164 static int lgdt3306a_deselect(struct i2c_mux_core *muxc, u32 chan)
2165 {
2166     struct i2c_client *client = i2c_mux_priv(muxc);
2167     struct lgdt3306a_state *state = i2c_get_clientdata(client);
2168 
2169     return lgdt3306a_i2c_gate_ctrl(&state->frontend, 0);
2170 }
2171 
2172 static int lgdt3306a_probe(struct i2c_client *client,
2173         const struct i2c_device_id *id)
2174 {
2175     struct lgdt3306a_config *config;
2176     struct lgdt3306a_state *state;
2177     struct dvb_frontend *fe;
2178     int ret;
2179 
2180     config = kmemdup(client->dev.platform_data,
2181              sizeof(struct lgdt3306a_config), GFP_KERNEL);
2182     if (config == NULL) {
2183         ret = -ENOMEM;
2184         goto fail;
2185     }
2186 
2187     config->i2c_addr = client->addr;
2188     fe = lgdt3306a_attach(config, client->adapter);
2189     if (fe == NULL) {
2190         ret = -ENODEV;
2191         goto err_fe;
2192     }
2193 
2194     i2c_set_clientdata(client, fe->demodulator_priv);
2195     state = fe->demodulator_priv;
2196     state->frontend.ops.release = NULL;
2197 
2198     /* create mux i2c adapter for tuner */
2199     state->muxc = i2c_mux_alloc(client->adapter, &client->dev,
2200                   1, 0, I2C_MUX_LOCKED,
2201                   lgdt3306a_select, lgdt3306a_deselect);
2202     if (!state->muxc) {
2203         ret = -ENOMEM;
2204         goto err_kfree;
2205     }
2206     state->muxc->priv = client;
2207     ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
2208     if (ret)
2209         goto err_kfree;
2210 
2211     /* create dvb_frontend */
2212     fe->ops.i2c_gate_ctrl = NULL;
2213     *config->i2c_adapter = state->muxc->adapter[0];
2214     *config->fe = fe;
2215 
2216     dev_info(&client->dev, "LG Electronics LGDT3306A successfully identified\n");
2217 
2218     return 0;
2219 
2220 err_kfree:
2221     kfree(state);
2222 err_fe:
2223     kfree(config);
2224 fail:
2225     dev_warn(&client->dev, "probe failed = %d\n", ret);
2226     return ret;
2227 }
2228 
2229 static int lgdt3306a_remove(struct i2c_client *client)
2230 {
2231     struct lgdt3306a_state *state = i2c_get_clientdata(client);
2232 
2233     i2c_mux_del_adapters(state->muxc);
2234 
2235     state->frontend.ops.release = NULL;
2236     state->frontend.demodulator_priv = NULL;
2237 
2238     kfree(state->cfg);
2239     kfree(state);
2240 
2241     return 0;
2242 }
2243 
2244 static const struct i2c_device_id lgdt3306a_id_table[] = {
2245     {"lgdt3306a", 0},
2246     {}
2247 };
2248 MODULE_DEVICE_TABLE(i2c, lgdt3306a_id_table);
2249 
2250 static struct i2c_driver lgdt3306a_driver = {
2251     .driver = {
2252         .name                = "lgdt3306a",
2253         .suppress_bind_attrs = true,
2254     },
2255     .probe      = lgdt3306a_probe,
2256     .remove     = lgdt3306a_remove,
2257     .id_table   = lgdt3306a_id_table,
2258 };
2259 
2260 module_i2c_driver(lgdt3306a_driver);
2261 
2262 MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
2263 MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>");
2264 MODULE_LICENSE("GPL");
2265 MODULE_VERSION("0.2");
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