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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *    Support for LG Electronics LGDT3304 and LGDT3305 - VSB/QAM
0004  *
0005  *    Copyright (C) 2008, 2009, 2010 Michael Krufky <mkrufky@linuxtv.org>
0006  *
0007  *    LGDT3304 support by Jarod Wilson <jarod@redhat.com>
0008  */
0009 
0010 #include <asm/div64.h>
0011 #include <linux/dvb/frontend.h>
0012 #include <linux/slab.h>
0013 #include <media/dvb_math.h>
0014 #include "lgdt3305.h"
0015 
0016 static int debug;
0017 module_param(debug, int, 0644);
0018 MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
0019 
0020 #define DBG_INFO 1
0021 #define DBG_REG  2
0022 
0023 #define lg_printk(kern, fmt, arg...)                    \
0024     printk(kern "%s: " fmt, __func__, ##arg)
0025 
0026 #define lg_info(fmt, arg...)    printk(KERN_INFO "lgdt3305: " fmt, ##arg)
0027 #define lg_warn(fmt, arg...)    lg_printk(KERN_WARNING,       fmt, ##arg)
0028 #define lg_err(fmt, arg...) lg_printk(KERN_ERR,           fmt, ##arg)
0029 #define lg_dbg(fmt, arg...) if (debug & DBG_INFO)           \
0030                 lg_printk(KERN_DEBUG,         fmt, ##arg)
0031 #define lg_reg(fmt, arg...) if (debug & DBG_REG)            \
0032                 lg_printk(KERN_DEBUG,         fmt, ##arg)
0033 
0034 #define lg_fail(ret)                            \
0035 ({                                  \
0036     int __ret;                          \
0037     __ret = (ret < 0);                      \
0038     if (__ret)                          \
0039         lg_err("error %d on line %d\n", ret, __LINE__);     \
0040     __ret;                              \
0041 })
0042 
0043 struct lgdt3305_state {
0044     struct i2c_adapter *i2c_adap;
0045     const struct lgdt3305_config *cfg;
0046 
0047     struct dvb_frontend frontend;
0048 
0049     enum fe_modulation current_modulation;
0050     u32 current_frequency;
0051     u32 snr;
0052 };
0053 
0054 /* ------------------------------------------------------------------------ */
0055 
0056 /* FIXME: verify & document the LGDT3304 registers */
0057 
0058 #define LGDT3305_GEN_CTRL_1                   0x0000
0059 #define LGDT3305_GEN_CTRL_2                   0x0001
0060 #define LGDT3305_GEN_CTRL_3                   0x0002
0061 #define LGDT3305_GEN_STATUS                   0x0003
0062 #define LGDT3305_GEN_CONTROL                  0x0007
0063 #define LGDT3305_GEN_CTRL_4                   0x000a
0064 #define LGDT3305_DGTL_AGC_REF_1               0x0012
0065 #define LGDT3305_DGTL_AGC_REF_2               0x0013
0066 #define LGDT3305_CR_CTR_FREQ_1                0x0106
0067 #define LGDT3305_CR_CTR_FREQ_2                0x0107
0068 #define LGDT3305_CR_CTR_FREQ_3                0x0108
0069 #define LGDT3305_CR_CTR_FREQ_4                0x0109
0070 #define LGDT3305_CR_MSE_1                     0x011b
0071 #define LGDT3305_CR_MSE_2                     0x011c
0072 #define LGDT3305_CR_LOCK_STATUS               0x011d
0073 #define LGDT3305_CR_CTRL_7                    0x0126
0074 #define LGDT3305_AGC_POWER_REF_1              0x0300
0075 #define LGDT3305_AGC_POWER_REF_2              0x0301
0076 #define LGDT3305_AGC_DELAY_PT_1               0x0302
0077 #define LGDT3305_AGC_DELAY_PT_2               0x0303
0078 #define LGDT3305_RFAGC_LOOP_FLTR_BW_1         0x0306
0079 #define LGDT3305_RFAGC_LOOP_FLTR_BW_2         0x0307
0080 #define LGDT3305_IFBW_1                       0x0308
0081 #define LGDT3305_IFBW_2                       0x0309
0082 #define LGDT3305_AGC_CTRL_1                   0x030c
0083 #define LGDT3305_AGC_CTRL_4                   0x0314
0084 #define LGDT3305_EQ_MSE_1                     0x0413
0085 #define LGDT3305_EQ_MSE_2                     0x0414
0086 #define LGDT3305_EQ_MSE_3                     0x0415
0087 #define LGDT3305_PT_MSE_1                     0x0417
0088 #define LGDT3305_PT_MSE_2                     0x0418
0089 #define LGDT3305_PT_MSE_3                     0x0419
0090 #define LGDT3305_FEC_BLOCK_CTRL               0x0504
0091 #define LGDT3305_FEC_LOCK_STATUS              0x050a
0092 #define LGDT3305_FEC_PKT_ERR_1                0x050c
0093 #define LGDT3305_FEC_PKT_ERR_2                0x050d
0094 #define LGDT3305_TP_CTRL_1                    0x050e
0095 #define LGDT3305_BERT_PERIOD                  0x0801
0096 #define LGDT3305_BERT_ERROR_COUNT_1           0x080a
0097 #define LGDT3305_BERT_ERROR_COUNT_2           0x080b
0098 #define LGDT3305_BERT_ERROR_COUNT_3           0x080c
0099 #define LGDT3305_BERT_ERROR_COUNT_4           0x080d
0100 
0101 static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val)
0102 {
0103     int ret;
0104     u8 buf[] = { reg >> 8, reg & 0xff, val };
0105     struct i2c_msg msg = {
0106         .addr = state->cfg->i2c_addr, .flags = 0,
0107         .buf = buf, .len = 3,
0108     };
0109 
0110     lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
0111 
0112     ret = i2c_transfer(state->i2c_adap, &msg, 1);
0113 
0114     if (ret != 1) {
0115         lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
0116                msg.buf[0], msg.buf[1], msg.buf[2], ret);
0117         if (ret < 0)
0118             return ret;
0119         else
0120             return -EREMOTEIO;
0121     }
0122     return 0;
0123 }
0124 
0125 static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val)
0126 {
0127     int ret;
0128     u8 reg_buf[] = { reg >> 8, reg & 0xff };
0129     struct i2c_msg msg[] = {
0130         { .addr = state->cfg->i2c_addr,
0131           .flags = 0, .buf = reg_buf, .len = 2 },
0132         { .addr = state->cfg->i2c_addr,
0133           .flags = I2C_M_RD, .buf = val, .len = 1 },
0134     };
0135 
0136     lg_reg("reg: 0x%04x\n", reg);
0137 
0138     ret = i2c_transfer(state->i2c_adap, msg, 2);
0139 
0140     if (ret != 2) {
0141         lg_err("error (addr %02x reg %04x error (ret == %i)\n",
0142                state->cfg->i2c_addr, reg, ret);
0143         if (ret < 0)
0144             return ret;
0145         else
0146             return -EREMOTEIO;
0147     }
0148     return 0;
0149 }
0150 
0151 #define read_reg(state, reg)                        \
0152 ({                                  \
0153     u8 __val;                           \
0154     int ret = lgdt3305_read_reg(state, reg, &__val);        \
0155     if (lg_fail(ret))                       \
0156         __val = 0;                      \
0157     __val;                              \
0158 })
0159 
0160 static int lgdt3305_set_reg_bit(struct lgdt3305_state *state,
0161                 u16 reg, int bit, int onoff)
0162 {
0163     u8 val;
0164     int ret;
0165 
0166     lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
0167 
0168     ret = lgdt3305_read_reg(state, reg, &val);
0169     if (lg_fail(ret))
0170         goto fail;
0171 
0172     val &= ~(1 << bit);
0173     val |= (onoff & 1) << bit;
0174 
0175     ret = lgdt3305_write_reg(state, reg, val);
0176 fail:
0177     return ret;
0178 }
0179 
0180 struct lgdt3305_reg {
0181     u16 reg;
0182     u8 val;
0183 };
0184 
0185 static int lgdt3305_write_regs(struct lgdt3305_state *state,
0186                    struct lgdt3305_reg *regs, int len)
0187 {
0188     int i, ret;
0189 
0190     lg_reg("writing %d registers...\n", len);
0191 
0192     for (i = 0; i < len - 1; i++) {
0193         ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val);
0194         if (lg_fail(ret))
0195             return ret;
0196     }
0197     return 0;
0198 }
0199 
0200 /* ------------------------------------------------------------------------ */
0201 
0202 static int lgdt3305_soft_reset(struct lgdt3305_state *state)
0203 {
0204     int ret;
0205 
0206     lg_dbg("\n");
0207 
0208     ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 0);
0209     if (lg_fail(ret))
0210         goto fail;
0211 
0212     msleep(20);
0213     ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 1);
0214 fail:
0215     return ret;
0216 }
0217 
0218 static inline int lgdt3305_mpeg_mode(struct lgdt3305_state *state,
0219                      enum lgdt3305_mpeg_mode mode)
0220 {
0221     lg_dbg("(%d)\n", mode);
0222     return lgdt3305_set_reg_bit(state, LGDT3305_TP_CTRL_1, 5, mode);
0223 }
0224 
0225 static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state)
0226 {
0227     u8 val;
0228     int ret;
0229     enum lgdt3305_tp_clock_edge edge = state->cfg->tpclk_edge;
0230     enum lgdt3305_tp_clock_mode mode = state->cfg->tpclk_mode;
0231     enum lgdt3305_tp_valid_polarity valid = state->cfg->tpvalid_polarity;
0232 
0233     lg_dbg("edge = %d, valid = %d\n", edge, valid);
0234 
0235     ret = lgdt3305_read_reg(state, LGDT3305_TP_CTRL_1, &val);
0236     if (lg_fail(ret))
0237         goto fail;
0238 
0239     val &= ~0x09;
0240 
0241     if (edge)
0242         val |= 0x08;
0243     if (mode)
0244         val |= 0x40;
0245     if (valid)
0246         val |= 0x01;
0247 
0248     ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val);
0249     if (lg_fail(ret))
0250         goto fail;
0251 
0252     ret = lgdt3305_soft_reset(state);
0253 fail:
0254     return ret;
0255 }
0256 
0257 static int lgdt3305_set_modulation(struct lgdt3305_state *state,
0258                    struct dtv_frontend_properties *p)
0259 {
0260     u8 opermode;
0261     int ret;
0262 
0263     lg_dbg("\n");
0264 
0265     ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_1, &opermode);
0266     if (lg_fail(ret))
0267         goto fail;
0268 
0269     opermode &= ~0x03;
0270 
0271     switch (p->modulation) {
0272     case VSB_8:
0273         opermode |= 0x03;
0274         break;
0275     case QAM_64:
0276         opermode |= 0x00;
0277         break;
0278     case QAM_256:
0279         opermode |= 0x01;
0280         break;
0281     default:
0282         return -EINVAL;
0283     }
0284     ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode);
0285 fail:
0286     return ret;
0287 }
0288 
0289 static int lgdt3305_set_filter_extension(struct lgdt3305_state *state,
0290                      struct dtv_frontend_properties *p)
0291 {
0292     int val;
0293 
0294     switch (p->modulation) {
0295     case VSB_8:
0296         val = 0;
0297         break;
0298     case QAM_64:
0299     case QAM_256:
0300         val = 1;
0301         break;
0302     default:
0303         return -EINVAL;
0304     }
0305     lg_dbg("val = %d\n", val);
0306 
0307     return lgdt3305_set_reg_bit(state, 0x043f, 2, val);
0308 }
0309 
0310 /* ------------------------------------------------------------------------ */
0311 
0312 static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state,
0313                      struct dtv_frontend_properties *p)
0314 {
0315     u16 agc_ref;
0316 
0317     switch (p->modulation) {
0318     case VSB_8:
0319         agc_ref = 0x32c4;
0320         break;
0321     case QAM_64:
0322         agc_ref = 0x2a00;
0323         break;
0324     case QAM_256:
0325         agc_ref = 0x2a80;
0326         break;
0327     default:
0328         return -EINVAL;
0329     }
0330 
0331     lg_dbg("agc ref: 0x%04x\n", agc_ref);
0332 
0333     lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8);
0334     lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff);
0335 
0336     return 0;
0337 }
0338 
0339 static int lgdt3305_rfagc_loop(struct lgdt3305_state *state,
0340                    struct dtv_frontend_properties *p)
0341 {
0342     u16 ifbw, rfbw, agcdelay;
0343 
0344     switch (p->modulation) {
0345     case VSB_8:
0346         agcdelay = 0x04c0;
0347         rfbw     = 0x8000;
0348         ifbw     = 0x8000;
0349         break;
0350     case QAM_64:
0351     case QAM_256:
0352         agcdelay = 0x046b;
0353         rfbw     = 0x8889;
0354         /* FIXME: investigate optimal ifbw & rfbw values for the
0355          *        DT3304 and re-write this switch..case block */
0356         if (state->cfg->demod_chip == LGDT3304)
0357             ifbw = 0x6666;
0358         else /* (state->cfg->demod_chip == LGDT3305) */
0359             ifbw = 0x8888;
0360         break;
0361     default:
0362         return -EINVAL;
0363     }
0364 
0365     if (state->cfg->rf_agc_loop) {
0366         lg_dbg("agcdelay: 0x%04x, rfbw: 0x%04x\n", agcdelay, rfbw);
0367 
0368         /* rf agc loop filter bandwidth */
0369         lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1,
0370                    agcdelay >> 8);
0371         lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2,
0372                    agcdelay & 0xff);
0373 
0374         lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1,
0375                    rfbw >> 8);
0376         lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2,
0377                    rfbw & 0xff);
0378     } else {
0379         lg_dbg("ifbw: 0x%04x\n", ifbw);
0380 
0381         /* if agc loop filter bandwidth */
0382         lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8);
0383         lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff);
0384     }
0385 
0386     return 0;
0387 }
0388 
0389 static int lgdt3305_agc_setup(struct lgdt3305_state *state,
0390                   struct dtv_frontend_properties *p)
0391 {
0392     int lockdten, acqen;
0393 
0394     switch (p->modulation) {
0395     case VSB_8:
0396         lockdten = 0;
0397         acqen = 0;
0398         break;
0399     case QAM_64:
0400     case QAM_256:
0401         lockdten = 1;
0402         acqen = 1;
0403         break;
0404     default:
0405         return -EINVAL;
0406     }
0407 
0408     lg_dbg("lockdten = %d, acqen = %d\n", lockdten, acqen);
0409 
0410     /* control agc function */
0411     switch (state->cfg->demod_chip) {
0412     case LGDT3304:
0413         lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1);
0414         lgdt3305_set_reg_bit(state, 0x030e, 2, acqen);
0415         break;
0416     case LGDT3305:
0417         lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1);
0418         lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 2, acqen);
0419         break;
0420     default:
0421         return -EINVAL;
0422     }
0423 
0424     return lgdt3305_rfagc_loop(state, p);
0425 }
0426 
0427 static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state,
0428                       struct dtv_frontend_properties *p)
0429 {
0430     u16 usref = 0;
0431 
0432     switch (p->modulation) {
0433     case VSB_8:
0434         if (state->cfg->usref_8vsb)
0435             usref = state->cfg->usref_8vsb;
0436         break;
0437     case QAM_64:
0438         if (state->cfg->usref_qam64)
0439             usref = state->cfg->usref_qam64;
0440         break;
0441     case QAM_256:
0442         if (state->cfg->usref_qam256)
0443             usref = state->cfg->usref_qam256;
0444         break;
0445     default:
0446         return -EINVAL;
0447     }
0448 
0449     if (usref) {
0450         lg_dbg("set manual mode: 0x%04x\n", usref);
0451 
0452         lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 3, 1);
0453 
0454         lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1,
0455                    0xff & (usref >> 8));
0456         lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2,
0457                    0xff & (usref >> 0));
0458     }
0459     return 0;
0460 }
0461 
0462 /* ------------------------------------------------------------------------ */
0463 
0464 static int lgdt3305_spectral_inversion(struct lgdt3305_state *state,
0465                        struct dtv_frontend_properties *p,
0466                        int inversion)
0467 {
0468     int ret;
0469 
0470     lg_dbg("(%d)\n", inversion);
0471 
0472     switch (p->modulation) {
0473     case VSB_8:
0474         ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7,
0475                      inversion ? 0xf9 : 0x79);
0476         break;
0477     case QAM_64:
0478     case QAM_256:
0479         ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL,
0480                      inversion ? 0xfd : 0xff);
0481         break;
0482     default:
0483         ret = -EINVAL;
0484     }
0485     return ret;
0486 }
0487 
0488 static int lgdt3305_set_if(struct lgdt3305_state *state,
0489                struct dtv_frontend_properties *p)
0490 {
0491     u16 if_freq_khz;
0492     u8 nco1, nco2, nco3, nco4;
0493     u64 nco;
0494 
0495     switch (p->modulation) {
0496     case VSB_8:
0497         if_freq_khz = state->cfg->vsb_if_khz;
0498         break;
0499     case QAM_64:
0500     case QAM_256:
0501         if_freq_khz = state->cfg->qam_if_khz;
0502         break;
0503     default:
0504         return -EINVAL;
0505     }
0506 
0507     nco = if_freq_khz / 10;
0508 
0509     switch (p->modulation) {
0510     case VSB_8:
0511         nco <<= 24;
0512         do_div(nco, 625);
0513         break;
0514     case QAM_64:
0515     case QAM_256:
0516         nco <<= 28;
0517         do_div(nco, 625);
0518         break;
0519     default:
0520         return -EINVAL;
0521     }
0522 
0523     nco1 = (nco >> 24) & 0x3f;
0524     nco1 |= 0x40;
0525     nco2 = (nco >> 16) & 0xff;
0526     nco3 = (nco >> 8) & 0xff;
0527     nco4 = nco & 0xff;
0528 
0529     lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1);
0530     lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2);
0531     lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3);
0532     lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4);
0533 
0534     lg_dbg("%d KHz -> [%02x%02x%02x%02x]\n",
0535            if_freq_khz, nco1, nco2, nco3, nco4);
0536 
0537     return 0;
0538 }
0539 
0540 /* ------------------------------------------------------------------------ */
0541 
0542 static int lgdt3305_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
0543 {
0544     struct lgdt3305_state *state = fe->demodulator_priv;
0545 
0546     if (state->cfg->deny_i2c_rptr)
0547         return 0;
0548 
0549     lg_dbg("(%d)\n", enable);
0550 
0551     return lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_2, 5,
0552                     enable ? 0 : 1);
0553 }
0554 
0555 static int lgdt3305_sleep(struct dvb_frontend *fe)
0556 {
0557     struct lgdt3305_state *state = fe->demodulator_priv;
0558     u8 gen_ctrl_3, gen_ctrl_4;
0559 
0560     lg_dbg("\n");
0561 
0562     gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3);
0563     gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4);
0564 
0565     /* hold in software reset while sleeping */
0566     gen_ctrl_3 &= ~0x01;
0567     /* tristate the IF-AGC pin */
0568     gen_ctrl_3 |=  0x02;
0569     /* tristate the RF-AGC pin */
0570     gen_ctrl_3 |=  0x04;
0571 
0572     /* disable vsb/qam module */
0573     gen_ctrl_4 &= ~0x01;
0574     /* disable adc module */
0575     gen_ctrl_4 &= ~0x02;
0576 
0577     lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3);
0578     lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4);
0579 
0580     return 0;
0581 }
0582 
0583 static int lgdt3305_init(struct dvb_frontend *fe)
0584 {
0585     struct lgdt3305_state *state = fe->demodulator_priv;
0586     int ret;
0587 
0588     static struct lgdt3305_reg lgdt3304_init_data[] = {
0589         { .reg = LGDT3305_GEN_CTRL_1,           .val = 0x03, },
0590         { .reg = 0x000d,                        .val = 0x02, },
0591         { .reg = 0x000e,                        .val = 0x02, },
0592         { .reg = LGDT3305_DGTL_AGC_REF_1,       .val = 0x32, },
0593         { .reg = LGDT3305_DGTL_AGC_REF_2,       .val = 0xc4, },
0594         { .reg = LGDT3305_CR_CTR_FREQ_1,        .val = 0x00, },
0595         { .reg = LGDT3305_CR_CTR_FREQ_2,        .val = 0x00, },
0596         { .reg = LGDT3305_CR_CTR_FREQ_3,        .val = 0x00, },
0597         { .reg = LGDT3305_CR_CTR_FREQ_4,        .val = 0x00, },
0598         { .reg = LGDT3305_CR_CTRL_7,            .val = 0xf9, },
0599         { .reg = 0x0112,                        .val = 0x17, },
0600         { .reg = 0x0113,                        .val = 0x15, },
0601         { .reg = 0x0114,                        .val = 0x18, },
0602         { .reg = 0x0115,                        .val = 0xff, },
0603         { .reg = 0x0116,                        .val = 0x3c, },
0604         { .reg = 0x0214,                        .val = 0x67, },
0605         { .reg = 0x0424,                        .val = 0x8d, },
0606         { .reg = 0x0427,                        .val = 0x12, },
0607         { .reg = 0x0428,                        .val = 0x4f, },
0608         { .reg = LGDT3305_IFBW_1,               .val = 0x80, },
0609         { .reg = LGDT3305_IFBW_2,               .val = 0x00, },
0610         { .reg = 0x030a,                        .val = 0x08, },
0611         { .reg = 0x030b,                        .val = 0x9b, },
0612         { .reg = 0x030d,                        .val = 0x00, },
0613         { .reg = 0x030e,                        .val = 0x1c, },
0614         { .reg = 0x0314,                        .val = 0xe1, },
0615         { .reg = 0x000d,                        .val = 0x82, },
0616         { .reg = LGDT3305_TP_CTRL_1,            .val = 0x5b, },
0617         { .reg = LGDT3305_TP_CTRL_1,            .val = 0x5b, },
0618     };
0619 
0620     static struct lgdt3305_reg lgdt3305_init_data[] = {
0621         { .reg = LGDT3305_GEN_CTRL_1,           .val = 0x03, },
0622         { .reg = LGDT3305_GEN_CTRL_2,           .val = 0xb0, },
0623         { .reg = LGDT3305_GEN_CTRL_3,           .val = 0x01, },
0624         { .reg = LGDT3305_GEN_CONTROL,          .val = 0x6f, },
0625         { .reg = LGDT3305_GEN_CTRL_4,           .val = 0x03, },
0626         { .reg = LGDT3305_DGTL_AGC_REF_1,       .val = 0x32, },
0627         { .reg = LGDT3305_DGTL_AGC_REF_2,       .val = 0xc4, },
0628         { .reg = LGDT3305_CR_CTR_FREQ_1,        .val = 0x00, },
0629         { .reg = LGDT3305_CR_CTR_FREQ_2,        .val = 0x00, },
0630         { .reg = LGDT3305_CR_CTR_FREQ_3,        .val = 0x00, },
0631         { .reg = LGDT3305_CR_CTR_FREQ_4,        .val = 0x00, },
0632         { .reg = LGDT3305_CR_CTRL_7,            .val = 0x79, },
0633         { .reg = LGDT3305_AGC_POWER_REF_1,      .val = 0x32, },
0634         { .reg = LGDT3305_AGC_POWER_REF_2,      .val = 0xc4, },
0635         { .reg = LGDT3305_AGC_DELAY_PT_1,       .val = 0x0d, },
0636         { .reg = LGDT3305_AGC_DELAY_PT_2,       .val = 0x30, },
0637         { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1, .val = 0x80, },
0638         { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2, .val = 0x00, },
0639         { .reg = LGDT3305_IFBW_1,               .val = 0x80, },
0640         { .reg = LGDT3305_IFBW_2,               .val = 0x00, },
0641         { .reg = LGDT3305_AGC_CTRL_1,           .val = 0x30, },
0642         { .reg = LGDT3305_AGC_CTRL_4,           .val = 0x61, },
0643         { .reg = LGDT3305_FEC_BLOCK_CTRL,       .val = 0xff, },
0644         { .reg = LGDT3305_TP_CTRL_1,            .val = 0x1b, },
0645     };
0646 
0647     lg_dbg("\n");
0648 
0649     switch (state->cfg->demod_chip) {
0650     case LGDT3304:
0651         ret = lgdt3305_write_regs(state, lgdt3304_init_data,
0652                       ARRAY_SIZE(lgdt3304_init_data));
0653         break;
0654     case LGDT3305:
0655         ret = lgdt3305_write_regs(state, lgdt3305_init_data,
0656                       ARRAY_SIZE(lgdt3305_init_data));
0657         break;
0658     default:
0659         ret = -EINVAL;
0660     }
0661     if (lg_fail(ret))
0662         goto fail;
0663 
0664     ret = lgdt3305_soft_reset(state);
0665 fail:
0666     return ret;
0667 }
0668 
0669 static int lgdt3304_set_parameters(struct dvb_frontend *fe)
0670 {
0671     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0672     struct lgdt3305_state *state = fe->demodulator_priv;
0673     int ret;
0674 
0675     lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
0676 
0677     if (fe->ops.tuner_ops.set_params) {
0678         ret = fe->ops.tuner_ops.set_params(fe);
0679         if (fe->ops.i2c_gate_ctrl)
0680             fe->ops.i2c_gate_ctrl(fe, 0);
0681         if (lg_fail(ret))
0682             goto fail;
0683         state->current_frequency = p->frequency;
0684     }
0685 
0686     ret = lgdt3305_set_modulation(state, p);
0687     if (lg_fail(ret))
0688         goto fail;
0689 
0690     ret = lgdt3305_passband_digital_agc(state, p);
0691     if (lg_fail(ret))
0692         goto fail;
0693 
0694     ret = lgdt3305_agc_setup(state, p);
0695     if (lg_fail(ret))
0696         goto fail;
0697 
0698     /* reg 0x030d is 3304-only... seen in vsb and qam usbsnoops... */
0699     switch (p->modulation) {
0700     case VSB_8:
0701         lgdt3305_write_reg(state, 0x030d, 0x00);
0702         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f);
0703         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c);
0704         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac);
0705         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba);
0706         break;
0707     case QAM_64:
0708     case QAM_256:
0709         lgdt3305_write_reg(state, 0x030d, 0x14);
0710         ret = lgdt3305_set_if(state, p);
0711         if (lg_fail(ret))
0712             goto fail;
0713         break;
0714     default:
0715         return -EINVAL;
0716     }
0717 
0718 
0719     ret = lgdt3305_spectral_inversion(state, p,
0720                       state->cfg->spectral_inversion
0721                       ? 1 : 0);
0722     if (lg_fail(ret))
0723         goto fail;
0724 
0725     state->current_modulation = p->modulation;
0726 
0727     ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
0728     if (lg_fail(ret))
0729         goto fail;
0730 
0731     /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
0732     ret = lgdt3305_mpeg_mode_polarity(state);
0733 fail:
0734     return ret;
0735 }
0736 
0737 static int lgdt3305_set_parameters(struct dvb_frontend *fe)
0738 {
0739     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0740     struct lgdt3305_state *state = fe->demodulator_priv;
0741     int ret;
0742 
0743     lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
0744 
0745     if (fe->ops.tuner_ops.set_params) {
0746         ret = fe->ops.tuner_ops.set_params(fe);
0747         if (fe->ops.i2c_gate_ctrl)
0748             fe->ops.i2c_gate_ctrl(fe, 0);
0749         if (lg_fail(ret))
0750             goto fail;
0751         state->current_frequency = p->frequency;
0752     }
0753 
0754     ret = lgdt3305_set_modulation(state, p);
0755     if (lg_fail(ret))
0756         goto fail;
0757 
0758     ret = lgdt3305_passband_digital_agc(state, p);
0759     if (lg_fail(ret))
0760         goto fail;
0761     ret = lgdt3305_set_agc_power_ref(state, p);
0762     if (lg_fail(ret))
0763         goto fail;
0764     ret = lgdt3305_agc_setup(state, p);
0765     if (lg_fail(ret))
0766         goto fail;
0767 
0768     /* low if */
0769     ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f);
0770     if (lg_fail(ret))
0771         goto fail;
0772     ret = lgdt3305_set_reg_bit(state, LGDT3305_CR_CTR_FREQ_1, 6, 1);
0773     if (lg_fail(ret))
0774         goto fail;
0775 
0776     ret = lgdt3305_set_if(state, p);
0777     if (lg_fail(ret))
0778         goto fail;
0779     ret = lgdt3305_spectral_inversion(state, p,
0780                       state->cfg->spectral_inversion
0781                       ? 1 : 0);
0782     if (lg_fail(ret))
0783         goto fail;
0784 
0785     ret = lgdt3305_set_filter_extension(state, p);
0786     if (lg_fail(ret))
0787         goto fail;
0788 
0789     state->current_modulation = p->modulation;
0790 
0791     ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
0792     if (lg_fail(ret))
0793         goto fail;
0794 
0795     /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
0796     ret = lgdt3305_mpeg_mode_polarity(state);
0797 fail:
0798     return ret;
0799 }
0800 
0801 static int lgdt3305_get_frontend(struct dvb_frontend *fe,
0802                  struct dtv_frontend_properties *p)
0803 {
0804     struct lgdt3305_state *state = fe->demodulator_priv;
0805 
0806     lg_dbg("\n");
0807 
0808     p->modulation = state->current_modulation;
0809     p->frequency = state->current_frequency;
0810     return 0;
0811 }
0812 
0813 /* ------------------------------------------------------------------------ */
0814 
0815 static int lgdt3305_read_cr_lock_status(struct lgdt3305_state *state,
0816                     int *locked)
0817 {
0818     u8 val;
0819     int ret;
0820     char *cr_lock_state = "";
0821 
0822     *locked = 0;
0823 
0824     ret = lgdt3305_read_reg(state, LGDT3305_CR_LOCK_STATUS, &val);
0825     if (lg_fail(ret))
0826         goto fail;
0827 
0828     switch (state->current_modulation) {
0829     case QAM_256:
0830     case QAM_64:
0831         if (val & (1 << 1))
0832             *locked = 1;
0833 
0834         switch (val & 0x07) {
0835         case 0:
0836             cr_lock_state = "QAM UNLOCK";
0837             break;
0838         case 4:
0839             cr_lock_state = "QAM 1stLock";
0840             break;
0841         case 6:
0842             cr_lock_state = "QAM 2ndLock";
0843             break;
0844         case 7:
0845             cr_lock_state = "QAM FinalLock";
0846             break;
0847         default:
0848             cr_lock_state = "CLOCKQAM-INVALID!";
0849             break;
0850         }
0851         break;
0852     case VSB_8:
0853         if (val & (1 << 7)) {
0854             *locked = 1;
0855             cr_lock_state = "CLOCKVSB";
0856         }
0857         break;
0858     default:
0859         ret = -EINVAL;
0860     }
0861     lg_dbg("(%d) %s\n", *locked, cr_lock_state);
0862 fail:
0863     return ret;
0864 }
0865 
0866 static int lgdt3305_read_fec_lock_status(struct lgdt3305_state *state,
0867                      int *locked)
0868 {
0869     u8 val;
0870     int ret, mpeg_lock, fec_lock, viterbi_lock;
0871 
0872     *locked = 0;
0873 
0874     switch (state->current_modulation) {
0875     case QAM_256:
0876     case QAM_64:
0877         ret = lgdt3305_read_reg(state,
0878                     LGDT3305_FEC_LOCK_STATUS, &val);
0879         if (lg_fail(ret))
0880             goto fail;
0881 
0882         mpeg_lock    = (val & (1 << 0)) ? 1 : 0;
0883         fec_lock     = (val & (1 << 2)) ? 1 : 0;
0884         viterbi_lock = (val & (1 << 3)) ? 1 : 0;
0885 
0886         *locked = mpeg_lock && fec_lock && viterbi_lock;
0887 
0888         lg_dbg("(%d) %s%s%s\n", *locked,
0889                mpeg_lock    ? "mpeg lock  "  : "",
0890                fec_lock     ? "fec lock  "   : "",
0891                viterbi_lock ? "viterbi lock" : "");
0892         break;
0893     case VSB_8:
0894     default:
0895         ret = -EINVAL;
0896     }
0897 fail:
0898     return ret;
0899 }
0900 
0901 static int lgdt3305_read_status(struct dvb_frontend *fe, enum fe_status *status)
0902 {
0903     struct lgdt3305_state *state = fe->demodulator_priv;
0904     u8 val;
0905     int ret, signal, inlock, nofecerr, snrgood,
0906         cr_lock, fec_lock, sync_lock;
0907 
0908     *status = 0;
0909 
0910     ret = lgdt3305_read_reg(state, LGDT3305_GEN_STATUS, &val);
0911     if (lg_fail(ret))
0912         goto fail;
0913 
0914     signal    = (val & (1 << 4)) ? 1 : 0;
0915     inlock    = (val & (1 << 3)) ? 0 : 1;
0916     sync_lock = (val & (1 << 2)) ? 1 : 0;
0917     nofecerr  = (val & (1 << 1)) ? 1 : 0;
0918     snrgood   = (val & (1 << 0)) ? 1 : 0;
0919 
0920     lg_dbg("%s%s%s%s%s\n",
0921            signal    ? "SIGNALEXIST " : "",
0922            inlock    ? "INLOCK "      : "",
0923            sync_lock ? "SYNCLOCK "    : "",
0924            nofecerr  ? "NOFECERR "    : "",
0925            snrgood   ? "SNRGOOD "     : "");
0926 
0927     ret = lgdt3305_read_cr_lock_status(state, &cr_lock);
0928     if (lg_fail(ret))
0929         goto fail;
0930 
0931     if (signal)
0932         *status |= FE_HAS_SIGNAL;
0933     if (cr_lock)
0934         *status |= FE_HAS_CARRIER;
0935     if (nofecerr)
0936         *status |= FE_HAS_VITERBI;
0937     if (sync_lock)
0938         *status |= FE_HAS_SYNC;
0939 
0940     switch (state->current_modulation) {
0941     case QAM_256:
0942     case QAM_64:
0943         /* signal bit is unreliable on the DT3304 in QAM mode */
0944         if (((LGDT3304 == state->cfg->demod_chip)) && (cr_lock))
0945             *status |= FE_HAS_SIGNAL;
0946 
0947         ret = lgdt3305_read_fec_lock_status(state, &fec_lock);
0948         if (lg_fail(ret))
0949             goto fail;
0950 
0951         if (fec_lock)
0952             *status |= FE_HAS_LOCK;
0953         break;
0954     case VSB_8:
0955         if (inlock)
0956             *status |= FE_HAS_LOCK;
0957         break;
0958     default:
0959         ret = -EINVAL;
0960     }
0961 fail:
0962     return ret;
0963 }
0964 
0965 /* ------------------------------------------------------------------------ */
0966 
0967 /* borrowed from lgdt330x.c */
0968 static u32 calculate_snr(u32 mse, u32 c)
0969 {
0970     if (mse == 0) /* no signal */
0971         return 0;
0972 
0973     mse = intlog10(mse);
0974     if (mse > c) {
0975         /* Negative SNR, which is possible, but realisticly the
0976         demod will lose lock before the signal gets this bad.  The
0977         API only allows for unsigned values, so just return 0 */
0978         return 0;
0979     }
0980     return 10*(c - mse);
0981 }
0982 
0983 static int lgdt3305_read_snr(struct dvb_frontend *fe, u16 *snr)
0984 {
0985     struct lgdt3305_state *state = fe->demodulator_priv;
0986     u32 noise;  /* noise value */
0987     u32 c;      /* per-modulation SNR calculation constant */
0988 
0989     switch (state->current_modulation) {
0990     case VSB_8:
0991 #ifdef USE_PTMSE
0992         /* Use Phase Tracker Mean-Square Error Register */
0993         /* SNR for ranges from -13.11 to +44.08 */
0994         noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) |
0995             (read_reg(state, LGDT3305_PT_MSE_2) << 8) |
0996             (read_reg(state, LGDT3305_PT_MSE_3) & 0xff);
0997         c = 73957994; /* log10(25*32^2)*2^24 */
0998 #else
0999         /* Use Equalizer Mean-Square Error Register */
1000         /* SNR for ranges from -16.12 to +44.08 */
1001         noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) |
1002             (read_reg(state, LGDT3305_EQ_MSE_2) << 8) |
1003             (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff);
1004         c = 73957994; /* log10(25*32^2)*2^24 */
1005 #endif
1006         break;
1007     case QAM_64:
1008     case QAM_256:
1009         noise = (read_reg(state, LGDT3305_CR_MSE_1) << 8) |
1010             (read_reg(state, LGDT3305_CR_MSE_2) & 0xff);
1011 
1012         c = (state->current_modulation == QAM_64) ?
1013             97939837 : 98026066;
1014         /* log10(688128)*2^24 and log10(696320)*2^24 */
1015         break;
1016     default:
1017         return -EINVAL;
1018     }
1019     state->snr = calculate_snr(noise, c);
1020     /* report SNR in dB * 10 */
1021     *snr = (state->snr / ((1 << 24) / 10));
1022     lg_dbg("noise = 0x%08x, snr = %d.%02d dB\n", noise,
1023            state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
1024 
1025     return 0;
1026 }
1027 
1028 static int lgdt3305_read_signal_strength(struct dvb_frontend *fe,
1029                      u16 *strength)
1030 {
1031     /* borrowed from lgdt330x.c
1032      *
1033      * Calculate strength from SNR up to 35dB
1034      * Even though the SNR can go higher than 35dB,
1035      * there is some comfort factor in having a range of
1036      * strong signals that can show at 100%
1037      */
1038     struct lgdt3305_state *state = fe->demodulator_priv;
1039     u16 snr;
1040     int ret;
1041 
1042     *strength = 0;
1043 
1044     ret = fe->ops.read_snr(fe, &snr);
1045     if (lg_fail(ret))
1046         goto fail;
1047     /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
1048     /* scale the range 0 - 35*2^24 into 0 - 65535 */
1049     if (state->snr >= 8960 * 0x10000)
1050         *strength = 0xffff;
1051     else
1052         *strength = state->snr / 8960;
1053 fail:
1054     return ret;
1055 }
1056 
1057 /* ------------------------------------------------------------------------ */
1058 
1059 static int lgdt3305_read_ber(struct dvb_frontend *fe, u32 *ber)
1060 {
1061     *ber = 0;
1062     return 0;
1063 }
1064 
1065 static int lgdt3305_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1066 {
1067     struct lgdt3305_state *state = fe->demodulator_priv;
1068 
1069     *ucblocks =
1070         (read_reg(state, LGDT3305_FEC_PKT_ERR_1) << 8) |
1071         (read_reg(state, LGDT3305_FEC_PKT_ERR_2) & 0xff);
1072 
1073     return 0;
1074 }
1075 
1076 static int lgdt3305_get_tune_settings(struct dvb_frontend *fe,
1077                       struct dvb_frontend_tune_settings
1078                     *fe_tune_settings)
1079 {
1080     fe_tune_settings->min_delay_ms = 500;
1081     lg_dbg("\n");
1082     return 0;
1083 }
1084 
1085 static void lgdt3305_release(struct dvb_frontend *fe)
1086 {
1087     struct lgdt3305_state *state = fe->demodulator_priv;
1088     lg_dbg("\n");
1089     kfree(state);
1090 }
1091 
1092 static const struct dvb_frontend_ops lgdt3304_ops;
1093 static const struct dvb_frontend_ops lgdt3305_ops;
1094 
1095 struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config,
1096                      struct i2c_adapter *i2c_adap)
1097 {
1098     struct lgdt3305_state *state = NULL;
1099     int ret;
1100     u8 val;
1101 
1102     lg_dbg("(%d-%04x)\n",
1103            i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1104            config ? config->i2c_addr : 0);
1105 
1106     state = kzalloc(sizeof(struct lgdt3305_state), GFP_KERNEL);
1107     if (state == NULL)
1108         goto fail;
1109 
1110     state->cfg = config;
1111     state->i2c_adap = i2c_adap;
1112 
1113     switch (config->demod_chip) {
1114     case LGDT3304:
1115         memcpy(&state->frontend.ops, &lgdt3304_ops,
1116                sizeof(struct dvb_frontend_ops));
1117         break;
1118     case LGDT3305:
1119         memcpy(&state->frontend.ops, &lgdt3305_ops,
1120                sizeof(struct dvb_frontend_ops));
1121         break;
1122     default:
1123         goto fail;
1124     }
1125     state->frontend.demodulator_priv = state;
1126 
1127     /* verify that we're talking to a lg dt3304/5 */
1128     ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_2, &val);
1129     if ((lg_fail(ret)) | (val == 0))
1130         goto fail;
1131     ret = lgdt3305_write_reg(state, 0x0808, 0x80);
1132     if (lg_fail(ret))
1133         goto fail;
1134     ret = lgdt3305_read_reg(state, 0x0808, &val);
1135     if ((lg_fail(ret)) | (val != 0x80))
1136         goto fail;
1137     ret = lgdt3305_write_reg(state, 0x0808, 0x00);
1138     if (lg_fail(ret))
1139         goto fail;
1140 
1141     state->current_frequency = -1;
1142     state->current_modulation = -1;
1143 
1144     return &state->frontend;
1145 fail:
1146     lg_warn("unable to detect %s hardware\n",
1147         config->demod_chip ? "LGDT3304" : "LGDT3305");
1148     kfree(state);
1149     return NULL;
1150 }
1151 EXPORT_SYMBOL(lgdt3305_attach);
1152 
1153 static const struct dvb_frontend_ops lgdt3304_ops = {
1154     .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1155     .info = {
1156         .name = "LG Electronics LGDT3304 VSB/QAM Frontend",
1157         .frequency_min_hz      =  54 * MHz,
1158         .frequency_max_hz      = 858 * MHz,
1159         .frequency_stepsize_hz = 62500,
1160         .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
1161     },
1162     .i2c_gate_ctrl        = lgdt3305_i2c_gate_ctrl,
1163     .init                 = lgdt3305_init,
1164     .sleep                = lgdt3305_sleep,
1165     .set_frontend         = lgdt3304_set_parameters,
1166     .get_frontend         = lgdt3305_get_frontend,
1167     .get_tune_settings    = lgdt3305_get_tune_settings,
1168     .read_status          = lgdt3305_read_status,
1169     .read_ber             = lgdt3305_read_ber,
1170     .read_signal_strength = lgdt3305_read_signal_strength,
1171     .read_snr             = lgdt3305_read_snr,
1172     .read_ucblocks        = lgdt3305_read_ucblocks,
1173     .release              = lgdt3305_release,
1174 };
1175 
1176 static const struct dvb_frontend_ops lgdt3305_ops = {
1177     .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1178     .info = {
1179         .name = "LG Electronics LGDT3305 VSB/QAM Frontend",
1180         .frequency_min_hz      =  54 * MHz,
1181         .frequency_max_hz      = 858 * MHz,
1182         .frequency_stepsize_hz = 62500,
1183         .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
1184     },
1185     .i2c_gate_ctrl        = lgdt3305_i2c_gate_ctrl,
1186     .init                 = lgdt3305_init,
1187     .sleep                = lgdt3305_sleep,
1188     .set_frontend         = lgdt3305_set_parameters,
1189     .get_frontend         = lgdt3305_get_frontend,
1190     .get_tune_settings    = lgdt3305_get_tune_settings,
1191     .read_status          = lgdt3305_read_status,
1192     .read_ber             = lgdt3305_read_ber,
1193     .read_signal_strength = lgdt3305_read_signal_strength,
1194     .read_snr             = lgdt3305_read_snr,
1195     .read_ucblocks        = lgdt3305_read_ucblocks,
1196     .release              = lgdt3305_release,
1197 };
1198 
1199 MODULE_DESCRIPTION("LG Electronics LGDT3304/5 ATSC/QAM-B Demodulator Driver");
1200 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
1201 MODULE_LICENSE("GPL");
1202 MODULE_VERSION("0.2");
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