Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003     driver for LSI L64781 COFDM demodulator
0004 
0005     Copyright (C) 2001 Holger Waechtler for Convergence Integrated Media GmbH
0006                Marko Kohtala <marko.kohtala@luukku.com>
0007 
0008 
0009 */
0010 
0011 #include <linux/init.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/string.h>
0015 #include <linux/slab.h>
0016 #include <media/dvb_frontend.h>
0017 #include "l64781.h"
0018 
0019 
0020 struct l64781_state {
0021     struct i2c_adapter* i2c;
0022     const struct l64781_config* config;
0023     struct dvb_frontend frontend;
0024 
0025     /* private demodulator data */
0026     unsigned int first:1;
0027 };
0028 
0029 #define dprintk(args...) \
0030     do { \
0031         if (debug) printk(KERN_DEBUG "l64781: " args); \
0032     } while (0)
0033 
0034 static int debug;
0035 
0036 module_param(debug, int, 0644);
0037 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
0038 
0039 
0040 static int l64781_writereg (struct l64781_state* state, u8 reg, u8 data)
0041 {
0042     int ret;
0043     u8 buf [] = { reg, data };
0044     struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
0045 
0046     if ((ret = i2c_transfer(state->i2c, &msg, 1)) != 1)
0047         dprintk ("%s: write_reg error (reg == %02x) = %02x!\n",
0048              __func__, reg, ret);
0049 
0050     return (ret != 1) ? -1 : 0;
0051 }
0052 
0053 static int l64781_readreg (struct l64781_state* state, u8 reg)
0054 {
0055     int ret;
0056     u8 b0 [] = { reg };
0057     u8 b1 [] = { 0 };
0058     struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
0059                { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
0060 
0061     ret = i2c_transfer(state->i2c, msg, 2);
0062 
0063     if (ret != 2) return ret;
0064 
0065     return b1[0];
0066 }
0067 
0068 static void apply_tps (struct l64781_state* state)
0069 {
0070     l64781_writereg (state, 0x2a, 0x00);
0071     l64781_writereg (state, 0x2a, 0x01);
0072 
0073     /* This here is a little bit questionable because it enables
0074        the automatic update of TPS registers. I think we'd need to
0075        handle the IRQ from FE to update some other registers as
0076        well, or at least implement some magic to tuning to correct
0077        to the TPS received from transmission. */
0078     l64781_writereg (state, 0x2a, 0x02);
0079 }
0080 
0081 
0082 static void reset_afc (struct l64781_state* state)
0083 {
0084     /* Set AFC stall for the AFC_INIT_FRQ setting, TIM_STALL for
0085        timing offset */
0086     l64781_writereg (state, 0x07, 0x9e); /* stall AFC */
0087     l64781_writereg (state, 0x08, 0);    /* AFC INIT FREQ */
0088     l64781_writereg (state, 0x09, 0);
0089     l64781_writereg (state, 0x0a, 0);
0090     l64781_writereg (state, 0x07, 0x8e);
0091     l64781_writereg (state, 0x0e, 0);    /* AGC gain to zero in beginning */
0092     l64781_writereg (state, 0x11, 0x80); /* stall TIM */
0093     l64781_writereg (state, 0x10, 0);    /* TIM_OFFSET_LSB */
0094     l64781_writereg (state, 0x12, 0);
0095     l64781_writereg (state, 0x13, 0);
0096     l64781_writereg (state, 0x11, 0x00);
0097 }
0098 
0099 static int reset_and_configure (struct l64781_state* state)
0100 {
0101     u8 buf [] = { 0x06 };
0102     struct i2c_msg msg = { .addr = 0x00, .flags = 0, .buf = buf, .len = 1 };
0103     // NOTE: this is correct in writing to address 0x00
0104 
0105     return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV;
0106 }
0107 
0108 static int apply_frontend_param(struct dvb_frontend *fe)
0109 {
0110     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0111     struct l64781_state* state = fe->demodulator_priv;
0112     /* The coderates for FEC_NONE, FEC_4_5 and FEC_FEC_6_7 are arbitrary */
0113     static const u8 fec_tab[] = { 7, 0, 1, 2, 9, 3, 10, 4 };
0114     /* QPSK, QAM_16, QAM_64 */
0115     static const u8 qam_tab [] = { 2, 4, 0, 6 };
0116     static const u8 guard_tab [] = { 1, 2, 4, 8 };
0117     /* The Grundig 29504-401.04 Tuner comes with 18.432MHz crystal. */
0118     static const u32 ppm = 8000;
0119     u32 ddfs_offset_fixed;
0120 /*  u32 ddfs_offset_variable = 0x6000-((1000000UL+ppm)/ */
0121 /*          bw_tab[p->bandWidth]<<10)/15625; */
0122     u32 init_freq;
0123     u32 spi_bias;
0124     u8 val0x04;
0125     u8 val0x05;
0126     u8 val0x06;
0127     int bw;
0128 
0129     switch (p->bandwidth_hz) {
0130     case 8000000:
0131         bw = 8;
0132         break;
0133     case 7000000:
0134         bw = 7;
0135         break;
0136     case 6000000:
0137         bw = 6;
0138         break;
0139     default:
0140         return -EINVAL;
0141     }
0142 
0143     if (fe->ops.tuner_ops.set_params) {
0144         fe->ops.tuner_ops.set_params(fe);
0145         if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
0146     }
0147 
0148     if (p->inversion != INVERSION_ON &&
0149         p->inversion != INVERSION_OFF)
0150         return -EINVAL;
0151 
0152     if (p->code_rate_HP != FEC_1_2 && p->code_rate_HP != FEC_2_3 &&
0153         p->code_rate_HP != FEC_3_4 && p->code_rate_HP != FEC_5_6 &&
0154         p->code_rate_HP != FEC_7_8)
0155         return -EINVAL;
0156 
0157     if (p->hierarchy != HIERARCHY_NONE &&
0158         (p->code_rate_LP != FEC_1_2 && p->code_rate_LP != FEC_2_3 &&
0159          p->code_rate_LP != FEC_3_4 && p->code_rate_LP != FEC_5_6 &&
0160          p->code_rate_LP != FEC_7_8))
0161         return -EINVAL;
0162 
0163     if (p->modulation != QPSK && p->modulation != QAM_16 &&
0164         p->modulation != QAM_64)
0165         return -EINVAL;
0166 
0167     if (p->transmission_mode != TRANSMISSION_MODE_2K &&
0168         p->transmission_mode != TRANSMISSION_MODE_8K)
0169         return -EINVAL;
0170 
0171     if ((int)p->guard_interval < GUARD_INTERVAL_1_32 ||
0172         p->guard_interval > GUARD_INTERVAL_1_4)
0173         return -EINVAL;
0174 
0175     if ((int)p->hierarchy < HIERARCHY_NONE ||
0176         p->hierarchy > HIERARCHY_4)
0177         return -EINVAL;
0178 
0179     ddfs_offset_fixed = 0x4000-(ppm<<16)/bw/1000000;
0180 
0181     /* This works up to 20000 ppm, it overflows if too large ppm! */
0182     init_freq = (((8UL<<25) + (8UL<<19) / 25*ppm / (15625/25)) /
0183             bw & 0xFFFFFF);
0184 
0185     /* SPI bias calculation is slightly modified to fit in 32bit */
0186     /* will work for high ppm only... */
0187     spi_bias = 378 * (1 << 10);
0188     spi_bias *= 16;
0189     spi_bias *= bw;
0190     spi_bias *= qam_tab[p->modulation];
0191     spi_bias /= p->code_rate_HP + 1;
0192     spi_bias /= (guard_tab[p->guard_interval] + 32);
0193     spi_bias *= 1000;
0194     spi_bias /= 1000 + ppm/1000;
0195     spi_bias *= p->code_rate_HP;
0196 
0197     val0x04 = (p->transmission_mode << 2) | p->guard_interval;
0198     val0x05 = fec_tab[p->code_rate_HP];
0199 
0200     if (p->hierarchy != HIERARCHY_NONE)
0201         val0x05 |= (p->code_rate_LP - FEC_1_2) << 3;
0202 
0203     val0x06 = (p->hierarchy << 2) | p->modulation;
0204 
0205     l64781_writereg (state, 0x04, val0x04);
0206     l64781_writereg (state, 0x05, val0x05);
0207     l64781_writereg (state, 0x06, val0x06);
0208 
0209     reset_afc (state);
0210 
0211     /* Technical manual section 2.6.1, TIM_IIR_GAIN optimal values */
0212     l64781_writereg (state, 0x15,
0213              p->transmission_mode == TRANSMISSION_MODE_2K ? 1 : 3);
0214     l64781_writereg (state, 0x16, init_freq & 0xff);
0215     l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff);
0216     l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff);
0217 
0218     l64781_writereg (state, 0x1b, spi_bias & 0xff);
0219     l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff);
0220     l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) |
0221         (p->inversion == INVERSION_ON ? 0x80 : 0x00));
0222 
0223     l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff);
0224     l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f);
0225 
0226     l64781_readreg (state, 0x00);  /*  clear interrupt registers... */
0227     l64781_readreg (state, 0x01);  /*  dto. */
0228 
0229     apply_tps (state);
0230 
0231     return 0;
0232 }
0233 
0234 static int get_frontend(struct dvb_frontend *fe,
0235             struct dtv_frontend_properties *p)
0236 {
0237     struct l64781_state* state = fe->demodulator_priv;
0238     int tmp;
0239 
0240 
0241     tmp = l64781_readreg(state, 0x04);
0242     switch(tmp & 3) {
0243     case 0:
0244         p->guard_interval = GUARD_INTERVAL_1_32;
0245         break;
0246     case 1:
0247         p->guard_interval = GUARD_INTERVAL_1_16;
0248         break;
0249     case 2:
0250         p->guard_interval = GUARD_INTERVAL_1_8;
0251         break;
0252     case 3:
0253         p->guard_interval = GUARD_INTERVAL_1_4;
0254         break;
0255     }
0256     switch((tmp >> 2) & 3) {
0257     case 0:
0258         p->transmission_mode = TRANSMISSION_MODE_2K;
0259         break;
0260     case 1:
0261         p->transmission_mode = TRANSMISSION_MODE_8K;
0262         break;
0263     default:
0264         printk(KERN_WARNING "Unexpected value for transmission_mode\n");
0265     }
0266 
0267     tmp = l64781_readreg(state, 0x05);
0268     switch(tmp & 7) {
0269     case 0:
0270         p->code_rate_HP = FEC_1_2;
0271         break;
0272     case 1:
0273         p->code_rate_HP = FEC_2_3;
0274         break;
0275     case 2:
0276         p->code_rate_HP = FEC_3_4;
0277         break;
0278     case 3:
0279         p->code_rate_HP = FEC_5_6;
0280         break;
0281     case 4:
0282         p->code_rate_HP = FEC_7_8;
0283         break;
0284     default:
0285         printk("Unexpected value for code_rate_HP\n");
0286     }
0287     switch((tmp >> 3) & 7) {
0288     case 0:
0289         p->code_rate_LP = FEC_1_2;
0290         break;
0291     case 1:
0292         p->code_rate_LP = FEC_2_3;
0293         break;
0294     case 2:
0295         p->code_rate_LP = FEC_3_4;
0296         break;
0297     case 3:
0298         p->code_rate_LP = FEC_5_6;
0299         break;
0300     case 4:
0301         p->code_rate_LP = FEC_7_8;
0302         break;
0303     default:
0304         printk("Unexpected value for code_rate_LP\n");
0305     }
0306 
0307     tmp = l64781_readreg(state, 0x06);
0308     switch(tmp & 3) {
0309     case 0:
0310         p->modulation = QPSK;
0311         break;
0312     case 1:
0313         p->modulation = QAM_16;
0314         break;
0315     case 2:
0316         p->modulation = QAM_64;
0317         break;
0318     default:
0319         printk(KERN_WARNING "Unexpected value for modulation\n");
0320     }
0321     switch((tmp >> 2) & 7) {
0322     case 0:
0323         p->hierarchy = HIERARCHY_NONE;
0324         break;
0325     case 1:
0326         p->hierarchy = HIERARCHY_1;
0327         break;
0328     case 2:
0329         p->hierarchy = HIERARCHY_2;
0330         break;
0331     case 3:
0332         p->hierarchy = HIERARCHY_4;
0333         break;
0334     default:
0335         printk("Unexpected value for hierarchy\n");
0336     }
0337 
0338 
0339     tmp = l64781_readreg (state, 0x1d);
0340     p->inversion = (tmp & 0x80) ? INVERSION_ON : INVERSION_OFF;
0341 
0342     tmp = (int) (l64781_readreg (state, 0x08) |
0343              (l64781_readreg (state, 0x09) << 8) |
0344              (l64781_readreg (state, 0x0a) << 16));
0345     p->frequency += tmp;
0346 
0347     return 0;
0348 }
0349 
0350 static int l64781_read_status(struct dvb_frontend *fe, enum fe_status *status)
0351 {
0352     struct l64781_state* state = fe->demodulator_priv;
0353     int sync = l64781_readreg (state, 0x32);
0354     int gain = l64781_readreg (state, 0x0e);
0355 
0356     l64781_readreg (state, 0x00);  /*  clear interrupt registers... */
0357     l64781_readreg (state, 0x01);  /*  dto. */
0358 
0359     *status = 0;
0360 
0361     if (gain > 5)
0362         *status |= FE_HAS_SIGNAL;
0363 
0364     if (sync & 0x02) /* VCXO locked, this criteria should be ok */
0365         *status |= FE_HAS_CARRIER;
0366 
0367     if (sync & 0x20)
0368         *status |= FE_HAS_VITERBI;
0369 
0370     if (sync & 0x40)
0371         *status |= FE_HAS_SYNC;
0372 
0373     if (sync == 0x7f)
0374         *status |= FE_HAS_LOCK;
0375 
0376     return 0;
0377 }
0378 
0379 static int l64781_read_ber(struct dvb_frontend* fe, u32* ber)
0380 {
0381     struct l64781_state* state = fe->demodulator_priv;
0382 
0383     /*   XXX FIXME: set up counting period (reg 0x26...0x28)
0384      */
0385     *ber = l64781_readreg (state, 0x39)
0386         | (l64781_readreg (state, 0x3a) << 8);
0387 
0388     return 0;
0389 }
0390 
0391 static int l64781_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
0392 {
0393     struct l64781_state* state = fe->demodulator_priv;
0394 
0395     u8 gain = l64781_readreg (state, 0x0e);
0396     *signal_strength = (gain << 8) | gain;
0397 
0398     return 0;
0399 }
0400 
0401 static int l64781_read_snr(struct dvb_frontend* fe, u16* snr)
0402 {
0403     struct l64781_state* state = fe->demodulator_priv;
0404 
0405     u8 avg_quality = 0xff - l64781_readreg (state, 0x33);
0406     *snr = (avg_quality << 8) | avg_quality; /* not exact, but...*/
0407 
0408     return 0;
0409 }
0410 
0411 static int l64781_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
0412 {
0413     struct l64781_state* state = fe->demodulator_priv;
0414 
0415     *ucblocks = l64781_readreg (state, 0x37)
0416        | (l64781_readreg (state, 0x38) << 8);
0417 
0418     return 0;
0419 }
0420 
0421 static int l64781_sleep(struct dvb_frontend* fe)
0422 {
0423     struct l64781_state* state = fe->demodulator_priv;
0424 
0425     /* Power down */
0426     return l64781_writereg (state, 0x3e, 0x5a);
0427 }
0428 
0429 static int l64781_init(struct dvb_frontend* fe)
0430 {
0431     struct l64781_state* state = fe->demodulator_priv;
0432 
0433     reset_and_configure (state);
0434 
0435     /* Power up */
0436     l64781_writereg (state, 0x3e, 0xa5);
0437 
0438     /* Reset hard */
0439     l64781_writereg (state, 0x2a, 0x04);
0440     l64781_writereg (state, 0x2a, 0x00);
0441 
0442     /* Set tuner specific things */
0443     /* AFC_POL, set also in reset_afc */
0444     l64781_writereg (state, 0x07, 0x8e);
0445 
0446     /* Use internal ADC */
0447     l64781_writereg (state, 0x0b, 0x81);
0448 
0449     /* AGC loop gain, and polarity is positive */
0450     l64781_writereg (state, 0x0c, 0x84);
0451 
0452     /* Internal ADC outputs two's complement */
0453     l64781_writereg (state, 0x0d, 0x8c);
0454 
0455     /* With ppm=8000, it seems the DTR_SENSITIVITY will result in
0456        value of 2 with all possible bandwidths and guard
0457        intervals, which is the initial value anyway. */
0458     /*l64781_writereg (state, 0x19, 0x92);*/
0459 
0460     /* Everything is two's complement, soft bit and CSI_OUT too */
0461     l64781_writereg (state, 0x1e, 0x09);
0462 
0463     /* delay a bit after first init attempt */
0464     if (state->first) {
0465         state->first = 0;
0466         msleep(200);
0467     }
0468 
0469     return 0;
0470 }
0471 
0472 static int l64781_get_tune_settings(struct dvb_frontend* fe,
0473                     struct dvb_frontend_tune_settings* fesettings)
0474 {
0475     fesettings->min_delay_ms = 4000;
0476     fesettings->step_size = 0;
0477     fesettings->max_drift = 0;
0478     return 0;
0479 }
0480 
0481 static void l64781_release(struct dvb_frontend* fe)
0482 {
0483     struct l64781_state* state = fe->demodulator_priv;
0484     kfree(state);
0485 }
0486 
0487 static const struct dvb_frontend_ops l64781_ops;
0488 
0489 struct dvb_frontend* l64781_attach(const struct l64781_config* config,
0490                    struct i2c_adapter* i2c)
0491 {
0492     struct l64781_state* state = NULL;
0493     int reg0x3e = -1;
0494     u8 b0 [] = { 0x1a };
0495     u8 b1 [] = { 0x00 };
0496     struct i2c_msg msg [] = { { .addr = config->demod_address, .flags = 0, .buf = b0, .len = 1 },
0497                { .addr = config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
0498 
0499     /* allocate memory for the internal state */
0500     state = kzalloc(sizeof(struct l64781_state), GFP_KERNEL);
0501     if (state == NULL) goto error;
0502 
0503     /* setup the state */
0504     state->config = config;
0505     state->i2c = i2c;
0506     state->first = 1;
0507 
0508     /*
0509      *  the L64781 won't show up before we send the reset_and_configure()
0510      *  broadcast. If nothing responds there is no L64781 on the bus...
0511      */
0512     if (reset_and_configure(state) < 0) {
0513         dprintk("No response to reset and configure broadcast...\n");
0514         goto error;
0515     }
0516 
0517     /* The chip always responds to reads */
0518     if (i2c_transfer(state->i2c, msg, 2) != 2) {
0519         dprintk("No response to read on I2C bus\n");
0520         goto error;
0521     }
0522 
0523     /* Save current register contents for bailout */
0524     reg0x3e = l64781_readreg(state, 0x3e);
0525 
0526     /* Reading the POWER_DOWN register always returns 0 */
0527     if (reg0x3e != 0) {
0528         dprintk("Device doesn't look like L64781\n");
0529         goto error;
0530     }
0531 
0532     /* Turn the chip off */
0533     l64781_writereg (state, 0x3e, 0x5a);
0534 
0535     /* Responds to all reads with 0 */
0536     if (l64781_readreg(state, 0x1a) != 0) {
0537         dprintk("Read 1 returned unexpected value\n");
0538         goto error;
0539     }
0540 
0541     /* Turn the chip on */
0542     l64781_writereg (state, 0x3e, 0xa5);
0543 
0544     /* Responds with register default value */
0545     if (l64781_readreg(state, 0x1a) != 0xa1) {
0546         dprintk("Read 2 returned unexpected value\n");
0547         goto error;
0548     }
0549 
0550     /* create dvb_frontend */
0551     memcpy(&state->frontend.ops, &l64781_ops, sizeof(struct dvb_frontend_ops));
0552     state->frontend.demodulator_priv = state;
0553     return &state->frontend;
0554 
0555 error:
0556     if (reg0x3e >= 0)
0557         l64781_writereg (state, 0x3e, reg0x3e);  /* restore reg 0x3e */
0558     kfree(state);
0559     return NULL;
0560 }
0561 
0562 static const struct dvb_frontend_ops l64781_ops = {
0563     .delsys = { SYS_DVBT },
0564     .info = {
0565         .name = "LSI L64781 DVB-T",
0566     /*  .frequency_min_hz = ???,*/
0567     /*  .frequency_max_hz = ???,*/
0568         .frequency_stepsize_hz = 166666,
0569     /*      .symbol_rate_tolerance = ???,*/
0570         .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
0571               FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
0572               FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
0573               FE_CAN_MUTE_TS
0574     },
0575 
0576     .release = l64781_release,
0577 
0578     .init = l64781_init,
0579     .sleep = l64781_sleep,
0580 
0581     .set_frontend = apply_frontend_param,
0582     .get_frontend = get_frontend,
0583     .get_tune_settings = l64781_get_tune_settings,
0584 
0585     .read_status = l64781_read_status,
0586     .read_ber = l64781_read_ber,
0587     .read_signal_strength = l64781_read_signal_strength,
0588     .read_snr = l64781_read_snr,
0589     .read_ucblocks = l64781_read_ucblocks,
0590 };
0591 
0592 MODULE_DESCRIPTION("LSI L64781 DVB-T Demodulator driver");
0593 MODULE_AUTHOR("Holger Waechtler, Marko Kohtala");
0594 MODULE_LICENSE("GPL");
0595 
0596 EXPORT_SYMBOL(l64781_attach);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!