media/dvb-frontends/itd1000.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Driver for the Integrant ITD1000 "Zero-IF Tuner IC for Direct Broadcast Satellite"
0004  *
0005  *  Copyright (c) 2007-8 Patrick Boettcher <pb@linuxtv.org>
0006  */
0007
0008 #include <linux/module.h>
0009 #include <linux/moduleparam.h>
0010 #include <linux/delay.h>
0011 #include <linux/dvb/frontend.h>
0012 #include <linux/i2c.h>
0013 #include <linux/slab.h>
0014
0015 #include <media/dvb_frontend.h>
0016
0017 #include "itd1000.h"
0018 #include "itd1000_priv.h"
0019
0020 /* Max transfer size done by I2C transfer functions */
0021 #define MAX_XFER_SIZE  64
0022
0023 static int debug;
0024 module_param(debug, int, 0644);
0025 MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
0026
0027 #define itd_dbg(args...)  do { \
0028     if (debug) { \
0029         printk(KERN_DEBUG   "ITD1000: " args);\
0030     } \
0031 } while (0)
0032
0033 #define itd_warn(args...) do { \
0034     printk(KERN_WARNING "ITD1000: " args); \
0035 } while (0)
0036
0037 #define itd_info(args...) do { \
0038     printk(KERN_INFO    "ITD1000: " args); \
0039 } while (0)
0040
0041 /* don't write more than one byte with flexcop behind */
0042 static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len)
0043 {
0044     u8 buf[MAX_XFER_SIZE];
0045     struct i2c_msg msg = {
0046         .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1
0047     };
0048
0049     if (1 + len > sizeof(buf)) {
0050         printk(KERN_WARNING
0051                "itd1000: i2c wr reg=%04x: len=%d is too big!\n",
0052                reg, len);
0053         return -EINVAL;
0054     }
0055
0056     buf[0] = reg;
0057     memcpy(&buf[1], v, len);
0058
0059     /* itd_dbg("wr %02x: %02x\n", reg, v[0]); */
0060
0061     if (i2c_transfer(state->i2c, &msg, 1) != 1) {
0062         printk(KERN_WARNING "itd1000 I2C write failed\n");
0063         return -EREMOTEIO;
0064     }
0065     return 0;
0066 }
0067
0068 static int itd1000_read_reg(struct itd1000_state *state, u8 reg)
0069 {
0070     u8 val;
0071     struct i2c_msg msg[2] = {
0072         { .addr = state->cfg->i2c_address, .flags = 0,        .buf = &reg, .len = 1 },
0073         { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = &val, .len = 1 },
0074     };
0075
0076     /* ugly flexcop workaround */
0077     itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1);
0078
0079     if (i2c_transfer(state->i2c, msg, 2) != 2) {
0080         itd_warn("itd1000 I2C read failed\n");
0081         return -EREMOTEIO;
0082     }
0083     return val;
0084 }
0085
0086 static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v)
0087 {
0088     u8 tmp = v; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
0089     int ret = itd1000_write_regs(state, r, &tmp, 1);
0090     state->shadow[r] = tmp;
0091     return ret;
0092 }
0093
0094
0095 static struct {
0096     u32 symbol_rate;
0097     u8  pgaext  : 4; /* PLLFH */
0098     u8  bbgvmin : 4; /* BBGVMIN */
0099 } itd1000_lpf_pga[] = {
0100     {        0, 0x8, 0x3 },
0101     {  5200000, 0x8, 0x3 },
0102     { 12200000, 0x4, 0x3 },
0103     { 15400000, 0x2, 0x3 },
0104     { 19800000, 0x2, 0x3 },
0105     { 21500000, 0x2, 0x3 },
0106     { 24500000, 0x2, 0x3 },
0107     { 28400000, 0x2, 0x3 },
0108     { 33400000, 0x2, 0x3 },
0109     { 34400000, 0x1, 0x4 },
0110     { 34400000, 0x1, 0x4 },
0111     { 38400000, 0x1, 0x4 },
0112     { 38400000, 0x1, 0x4 },
0113     { 40400000, 0x1, 0x4 },
0114     { 45400000, 0x1, 0x4 },
0115 };
0116
0117 static void itd1000_set_lpf_bw(struct itd1000_state *state, u32 symbol_rate)
0118 {
0119     u8 i;
0120     u8 con1    = itd1000_read_reg(state, CON1)    & 0xfd;
0121     u8 pllfh   = itd1000_read_reg(state, PLLFH)   & 0x0f;
0122     u8 bbgvmin = itd1000_read_reg(state, BBGVMIN) & 0xf0;
0123     u8 bw      = itd1000_read_reg(state, BW)      & 0xf0;
0124
0125     itd_dbg("symbol_rate = %d\n", symbol_rate);
0126
0127     /* not sure what is that ? - starting to download the table */
0128     itd1000_write_reg(state, CON1, con1 | (1 << 1));
0129
0130     for (i = 0; i < ARRAY_SIZE(itd1000_lpf_pga); i++)
0131         if (symbol_rate < itd1000_lpf_pga[i].symbol_rate) {
0132             itd_dbg("symrate: index: %d pgaext: %x, bbgvmin: %x\n", i, itd1000_lpf_pga[i].pgaext, itd1000_lpf_pga[i].bbgvmin);
0133             itd1000_write_reg(state, PLLFH,   pllfh | (itd1000_lpf_pga[i].pgaext << 4));
0134             itd1000_write_reg(state, BBGVMIN, bbgvmin | (itd1000_lpf_pga[i].bbgvmin));
0135             itd1000_write_reg(state, BW,      bw | (i & 0x0f));
0136             break;
0137         }
0138
0139     itd1000_write_reg(state, CON1, con1 | (0 << 1));
0140 }
0141
0142 static struct {
0143     u8 vcorg;
0144     u32 fmax_rg;
0145 } itd1000_vcorg[] = {
0146     {  1,  920000 },
0147     {  2,  971000 },
0148     {  3, 1031000 },
0149     {  4, 1091000 },
0150     {  5, 1171000 },
0151     {  6, 1281000 },
0152     {  7, 1381000 },
0153     {  8,  500000 },    /* this is intentional. */
0154     {  9, 1451000 },
0155     { 10, 1531000 },
0156     { 11, 1631000 },
0157     { 12, 1741000 },
0158     { 13, 1891000 },
0159     { 14, 2071000 },
0160     { 15, 2250000 },
0161 };
0162
0163 static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz)
0164 {
0165     u8 i;
0166     u8 gvbb_i2c     = itd1000_read_reg(state, GVBB_I2C) & 0xbf;
0167     u8 vco_chp1_i2c = itd1000_read_reg(state, VCO_CHP1_I2C) & 0x0f;
0168     u8 adcout;
0169
0170     /* reserved bit again (reset ?) */
0171     itd1000_write_reg(state, GVBB_I2C, gvbb_i2c | (1 << 6));
0172
0173     for (i = 0; i < ARRAY_SIZE(itd1000_vcorg); i++) {
0174         if (freq_khz < itd1000_vcorg[i].fmax_rg) {
0175             itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | (itd1000_vcorg[i].vcorg << 4));
0176             msleep(1);
0177
0178             adcout = itd1000_read_reg(state, PLLLOCK) & 0x0f;
0179
0180             itd_dbg("VCO: %dkHz: %d -> ADCOUT: %d %02x\n", freq_khz, itd1000_vcorg[i].vcorg, adcout, vco_chp1_i2c);
0181
0182             if (adcout > 13) {
0183                 if (!(itd1000_vcorg[i].vcorg == 7 || itd1000_vcorg[i].vcorg == 15))
0184                     itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg + 1) << 4));
0185             } else if (adcout < 2) {
0186                 if (!(itd1000_vcorg[i].vcorg == 1 || itd1000_vcorg[i].vcorg == 9))
0187                     itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg - 1) << 4));
0188             }
0189             break;
0190         }
0191     }
0192 }
0193
0194 static const struct {
0195     u32 freq;
0196     u8 values[10]; /* RFTR, RFST1 - RFST9 */
0197 } itd1000_fre_values[] = {
0198     { 1075000, { 0x59, 0x1d, 0x1c, 0x17, 0x16, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
0199     { 1250000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
0200     { 1450000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
0201     { 1650000, { 0x69, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
0202     { 1750000, { 0x69, 0x1e, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
0203     { 1850000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
0204     { 1900000, { 0x69, 0x1d, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
0205     { 1950000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0d, 0x0b, 0x0a } },
0206     { 2050000, { 0x69, 0x1e, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0b, 0x0a } },
0207     { 2150000, { 0x69, 0x1d, 0x1c, 0x17, 0x15, 0x14, 0x13, 0x0f, 0x0e, 0x0b } }
0208 };
0209
0210
0211 #define FREF 16
0212
0213 static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz)
0214 {
0215     int i, j;
0216     u32 plln, pllf;
0217     u64 tmp;
0218
0219     plln = (freq_khz * 1000) / 2 / FREF;
0220
0221     /* Compute the factional part times 1000 */
0222     tmp  = plln % 1000000;
0223     plln /= 1000000;
0224
0225     tmp *= 1048576;
0226     do_div(tmp, 1000000);
0227     pllf = (u32) tmp;
0228
0229     state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF;
0230     itd_dbg("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d\n", freq_khz, state->frequency, pllf, plln);
0231
0232     itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */
0233     itd1000_write_reg(state, PLLNL, plln & 0xff);
0234     itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f));
0235     itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff);
0236     itd1000_write_reg(state, PLLFL, (pllf >> 0) & 0xff);
0237
0238     for (i = 0; i < ARRAY_SIZE(itd1000_fre_values); i++) {
0239         if (freq_khz <= itd1000_fre_values[i].freq) {
0240             itd_dbg("fre_values: %d\n", i);
0241             itd1000_write_reg(state, RFTR, itd1000_fre_values[i].values[0]);
0242             for (j = 0; j < 9; j++)
0243                 itd1000_write_reg(state, RFST1+j, itd1000_fre_values[i].values[j+1]);
0244             break;
0245         }
0246     }
0247
0248     itd1000_set_vco(state, freq_khz);
0249 }
0250
0251 static int itd1000_set_parameters(struct dvb_frontend *fe)
0252 {
0253     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0254     struct itd1000_state *state = fe->tuner_priv;
0255     u8 pllcon1;
0256
0257     itd1000_set_lo(state, c->frequency);
0258     itd1000_set_lpf_bw(state, c->symbol_rate);
0259
0260     pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f;
0261     itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7));
0262     itd1000_write_reg(state, PLLCON1, pllcon1);
0263
0264     return 0;
0265 }
0266
0267 static int itd1000_get_frequency(struct dvb_frontend *fe, u32 *frequency)
0268 {
0269     struct itd1000_state *state = fe->tuner_priv;
0270     *frequency = state->frequency;
0271     return 0;
0272 }
0273
0274 static int itd1000_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
0275 {
0276     return 0;
0277 }
0278
0279 static u8 itd1000_init_tab[][2] = {
0280     { PLLCON1,       0x65 }, /* Register does not change */
0281     { PLLNH,         0x80 }, /* Bits [7:6] do not change */
0282     { RESERVED_0X6D, 0x3b },
0283     { VCO_CHP2_I2C,  0x12 },
0284     { 0x72,          0xf9 }, /* No such regsister defined */
0285     { RESERVED_0X73, 0xff },
0286     { RESERVED_0X74, 0xb2 },
0287     { RESERVED_0X75, 0xc7 },
0288     { EXTGVBBRF,     0xf0 },
0289     { DIVAGCCK,      0x80 },
0290     { BBTR,          0xa0 },
0291     { RESERVED_0X7E, 0x4f },
0292     { 0x82,          0x88 }, /* No such regsister defined */
0293     { 0x83,          0x80 }, /* No such regsister defined */
0294     { 0x84,          0x80 }, /* No such regsister defined */
0295     { RESERVED_0X85, 0x74 },
0296     { RESERVED_0X86, 0xff },
0297     { RESERVED_0X88, 0x02 },
0298     { RESERVED_0X89, 0x16 },
0299     { RFST0,         0x1f },
0300     { RESERVED_0X94, 0x66 },
0301     { RESERVED_0X95, 0x66 },
0302     { RESERVED_0X96, 0x77 },
0303     { RESERVED_0X97, 0x99 },
0304     { RESERVED_0X98, 0xff },
0305     { RESERVED_0X99, 0xfc },
0306     { RESERVED_0X9A, 0xba },
0307     { RESERVED_0X9B, 0xaa },
0308 };
0309
0310 static u8 itd1000_reinit_tab[][2] = {
0311     { VCO_CHP1_I2C, 0x8a },
0312     { BW,           0x87 },
0313     { GVBB_I2C,     0x03 },
0314     { BBGVMIN,      0x03 },
0315     { CON1,         0x2e },
0316 };
0317
0318
0319 static int itd1000_init(struct dvb_frontend *fe)
0320 {
0321     struct itd1000_state *state = fe->tuner_priv;
0322     int i;
0323
0324     for (i = 0; i < ARRAY_SIZE(itd1000_init_tab); i++)
0325         itd1000_write_reg(state, itd1000_init_tab[i][0], itd1000_init_tab[i][1]);
0326
0327     for (i = 0; i < ARRAY_SIZE(itd1000_reinit_tab); i++)
0328         itd1000_write_reg(state, itd1000_reinit_tab[i][0], itd1000_reinit_tab[i][1]);
0329
0330     return 0;
0331 }
0332
0333 static int itd1000_sleep(struct dvb_frontend *fe)
0334 {
0335     return 0;
0336 }
0337
0338 static void itd1000_release(struct dvb_frontend *fe)
0339 {
0340     kfree(fe->tuner_priv);
0341     fe->tuner_priv = NULL;
0342 }
0343
0344 static const struct dvb_tuner_ops itd1000_tuner_ops = {
0345     .info = {
0346         .name              = "Integrant ITD1000",
0347         .frequency_min_hz  =  950 * MHz,
0348         .frequency_max_hz  = 2150 * MHz,
0349         .frequency_step_hz =  125 * kHz,
0350     },
0351
0352     .release       = itd1000_release,
0353
0354     .init          = itd1000_init,
0355     .sleep         = itd1000_sleep,
0356
0357     .set_params    = itd1000_set_parameters,
0358     .get_frequency = itd1000_get_frequency,
0359     .get_bandwidth = itd1000_get_bandwidth
0360 };
0361
0362
0363 struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg)
0364 {
0365     struct itd1000_state *state = NULL;
0366     u8 i = 0;
0367
0368     state = kzalloc(sizeof(struct itd1000_state), GFP_KERNEL);
0369     if (state == NULL)
0370         return NULL;
0371
0372     state->cfg = cfg;
0373     state->i2c = i2c;
0374
0375     i = itd1000_read_reg(state, 0);
0376     if (i != 0) {
0377         kfree(state);
0378         return NULL;
0379     }
0380     itd_info("successfully identified (ID: %d)\n", i);
0381
0382     memset(state->shadow, 0xff, sizeof(state->shadow));
0383     for (i = 0x65; i < 0x9c; i++)
0384         state->shadow[i] = itd1000_read_reg(state, i);
0385
0386     memcpy(&fe->ops.tuner_ops, &itd1000_tuner_ops, sizeof(struct dvb_tuner_ops));
0387
0388     fe->tuner_priv = state;
0389
0390     return fe;
0391 }
0392 EXPORT_SYMBOL(itd1000_attach);
0393
0394 MODULE_AUTHOR("Patrick Boettcher <pb@linuxtv.org>");
0395 MODULE_DESCRIPTION("Integrant ITD1000 driver");
0396 MODULE_LICENSE("GPL");