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0006 #ifndef GP8PSK_FE_H
0007 #define GP8PSK_FE_H
0008
0009 #include <linux/types.h>
0010
0011
0012
0013 #define GET_8PSK_CONFIG 0x80
0014 #define SET_8PSK_CONFIG 0x81
0015 #define I2C_WRITE 0x83
0016 #define I2C_READ 0x84
0017 #define ARM_TRANSFER 0x85
0018 #define TUNE_8PSK 0x86
0019 #define GET_SIGNAL_STRENGTH 0x87
0020 #define LOAD_BCM4500 0x88
0021 #define BOOT_8PSK 0x89
0022 #define START_INTERSIL 0x8A
0023 #define SET_LNB_VOLTAGE 0x8B
0024 #define SET_22KHZ_TONE 0x8C
0025 #define SEND_DISEQC_COMMAND 0x8D
0026 #define SET_DVB_MODE 0x8E
0027 #define SET_DN_SWITCH 0x8F
0028 #define GET_SIGNAL_LOCK 0x90
0029 #define GET_FW_VERS 0x92
0030 #define GET_SERIAL_NUMBER 0x93
0031 #define USE_EXTRA_VOLT 0x94
0032 #define GET_FPGA_VERS 0x95
0033 #define CW3K_INIT 0x9d
0034
0035
0036 #define bm8pskStarted 0x01
0037 #define bm8pskFW_Loaded 0x02
0038 #define bmIntersilOn 0x04
0039 #define bmDVBmode 0x08
0040 #define bm22kHz 0x10
0041 #define bmSEL18V 0x20
0042 #define bmDCtuned 0x40
0043 #define bmArmed 0x80
0044
0045
0046 #define ADV_MOD_DVB_QPSK 0
0047 #define ADV_MOD_TURBO_QPSK 1
0048 #define ADV_MOD_TURBO_8PSK 2
0049 #define ADV_MOD_TURBO_16QAM 3
0050
0051 #define ADV_MOD_DCII_C_QPSK 4
0052 #define ADV_MOD_DCII_I_QPSK 5
0053 #define ADV_MOD_DCII_Q_QPSK 6
0054 #define ADV_MOD_DCII_C_OQPSK 7
0055 #define ADV_MOD_DSS_QPSK 8
0056 #define ADV_MOD_DVB_BPSK 9
0057
0058
0059 #define GP8PSK_FW_REV1 0x020604
0060 #define GP8PSK_FW_REV2 0x020704
0061 #define GP8PSK_FW_VERS(_fw_vers) \
0062 ((_fw_vers)[2]<<0x10 | (_fw_vers)[1]<<0x08 | (_fw_vers)[0])
0063
0064 struct gp8psk_fe_ops {
0065 int (*in)(void *priv, u8 req, u16 value, u16 index, u8 *b, int blen);
0066 int (*out)(void *priv, u8 req, u16 value, u16 index, u8 *b, int blen);
0067 int (*reload)(void *priv);
0068 };
0069
0070 struct dvb_frontend *gp8psk_fe_attach(const struct gp8psk_fe_ops *ops,
0071 void *priv, bool is_rev1);
0072
0073 #endif