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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003     Montage Technology DS3000 - DVBS/S2 Demodulator driver
0004     Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
0005 
0006     Copyright (C) 2009-2012 TurboSight.com
0007 
0008  */
0009 
0010 #include <linux/slab.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/moduleparam.h>
0014 #include <linux/init.h>
0015 #include <linux/firmware.h>
0016 
0017 #include <media/dvb_frontend.h>
0018 #include "ts2020.h"
0019 #include "ds3000.h"
0020 
0021 static int debug;
0022 
0023 #define dprintk(args...) \
0024     do { \
0025         if (debug) \
0026             printk(args); \
0027     } while (0)
0028 
0029 /* as of March 2009 current DS3000 firmware version is 1.78 */
0030 /* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */
0031 #define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw"
0032 
0033 #define DS3000_SAMPLE_RATE 96000 /* in kHz */
0034 
0035 /* Register values to initialise the demod in DVB-S mode */
0036 static u8 ds3000_dvbs_init_tab[] = {
0037     0x23, 0x05,
0038     0x08, 0x03,
0039     0x0c, 0x00,
0040     0x21, 0x54,
0041     0x25, 0x82,
0042     0x27, 0x31,
0043     0x30, 0x08,
0044     0x31, 0x40,
0045     0x32, 0x32,
0046     0x33, 0x35,
0047     0x35, 0xff,
0048     0x3a, 0x00,
0049     0x37, 0x10,
0050     0x38, 0x10,
0051     0x39, 0x02,
0052     0x42, 0x60,
0053     0x4a, 0x40,
0054     0x4b, 0x04,
0055     0x4d, 0x91,
0056     0x5d, 0xc8,
0057     0x50, 0x77,
0058     0x51, 0x77,
0059     0x52, 0x36,
0060     0x53, 0x36,
0061     0x56, 0x01,
0062     0x63, 0x43,
0063     0x64, 0x30,
0064     0x65, 0x40,
0065     0x68, 0x26,
0066     0x69, 0x4c,
0067     0x70, 0x20,
0068     0x71, 0x70,
0069     0x72, 0x04,
0070     0x73, 0x00,
0071     0x70, 0x40,
0072     0x71, 0x70,
0073     0x72, 0x04,
0074     0x73, 0x00,
0075     0x70, 0x60,
0076     0x71, 0x70,
0077     0x72, 0x04,
0078     0x73, 0x00,
0079     0x70, 0x80,
0080     0x71, 0x70,
0081     0x72, 0x04,
0082     0x73, 0x00,
0083     0x70, 0xa0,
0084     0x71, 0x70,
0085     0x72, 0x04,
0086     0x73, 0x00,
0087     0x70, 0x1f,
0088     0x76, 0x00,
0089     0x77, 0xd1,
0090     0x78, 0x0c,
0091     0x79, 0x80,
0092     0x7f, 0x04,
0093     0x7c, 0x00,
0094     0x80, 0x86,
0095     0x81, 0xa6,
0096     0x85, 0x04,
0097     0xcd, 0xf4,
0098     0x90, 0x33,
0099     0xa0, 0x44,
0100     0xc0, 0x18,
0101     0xc3, 0x10,
0102     0xc4, 0x08,
0103     0xc5, 0x80,
0104     0xc6, 0x80,
0105     0xc7, 0x0a,
0106     0xc8, 0x1a,
0107     0xc9, 0x80,
0108     0xfe, 0x92,
0109     0xe0, 0xf8,
0110     0xe6, 0x8b,
0111     0xd0, 0x40,
0112     0xf8, 0x20,
0113     0xfa, 0x0f,
0114     0xfd, 0x20,
0115     0xad, 0x20,
0116     0xae, 0x07,
0117     0xb8, 0x00,
0118 };
0119 
0120 /* Register values to initialise the demod in DVB-S2 mode */
0121 static u8 ds3000_dvbs2_init_tab[] = {
0122     0x23, 0x0f,
0123     0x08, 0x07,
0124     0x0c, 0x00,
0125     0x21, 0x54,
0126     0x25, 0x82,
0127     0x27, 0x31,
0128     0x30, 0x08,
0129     0x31, 0x32,
0130     0x32, 0x32,
0131     0x33, 0x35,
0132     0x35, 0xff,
0133     0x3a, 0x00,
0134     0x37, 0x10,
0135     0x38, 0x10,
0136     0x39, 0x02,
0137     0x42, 0x60,
0138     0x4a, 0x80,
0139     0x4b, 0x04,
0140     0x4d, 0x81,
0141     0x5d, 0x88,
0142     0x50, 0x36,
0143     0x51, 0x36,
0144     0x52, 0x36,
0145     0x53, 0x36,
0146     0x63, 0x60,
0147     0x64, 0x10,
0148     0x65, 0x10,
0149     0x68, 0x04,
0150     0x69, 0x29,
0151     0x70, 0x20,
0152     0x71, 0x70,
0153     0x72, 0x04,
0154     0x73, 0x00,
0155     0x70, 0x40,
0156     0x71, 0x70,
0157     0x72, 0x04,
0158     0x73, 0x00,
0159     0x70, 0x60,
0160     0x71, 0x70,
0161     0x72, 0x04,
0162     0x73, 0x00,
0163     0x70, 0x80,
0164     0x71, 0x70,
0165     0x72, 0x04,
0166     0x73, 0x00,
0167     0x70, 0xa0,
0168     0x71, 0x70,
0169     0x72, 0x04,
0170     0x73, 0x00,
0171     0x70, 0x1f,
0172     0xa0, 0x44,
0173     0xc0, 0x08,
0174     0xc1, 0x10,
0175     0xc2, 0x08,
0176     0xc3, 0x10,
0177     0xc4, 0x08,
0178     0xc5, 0xf0,
0179     0xc6, 0xf0,
0180     0xc7, 0x0a,
0181     0xc8, 0x1a,
0182     0xc9, 0x80,
0183     0xca, 0x23,
0184     0xcb, 0x24,
0185     0xce, 0x74,
0186     0x90, 0x03,
0187     0x76, 0x80,
0188     0x77, 0x42,
0189     0x78, 0x0a,
0190     0x79, 0x80,
0191     0xad, 0x40,
0192     0xae, 0x07,
0193     0x7f, 0xd4,
0194     0x7c, 0x00,
0195     0x80, 0xa8,
0196     0x81, 0xda,
0197     0x7c, 0x01,
0198     0x80, 0xda,
0199     0x81, 0xec,
0200     0x7c, 0x02,
0201     0x80, 0xca,
0202     0x81, 0xeb,
0203     0x7c, 0x03,
0204     0x80, 0xba,
0205     0x81, 0xdb,
0206     0x85, 0x08,
0207     0x86, 0x00,
0208     0x87, 0x02,
0209     0x89, 0x80,
0210     0x8b, 0x44,
0211     0x8c, 0xaa,
0212     0x8a, 0x10,
0213     0xba, 0x00,
0214     0xf5, 0x04,
0215     0xfe, 0x44,
0216     0xd2, 0x32,
0217     0xb8, 0x00,
0218 };
0219 
0220 struct ds3000_state {
0221     struct i2c_adapter *i2c;
0222     const struct ds3000_config *config;
0223     struct dvb_frontend frontend;
0224     /* previous uncorrected block counter for DVB-S2 */
0225     u16 prevUCBS2;
0226 };
0227 
0228 static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
0229 {
0230     u8 buf[] = { reg, data };
0231     struct i2c_msg msg = { .addr = state->config->demod_address,
0232         .flags = 0, .buf = buf, .len = 2 };
0233     int err;
0234 
0235     dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
0236 
0237     err = i2c_transfer(state->i2c, &msg, 1);
0238     if (err != 1) {
0239         printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n",
0240                __func__, err, reg, data);
0241         return -EREMOTEIO;
0242     }
0243 
0244     return 0;
0245 }
0246 
0247 static int ds3000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
0248 {
0249     struct ds3000_state *state = fe->demodulator_priv;
0250 
0251     if (enable)
0252         ds3000_writereg(state, 0x03, 0x12);
0253     else
0254         ds3000_writereg(state, 0x03, 0x02);
0255 
0256     return 0;
0257 }
0258 
0259 /* I2C write for 8k firmware load */
0260 static int ds3000_writeFW(struct ds3000_state *state, int reg,
0261                 const u8 *data, u16 len)
0262 {
0263     int i, ret = 0;
0264     struct i2c_msg msg;
0265     u8 *buf;
0266 
0267     buf = kmalloc(33, GFP_KERNEL);
0268     if (!buf)
0269         return -ENOMEM;
0270 
0271     *(buf) = reg;
0272 
0273     msg.addr = state->config->demod_address;
0274     msg.flags = 0;
0275     msg.buf = buf;
0276     msg.len = 33;
0277 
0278     for (i = 0; i < len; i += 32) {
0279         memcpy(buf + 1, data + i, 32);
0280 
0281         dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
0282 
0283         ret = i2c_transfer(state->i2c, &msg, 1);
0284         if (ret != 1) {
0285             printk(KERN_ERR "%s: write error(err == %i, reg == 0x%02x\n",
0286                    __func__, ret, reg);
0287             ret = -EREMOTEIO;
0288             goto error;
0289         }
0290     }
0291     ret = 0;
0292 
0293 error:
0294     kfree(buf);
0295 
0296     return ret;
0297 }
0298 
0299 static int ds3000_readreg(struct ds3000_state *state, u8 reg)
0300 {
0301     int ret;
0302     u8 b0[] = { reg };
0303     u8 b1[] = { 0 };
0304     struct i2c_msg msg[] = {
0305         {
0306             .addr = state->config->demod_address,
0307             .flags = 0,
0308             .buf = b0,
0309             .len = 1
0310         }, {
0311             .addr = state->config->demod_address,
0312             .flags = I2C_M_RD,
0313             .buf = b1,
0314             .len = 1
0315         }
0316     };
0317 
0318     ret = i2c_transfer(state->i2c, msg, 2);
0319 
0320     if (ret != 2) {
0321         printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
0322         return ret;
0323     }
0324 
0325     dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
0326 
0327     return b1[0];
0328 }
0329 
0330 static int ds3000_load_firmware(struct dvb_frontend *fe,
0331                     const struct firmware *fw);
0332 
0333 static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
0334 {
0335     struct ds3000_state *state = fe->demodulator_priv;
0336     const struct firmware *fw;
0337     int ret = 0;
0338 
0339     dprintk("%s()\n", __func__);
0340 
0341     ret = ds3000_readreg(state, 0xb2);
0342     if (ret < 0)
0343         return ret;
0344 
0345     /* Load firmware */
0346     /* request the firmware, this will block until someone uploads it */
0347     printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
0348                 DS3000_DEFAULT_FIRMWARE);
0349     ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE,
0350                 state->i2c->dev.parent);
0351     printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
0352     if (ret) {
0353         printk(KERN_ERR "%s: No firmware uploaded (timeout or file not found?)\n",
0354                __func__);
0355         return ret;
0356     }
0357 
0358     ret = ds3000_load_firmware(fe, fw);
0359     if (ret)
0360         printk("%s: Writing firmware to device failed\n", __func__);
0361 
0362     release_firmware(fw);
0363 
0364     dprintk("%s: Firmware upload %s\n", __func__,
0365             ret == 0 ? "complete" : "failed");
0366 
0367     return ret;
0368 }
0369 
0370 static int ds3000_load_firmware(struct dvb_frontend *fe,
0371                     const struct firmware *fw)
0372 {
0373     struct ds3000_state *state = fe->demodulator_priv;
0374     int ret = 0;
0375 
0376     dprintk("%s\n", __func__);
0377     dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
0378             fw->size,
0379             fw->data[0],
0380             fw->data[1],
0381             fw->data[fw->size - 2],
0382             fw->data[fw->size - 1]);
0383 
0384     /* Begin the firmware load process */
0385     ds3000_writereg(state, 0xb2, 0x01);
0386     /* write the entire firmware */
0387     ret = ds3000_writeFW(state, 0xb0, fw->data, fw->size);
0388     ds3000_writereg(state, 0xb2, 0x00);
0389 
0390     return ret;
0391 }
0392 
0393 static int ds3000_set_voltage(struct dvb_frontend *fe,
0394                   enum fe_sec_voltage voltage)
0395 {
0396     struct ds3000_state *state = fe->demodulator_priv;
0397     u8 data;
0398 
0399     dprintk("%s(%d)\n", __func__, voltage);
0400 
0401     data = ds3000_readreg(state, 0xa2);
0402     data |= 0x03; /* bit0 V/H, bit1 off/on */
0403 
0404     switch (voltage) {
0405     case SEC_VOLTAGE_18:
0406         data &= ~0x03;
0407         break;
0408     case SEC_VOLTAGE_13:
0409         data &= ~0x03;
0410         data |= 0x01;
0411         break;
0412     case SEC_VOLTAGE_OFF:
0413         break;
0414     }
0415 
0416     ds3000_writereg(state, 0xa2, data);
0417 
0418     return 0;
0419 }
0420 
0421 static int ds3000_read_status(struct dvb_frontend *fe, enum fe_status *status)
0422 {
0423     struct ds3000_state *state = fe->demodulator_priv;
0424     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0425     int lock;
0426 
0427     *status = 0;
0428 
0429     switch (c->delivery_system) {
0430     case SYS_DVBS:
0431         lock = ds3000_readreg(state, 0xd1);
0432         if ((lock & 0x07) == 0x07)
0433             *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
0434                 FE_HAS_VITERBI | FE_HAS_SYNC |
0435                 FE_HAS_LOCK;
0436 
0437         break;
0438     case SYS_DVBS2:
0439         lock = ds3000_readreg(state, 0x0d);
0440         if ((lock & 0x8f) == 0x8f)
0441             *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
0442                 FE_HAS_VITERBI | FE_HAS_SYNC |
0443                 FE_HAS_LOCK;
0444 
0445         break;
0446     default:
0447         return -EINVAL;
0448     }
0449 
0450     if (state->config->set_lock_led)
0451         state->config->set_lock_led(fe, *status == 0 ? 0 : 1);
0452 
0453     dprintk("%s: status = 0x%02x\n", __func__, lock);
0454 
0455     return 0;
0456 }
0457 
0458 /* read DS3000 BER value */
0459 static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
0460 {
0461     struct ds3000_state *state = fe->demodulator_priv;
0462     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0463     u8 data;
0464     u32 ber_reading, lpdc_frames;
0465 
0466     dprintk("%s()\n", __func__);
0467 
0468     switch (c->delivery_system) {
0469     case SYS_DVBS:
0470         /* set the number of bytes checked during
0471         BER estimation */
0472         ds3000_writereg(state, 0xf9, 0x04);
0473         /* read BER estimation status */
0474         data = ds3000_readreg(state, 0xf8);
0475         /* check if BER estimation is ready */
0476         if ((data & 0x10) == 0) {
0477             /* this is the number of error bits,
0478             to calculate the bit error rate
0479             divide to 8388608 */
0480             *ber = (ds3000_readreg(state, 0xf7) << 8) |
0481                 ds3000_readreg(state, 0xf6);
0482             /* start counting error bits */
0483             /* need to be set twice
0484             otherwise it fails sometimes */
0485             data |= 0x10;
0486             ds3000_writereg(state, 0xf8, data);
0487             ds3000_writereg(state, 0xf8, data);
0488         } else
0489             /* used to indicate that BER estimation
0490             is not ready, i.e. BER is unknown */
0491             *ber = 0xffffffff;
0492         break;
0493     case SYS_DVBS2:
0494         /* read the number of LPDC decoded frames */
0495         lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
0496                 (ds3000_readreg(state, 0xd6) << 8) |
0497                 ds3000_readreg(state, 0xd5);
0498         /* read the number of packets with bad CRC */
0499         ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
0500                 ds3000_readreg(state, 0xf7);
0501         if (lpdc_frames > 750) {
0502             /* clear LPDC frame counters */
0503             ds3000_writereg(state, 0xd1, 0x01);
0504             /* clear bad packets counter */
0505             ds3000_writereg(state, 0xf9, 0x01);
0506             /* enable bad packets counter */
0507             ds3000_writereg(state, 0xf9, 0x00);
0508             /* enable LPDC frame counters */
0509             ds3000_writereg(state, 0xd1, 0x00);
0510             *ber = ber_reading;
0511         } else
0512             /* used to indicate that BER estimation is not ready,
0513             i.e. BER is unknown */
0514             *ber = 0xffffffff;
0515         break;
0516     default:
0517         return -EINVAL;
0518     }
0519 
0520     return 0;
0521 }
0522 
0523 static int ds3000_read_signal_strength(struct dvb_frontend *fe,
0524                         u16 *signal_strength)
0525 {
0526     if (fe->ops.tuner_ops.get_rf_strength)
0527         fe->ops.tuner_ops.get_rf_strength(fe, signal_strength);
0528 
0529     return 0;
0530 }
0531 
0532 /* calculate DS3000 snr value in dB */
0533 static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
0534 {
0535     struct ds3000_state *state = fe->demodulator_priv;
0536     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0537     u8 snr_reading, snr_value;
0538     u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
0539     static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
0540         0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
0541         0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
0542         0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
0543     };
0544     static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
0545         0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
0546         0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
0547         0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
0548         0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
0549         0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
0550         0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
0551         0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
0552         0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
0553         0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
0554         0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
0555         0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
0556         0x49e9, 0x4a20, 0x4a57
0557     };
0558 
0559     dprintk("%s()\n", __func__);
0560 
0561     switch (c->delivery_system) {
0562     case SYS_DVBS:
0563         snr_reading = ds3000_readreg(state, 0xff);
0564         snr_reading /= 8;
0565         if (snr_reading == 0)
0566             *snr = 0x0000;
0567         else {
0568             if (snr_reading > 20)
0569                 snr_reading = 20;
0570             snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
0571             /* cook the value to be suitable for szap-s2
0572             human readable output */
0573             *snr = snr_value * 8 * 655;
0574         }
0575         dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
0576                 snr_reading, *snr);
0577         break;
0578     case SYS_DVBS2:
0579         dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
0580                 (ds3000_readreg(state, 0x8d) << 4);
0581         dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
0582         tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
0583         if (tmp == 0) {
0584             *snr = 0x0000;
0585             return 0;
0586         }
0587         if (dvbs2_noise_reading == 0) {
0588             snr_value = 0x0013;
0589             /* cook the value to be suitable for szap-s2
0590             human readable output */
0591             *snr = 0xffff;
0592             return 0;
0593         }
0594         if (tmp > dvbs2_noise_reading) {
0595             snr_reading = tmp / dvbs2_noise_reading;
0596             if (snr_reading > 80)
0597                 snr_reading = 80;
0598             snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
0599             /* cook the value to be suitable for szap-s2
0600             human readable output */
0601             *snr = snr_value * 5 * 655;
0602         } else {
0603             snr_reading = dvbs2_noise_reading / tmp;
0604             if (snr_reading > 80)
0605                 snr_reading = 80;
0606             *snr = -(dvbs2_snr_tab[snr_reading - 1] / 1000);
0607         }
0608         dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
0609                 snr_reading, *snr);
0610         break;
0611     default:
0612         return -EINVAL;
0613     }
0614 
0615     return 0;
0616 }
0617 
0618 /* read DS3000 uncorrected blocks */
0619 static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
0620 {
0621     struct ds3000_state *state = fe->demodulator_priv;
0622     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0623     u8 data;
0624     u16 _ucblocks;
0625 
0626     dprintk("%s()\n", __func__);
0627 
0628     switch (c->delivery_system) {
0629     case SYS_DVBS:
0630         *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
0631                 ds3000_readreg(state, 0xf4);
0632         data = ds3000_readreg(state, 0xf8);
0633         /* clear packet counters */
0634         data &= ~0x20;
0635         ds3000_writereg(state, 0xf8, data);
0636         /* enable packet counters */
0637         data |= 0x20;
0638         ds3000_writereg(state, 0xf8, data);
0639         break;
0640     case SYS_DVBS2:
0641         _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
0642                 ds3000_readreg(state, 0xe1);
0643         if (_ucblocks > state->prevUCBS2)
0644             *ucblocks = _ucblocks - state->prevUCBS2;
0645         else
0646             *ucblocks = state->prevUCBS2 - _ucblocks;
0647         state->prevUCBS2 = _ucblocks;
0648         break;
0649     default:
0650         return -EINVAL;
0651     }
0652 
0653     return 0;
0654 }
0655 
0656 static int ds3000_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
0657 {
0658     struct ds3000_state *state = fe->demodulator_priv;
0659     u8 data;
0660 
0661     dprintk("%s(%d)\n", __func__, tone);
0662     if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
0663         printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
0664         return -EINVAL;
0665     }
0666 
0667     data = ds3000_readreg(state, 0xa2);
0668     data &= ~0xc0;
0669     ds3000_writereg(state, 0xa2, data);
0670 
0671     switch (tone) {
0672     case SEC_TONE_ON:
0673         dprintk("%s: setting tone on\n", __func__);
0674         data = ds3000_readreg(state, 0xa1);
0675         data &= ~0x43;
0676         data |= 0x04;
0677         ds3000_writereg(state, 0xa1, data);
0678         break;
0679     case SEC_TONE_OFF:
0680         dprintk("%s: setting tone off\n", __func__);
0681         data = ds3000_readreg(state, 0xa2);
0682         data |= 0x80;
0683         ds3000_writereg(state, 0xa2, data);
0684         break;
0685     }
0686 
0687     return 0;
0688 }
0689 
0690 static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
0691                 struct dvb_diseqc_master_cmd *d)
0692 {
0693     struct ds3000_state *state = fe->demodulator_priv;
0694     int i;
0695     u8 data;
0696 
0697     /* Dump DiSEqC message */
0698     dprintk("%s(", __func__);
0699     for (i = 0 ; i < d->msg_len;) {
0700         dprintk("0x%02x", d->msg[i]);
0701         if (++i < d->msg_len)
0702             dprintk(", ");
0703     }
0704 
0705     /* enable DiSEqC message send pin */
0706     data = ds3000_readreg(state, 0xa2);
0707     data &= ~0xc0;
0708     ds3000_writereg(state, 0xa2, data);
0709 
0710     /* DiSEqC message */
0711     for (i = 0; i < d->msg_len; i++)
0712         ds3000_writereg(state, 0xa3 + i, d->msg[i]);
0713 
0714     data = ds3000_readreg(state, 0xa1);
0715     /* clear DiSEqC message length and status,
0716     enable DiSEqC message send */
0717     data &= ~0xf8;
0718     /* set DiSEqC mode, modulation active during 33 pulses,
0719     set DiSEqC message length */
0720     data |= ((d->msg_len - 1) << 3) | 0x07;
0721     ds3000_writereg(state, 0xa1, data);
0722 
0723     /* wait up to 150ms for DiSEqC transmission to complete */
0724     for (i = 0; i < 15; i++) {
0725         data = ds3000_readreg(state, 0xa1);
0726         if ((data & 0x40) == 0)
0727             break;
0728         msleep(10);
0729     }
0730 
0731     /* DiSEqC timeout after 150ms */
0732     if (i == 15) {
0733         data = ds3000_readreg(state, 0xa1);
0734         data &= ~0x80;
0735         data |= 0x40;
0736         ds3000_writereg(state, 0xa1, data);
0737 
0738         data = ds3000_readreg(state, 0xa2);
0739         data &= ~0xc0;
0740         data |= 0x80;
0741         ds3000_writereg(state, 0xa2, data);
0742 
0743         return -ETIMEDOUT;
0744     }
0745 
0746     data = ds3000_readreg(state, 0xa2);
0747     data &= ~0xc0;
0748     data |= 0x80;
0749     ds3000_writereg(state, 0xa2, data);
0750 
0751     return 0;
0752 }
0753 
0754 /* Send DiSEqC burst */
0755 static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
0756                     enum fe_sec_mini_cmd burst)
0757 {
0758     struct ds3000_state *state = fe->demodulator_priv;
0759     int i;
0760     u8 data;
0761 
0762     dprintk("%s()\n", __func__);
0763 
0764     data = ds3000_readreg(state, 0xa2);
0765     data &= ~0xc0;
0766     ds3000_writereg(state, 0xa2, data);
0767 
0768     /* DiSEqC burst */
0769     if (burst == SEC_MINI_A)
0770         /* Unmodulated tone burst */
0771         ds3000_writereg(state, 0xa1, 0x02);
0772     else if (burst == SEC_MINI_B)
0773         /* Modulated tone burst */
0774         ds3000_writereg(state, 0xa1, 0x01);
0775     else
0776         return -EINVAL;
0777 
0778     msleep(13);
0779     for (i = 0; i < 5; i++) {
0780         data = ds3000_readreg(state, 0xa1);
0781         if ((data & 0x40) == 0)
0782             break;
0783         msleep(1);
0784     }
0785 
0786     if (i == 5) {
0787         data = ds3000_readreg(state, 0xa1);
0788         data &= ~0x80;
0789         data |= 0x40;
0790         ds3000_writereg(state, 0xa1, data);
0791 
0792         data = ds3000_readreg(state, 0xa2);
0793         data &= ~0xc0;
0794         data |= 0x80;
0795         ds3000_writereg(state, 0xa2, data);
0796 
0797         return -ETIMEDOUT;
0798     }
0799 
0800     data = ds3000_readreg(state, 0xa2);
0801     data &= ~0xc0;
0802     data |= 0x80;
0803     ds3000_writereg(state, 0xa2, data);
0804 
0805     return 0;
0806 }
0807 
0808 static void ds3000_release(struct dvb_frontend *fe)
0809 {
0810     struct ds3000_state *state = fe->demodulator_priv;
0811 
0812     if (state->config->set_lock_led)
0813         state->config->set_lock_led(fe, 0);
0814 
0815     dprintk("%s\n", __func__);
0816     kfree(state);
0817 }
0818 
0819 static const struct dvb_frontend_ops ds3000_ops;
0820 
0821 struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
0822                     struct i2c_adapter *i2c)
0823 {
0824     struct ds3000_state *state;
0825     int ret;
0826 
0827     dprintk("%s\n", __func__);
0828 
0829     /* allocate memory for the internal state */
0830     state = kzalloc(sizeof(*state), GFP_KERNEL);
0831     if (!state)
0832         return NULL;
0833 
0834     state->config = config;
0835     state->i2c = i2c;
0836     state->prevUCBS2 = 0;
0837 
0838     /* check if the demod is present */
0839     ret = ds3000_readreg(state, 0x00) & 0xfe;
0840     if (ret != 0xe0) {
0841         kfree(state);
0842         printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
0843         return NULL;
0844     }
0845 
0846     printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
0847             ds3000_readreg(state, 0x02),
0848             ds3000_readreg(state, 0x01));
0849 
0850     memcpy(&state->frontend.ops, &ds3000_ops,
0851             sizeof(struct dvb_frontend_ops));
0852     state->frontend.demodulator_priv = state;
0853 
0854     /*
0855      * Some devices like T480 starts with voltage on. Be sure
0856      * to turn voltage off during init, as this can otherwise
0857      * interfere with Unicable SCR systems.
0858      */
0859     ds3000_set_voltage(&state->frontend, SEC_VOLTAGE_OFF);
0860     return &state->frontend;
0861 }
0862 EXPORT_SYMBOL(ds3000_attach);
0863 
0864 static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
0865                     s32 carrier_offset_khz)
0866 {
0867     struct ds3000_state *state = fe->demodulator_priv;
0868     s32 tmp;
0869 
0870     tmp = carrier_offset_khz;
0871     tmp *= 65536;
0872     tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
0873 
0874     if (tmp < 0)
0875         tmp += 65536;
0876 
0877     ds3000_writereg(state, 0x5f, tmp >> 8);
0878     ds3000_writereg(state, 0x5e, tmp & 0xff);
0879 
0880     return 0;
0881 }
0882 
0883 static int ds3000_set_frontend(struct dvb_frontend *fe)
0884 {
0885     struct ds3000_state *state = fe->demodulator_priv;
0886     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0887 
0888     int i;
0889     enum fe_status status;
0890     s32 offset_khz;
0891     u32 frequency;
0892     u16 value;
0893 
0894     dprintk("%s() ", __func__);
0895 
0896     if (state->config->set_ts_params)
0897         state->config->set_ts_params(fe, 0);
0898     /* Tune */
0899     if (fe->ops.tuner_ops.set_params)
0900         fe->ops.tuner_ops.set_params(fe);
0901 
0902     /* ds3000 global reset */
0903     ds3000_writereg(state, 0x07, 0x80);
0904     ds3000_writereg(state, 0x07, 0x00);
0905     /* ds3000 built-in uC reset */
0906     ds3000_writereg(state, 0xb2, 0x01);
0907     /* ds3000 software reset */
0908     ds3000_writereg(state, 0x00, 0x01);
0909 
0910     switch (c->delivery_system) {
0911     case SYS_DVBS:
0912         /* initialise the demod in DVB-S mode */
0913         for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
0914             ds3000_writereg(state,
0915                 ds3000_dvbs_init_tab[i],
0916                 ds3000_dvbs_init_tab[i + 1]);
0917         value = ds3000_readreg(state, 0xfe);
0918         value &= 0xc0;
0919         value |= 0x1b;
0920         ds3000_writereg(state, 0xfe, value);
0921         break;
0922     case SYS_DVBS2:
0923         /* initialise the demod in DVB-S2 mode */
0924         for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
0925             ds3000_writereg(state,
0926                 ds3000_dvbs2_init_tab[i],
0927                 ds3000_dvbs2_init_tab[i + 1]);
0928         if (c->symbol_rate >= 30000000)
0929             ds3000_writereg(state, 0xfe, 0x54);
0930         else
0931             ds3000_writereg(state, 0xfe, 0x98);
0932         break;
0933     default:
0934         return -EINVAL;
0935     }
0936 
0937     /* enable 27MHz clock output */
0938     ds3000_writereg(state, 0x29, 0x80);
0939     /* enable ac coupling */
0940     ds3000_writereg(state, 0x25, 0x8a);
0941 
0942     if ((c->symbol_rate < ds3000_ops.info.symbol_rate_min) ||
0943             (c->symbol_rate > ds3000_ops.info.symbol_rate_max)) {
0944         dprintk("%s() symbol_rate %u out of range (%u ... %u)\n",
0945                 __func__, c->symbol_rate,
0946                 ds3000_ops.info.symbol_rate_min,
0947                 ds3000_ops.info.symbol_rate_max);
0948         return -EINVAL;
0949     }
0950 
0951     /* enhance symbol rate performance */
0952     if ((c->symbol_rate / 1000) <= 5000) {
0953         value = 29777 / (c->symbol_rate / 1000) + 1;
0954         if (value % 2 != 0)
0955             value++;
0956         ds3000_writereg(state, 0xc3, 0x0d);
0957         ds3000_writereg(state, 0xc8, value);
0958         ds3000_writereg(state, 0xc4, 0x10);
0959         ds3000_writereg(state, 0xc7, 0x0e);
0960     } else if ((c->symbol_rate / 1000) <= 10000) {
0961         value = 92166 / (c->symbol_rate / 1000) + 1;
0962         if (value % 2 != 0)
0963             value++;
0964         ds3000_writereg(state, 0xc3, 0x07);
0965         ds3000_writereg(state, 0xc8, value);
0966         ds3000_writereg(state, 0xc4, 0x09);
0967         ds3000_writereg(state, 0xc7, 0x12);
0968     } else if ((c->symbol_rate / 1000) <= 20000) {
0969         value = 64516 / (c->symbol_rate / 1000) + 1;
0970         ds3000_writereg(state, 0xc3, value);
0971         ds3000_writereg(state, 0xc8, 0x0e);
0972         ds3000_writereg(state, 0xc4, 0x07);
0973         ds3000_writereg(state, 0xc7, 0x18);
0974     } else {
0975         value = 129032 / (c->symbol_rate / 1000) + 1;
0976         ds3000_writereg(state, 0xc3, value);
0977         ds3000_writereg(state, 0xc8, 0x0a);
0978         ds3000_writereg(state, 0xc4, 0x05);
0979         ds3000_writereg(state, 0xc7, 0x24);
0980     }
0981 
0982     /* normalized symbol rate rounded to the closest integer */
0983     value = (((c->symbol_rate / 1000) << 16) +
0984             (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
0985     ds3000_writereg(state, 0x61, value & 0x00ff);
0986     ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
0987 
0988     /* co-channel interference cancellation disabled */
0989     ds3000_writereg(state, 0x56, 0x00);
0990 
0991     /* equalizer disabled */
0992     ds3000_writereg(state, 0x76, 0x00);
0993 
0994     /*ds3000_writereg(state, 0x08, 0x03);
0995     ds3000_writereg(state, 0xfd, 0x22);
0996     ds3000_writereg(state, 0x08, 0x07);
0997     ds3000_writereg(state, 0xfd, 0x42);
0998     ds3000_writereg(state, 0x08, 0x07);*/
0999 
1000     if (state->config->ci_mode) {
1001         switch (c->delivery_system) {
1002         case SYS_DVBS:
1003         default:
1004             ds3000_writereg(state, 0xfd, 0x80);
1005         break;
1006         case SYS_DVBS2:
1007             ds3000_writereg(state, 0xfd, 0x01);
1008             break;
1009         }
1010     }
1011 
1012     /* ds3000 out of software reset */
1013     ds3000_writereg(state, 0x00, 0x00);
1014     /* start ds3000 built-in uC */
1015     ds3000_writereg(state, 0xb2, 0x00);
1016 
1017     if (fe->ops.tuner_ops.get_frequency) {
1018         fe->ops.tuner_ops.get_frequency(fe, &frequency);
1019         offset_khz = frequency - c->frequency;
1020         ds3000_set_carrier_offset(fe, offset_khz);
1021     }
1022 
1023     for (i = 0; i < 30 ; i++) {
1024         ds3000_read_status(fe, &status);
1025         if (status & FE_HAS_LOCK)
1026             break;
1027 
1028         msleep(10);
1029     }
1030 
1031     return 0;
1032 }
1033 
1034 static int ds3000_tune(struct dvb_frontend *fe,
1035             bool re_tune,
1036             unsigned int mode_flags,
1037             unsigned int *delay,
1038             enum fe_status *status)
1039 {
1040     if (re_tune) {
1041         int ret = ds3000_set_frontend(fe);
1042         if (ret)
1043             return ret;
1044     }
1045 
1046     *delay = HZ / 5;
1047 
1048     return ds3000_read_status(fe, status);
1049 }
1050 
1051 static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
1052 {
1053     struct ds3000_state *state = fe->demodulator_priv;
1054 
1055     if (state->config->set_lock_led)
1056         state->config->set_lock_led(fe, 0);
1057 
1058     dprintk("%s()\n", __func__);
1059     return DVBFE_ALGO_HW;
1060 }
1061 
1062 /*
1063  * Initialise or wake up device
1064  *
1065  * Power config will reset and load initial firmware if required
1066  */
1067 static int ds3000_initfe(struct dvb_frontend *fe)
1068 {
1069     struct ds3000_state *state = fe->demodulator_priv;
1070     int ret;
1071 
1072     dprintk("%s()\n", __func__);
1073     /* hard reset */
1074     ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
1075     msleep(1);
1076 
1077     /* Load the firmware if required */
1078     ret = ds3000_firmware_ondemand(fe);
1079     if (ret != 0) {
1080         printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
1081         return ret;
1082     }
1083 
1084     return 0;
1085 }
1086 
1087 static const struct dvb_frontend_ops ds3000_ops = {
1088     .delsys = { SYS_DVBS, SYS_DVBS2 },
1089     .info = {
1090         .name = "Montage Technology DS3000",
1091         .frequency_min_hz =  950 * MHz,
1092         .frequency_max_hz = 2150 * MHz,
1093         .frequency_stepsize_hz = 1011 * kHz,
1094         .frequency_tolerance_hz = 5 * MHz,
1095         .symbol_rate_min = 1000000,
1096         .symbol_rate_max = 45000000,
1097         .caps = FE_CAN_INVERSION_AUTO |
1098             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1099             FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1100             FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1101             FE_CAN_2G_MODULATION |
1102             FE_CAN_QPSK | FE_CAN_RECOVER
1103     },
1104 
1105     .release = ds3000_release,
1106 
1107     .init = ds3000_initfe,
1108     .i2c_gate_ctrl = ds3000_i2c_gate_ctrl,
1109     .read_status = ds3000_read_status,
1110     .read_ber = ds3000_read_ber,
1111     .read_signal_strength = ds3000_read_signal_strength,
1112     .read_snr = ds3000_read_snr,
1113     .read_ucblocks = ds3000_read_ucblocks,
1114     .set_voltage = ds3000_set_voltage,
1115     .set_tone = ds3000_set_tone,
1116     .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
1117     .diseqc_send_burst = ds3000_diseqc_send_burst,
1118     .get_frontend_algo = ds3000_get_algo,
1119 
1120     .set_frontend = ds3000_set_frontend,
1121     .tune = ds3000_tune,
1122 };
1123 
1124 module_param(debug, int, 0644);
1125 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1126 
1127 MODULE_DESCRIPTION("DVB Frontend module for Montage Technology DS3000 hardware");
1128 MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
1129 MODULE_LICENSE("GPL");
1130 MODULE_FIRMWARE(DS3000_DEFAULT_FIRMWARE);
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