media/dvb-frontends/drxk_hard.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #include "drxk_map.h"
0003
0004 #define DRXK_VERSION_MAJOR 0
0005 #define DRXK_VERSION_MINOR 9
0006 #define DRXK_VERSION_PATCH 4300
0007
0008 #define HI_I2C_DELAY        42
0009 #define HI_I2C_BRIDGE_DELAY 350
0010 #define DRXK_MAX_RETRIES    100
0011
0012 #define DRIVER_4400 1
0013
0014 #define DRXX_JTAGID   0x039210D9
0015 #define DRXX_J_JTAGID 0x239310D9
0016 #define DRXX_K_JTAGID 0x039210D9
0017
0018 #define DRX_UNKNOWN     254
0019 #define DRX_AUTO        255
0020
0021 #define DRX_SCU_READY   0
0022 #define DRXK_MAX_WAITTIME (200)
0023 #define SCU_RESULT_OK      0
0024 #define SCU_RESULT_SIZE   -4
0025 #define SCU_RESULT_INVPAR -3
0026 #define SCU_RESULT_UNKSTD -2
0027 #define SCU_RESULT_UNKCMD -1
0028
0029 #ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT
0030 #define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200)
0031 #endif
0032
0033 #define DRXK_8VSB_MPEG_BIT_RATE     19392658UL  /*bps*/
0034 #define DRXK_DVBT_MPEG_BIT_RATE     32000000UL  /*bps*/
0035 #define DRXK_QAM16_MPEG_BIT_RATE    27000000UL  /*bps*/
0036 #define DRXK_QAM32_MPEG_BIT_RATE    33000000UL  /*bps*/
0037 #define DRXK_QAM64_MPEG_BIT_RATE    40000000UL  /*bps*/
0038 #define DRXK_QAM128_MPEG_BIT_RATE   46000000UL  /*bps*/
0039 #define DRXK_QAM256_MPEG_BIT_RATE   52000000UL  /*bps*/
0040 #define DRXK_MAX_MPEG_BIT_RATE      52000000UL  /*bps*/
0041
0042 #define   IQM_CF_OUT_ENA_OFDM__M                                            0x4
0043 #define     IQM_FS_ADJ_SEL_B_QAM                                            0x1
0044 #define     IQM_FS_ADJ_SEL_B_OFF                                            0x0
0045 #define     IQM_FS_ADJ_SEL_B_VSB                                            0x2
0046 #define     IQM_RC_ADJ_SEL_B_OFF                                            0x0
0047 #define     IQM_RC_ADJ_SEL_B_QAM                                            0x1
0048 #define     IQM_RC_ADJ_SEL_B_VSB                                            0x2
0049
0050 enum operation_mode {
0051     OM_NONE,
0052     OM_QAM_ITU_A,
0053     OM_QAM_ITU_B,
0054     OM_QAM_ITU_C,
0055     OM_DVBT
0056 };
0057
0058 enum drx_power_mode {
0059     DRX_POWER_UP = 0,
0060     DRX_POWER_MODE_1,
0061     DRX_POWER_MODE_2,
0062     DRX_POWER_MODE_3,
0063     DRX_POWER_MODE_4,
0064     DRX_POWER_MODE_5,
0065     DRX_POWER_MODE_6,
0066     DRX_POWER_MODE_7,
0067     DRX_POWER_MODE_8,
0068
0069     DRX_POWER_MODE_9,
0070     DRX_POWER_MODE_10,
0071     DRX_POWER_MODE_11,
0072     DRX_POWER_MODE_12,
0073     DRX_POWER_MODE_13,
0074     DRX_POWER_MODE_14,
0075     DRX_POWER_MODE_15,
0076     DRX_POWER_MODE_16,
0077     DRX_POWER_DOWN = 255
0078 };
0079
0080
0081 /* Intermediate power mode for DRXK, power down OFDM clock domain */
0082 #ifndef DRXK_POWER_DOWN_OFDM
0083 #define DRXK_POWER_DOWN_OFDM        DRX_POWER_MODE_1
0084 #endif
0085
0086 /* Intermediate power mode for DRXK, power down core (sysclk) */
0087 #ifndef DRXK_POWER_DOWN_CORE
0088 #define DRXK_POWER_DOWN_CORE        DRX_POWER_MODE_9
0089 #endif
0090
0091 /* Intermediate power mode for DRXK, power down pll (only osc runs) */
0092 #ifndef DRXK_POWER_DOWN_PLL
0093 #define DRXK_POWER_DOWN_PLL         DRX_POWER_MODE_10
0094 #endif
0095
0096
0097 enum agc_ctrl_mode {
0098     DRXK_AGC_CTRL_AUTO = 0,
0099     DRXK_AGC_CTRL_USER,
0100     DRXK_AGC_CTRL_OFF
0101 };
0102
0103 enum e_drxk_state {
0104     DRXK_UNINITIALIZED = 0,
0105     DRXK_STOPPED,
0106     DRXK_DTV_STARTED,
0107     DRXK_ATV_STARTED,
0108     DRXK_POWERED_DOWN,
0109     DRXK_NO_DEV         /* If drxk init failed */
0110 };
0111
0112 enum e_drxk_coef_array_index {
0113     DRXK_COEF_IDX_MN = 0,
0114     DRXK_COEF_IDX_FM    ,
0115     DRXK_COEF_IDX_L     ,
0116     DRXK_COEF_IDX_LP    ,
0117     DRXK_COEF_IDX_BG    ,
0118     DRXK_COEF_IDX_DK    ,
0119     DRXK_COEF_IDX_I     ,
0120     DRXK_COEF_IDX_MAX
0121 };
0122 enum e_drxk_sif_attenuation {
0123     DRXK_SIF_ATTENUATION_0DB,
0124     DRXK_SIF_ATTENUATION_3DB,
0125     DRXK_SIF_ATTENUATION_6DB,
0126     DRXK_SIF_ATTENUATION_9DB
0127 };
0128 enum e_drxk_constellation {
0129     DRX_CONSTELLATION_BPSK = 0,
0130     DRX_CONSTELLATION_QPSK,
0131     DRX_CONSTELLATION_PSK8,
0132     DRX_CONSTELLATION_QAM16,
0133     DRX_CONSTELLATION_QAM32,
0134     DRX_CONSTELLATION_QAM64,
0135     DRX_CONSTELLATION_QAM128,
0136     DRX_CONSTELLATION_QAM256,
0137     DRX_CONSTELLATION_QAM512,
0138     DRX_CONSTELLATION_QAM1024,
0139     DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
0140     DRX_CONSTELLATION_AUTO    = DRX_AUTO
0141 };
0142 enum e_drxk_interleave_mode {
0143     DRXK_QAM_I12_J17    = 16,
0144     DRXK_QAM_I_UNKNOWN  = DRX_UNKNOWN
0145 };
0146 enum {
0147     DRXK_SPIN_A1 = 0,
0148     DRXK_SPIN_A2,
0149     DRXK_SPIN_A3,
0150     DRXK_SPIN_UNKNOWN
0151 };
0152
0153 enum drxk_cfg_dvbt_sqi_speed {
0154     DRXK_DVBT_SQI_SPEED_FAST = 0,
0155     DRXK_DVBT_SQI_SPEED_MEDIUM,
0156     DRXK_DVBT_SQI_SPEED_SLOW,
0157     DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
0158 } ;
0159
0160 enum drx_fftmode_t {
0161     DRX_FFTMODE_2K = 0,
0162     DRX_FFTMODE_4K,
0163     DRX_FFTMODE_8K,
0164     DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
0165     DRX_FFTMODE_AUTO    = DRX_AUTO
0166 };
0167
0168 enum drxmpeg_str_width_t {
0169     DRX_MPEG_STR_WIDTH_1,
0170     DRX_MPEG_STR_WIDTH_8
0171 };
0172
0173 enum drx_qam_lock_range_t {
0174     DRX_QAM_LOCKRANGE_NORMAL,
0175     DRX_QAM_LOCKRANGE_EXTENDED
0176 };
0177
0178 struct drxk_cfg_dvbt_echo_thres_t {
0179     u16             threshold;
0180     enum drx_fftmode_t      fft_mode;
0181 } ;
0182
0183 struct s_cfg_agc {
0184     enum agc_ctrl_mode     ctrl_mode;        /* off, user, auto */
0185     u16            output_level;     /* range dependent on AGC */
0186     u16            min_output_level;  /* range dependent on AGC */
0187     u16            max_output_level;  /* range dependent on AGC */
0188     u16            speed;           /* range dependent on AGC */
0189     u16            top;             /* rf-agc take over point */
0190     u16            cut_off_current;   /* rf-agc is accelerated if output current
0191                        is below cut-off current */
0192     u16            ingain_tgt_max;
0193     u16            fast_clip_ctrl_delay;
0194 };
0195
0196 struct s_cfg_pre_saw {
0197     u16        reference; /* pre SAW reference value, range 0 .. 31 */
0198     bool          use_pre_saw; /* TRUE algorithms must use pre SAW sense */
0199 };
0200
0201 struct drxk_ofdm_sc_cmd_t {
0202     u16 cmd;        /* Command number */
0203     u16 subcmd;     /* Sub-command parameter*/
0204     u16 param0;     /* General purpous param */
0205     u16 param1;     /* General purpous param */
0206     u16 param2;     /* General purpous param */
0207     u16 param3;     /* General purpous param */
0208     u16 param4;     /* General purpous param */
0209 };
0210
0211 struct drxk_state {
0212     struct dvb_frontend frontend;
0213     struct dtv_frontend_properties props;
0214     struct device *dev;
0215
0216     struct i2c_adapter *i2c;
0217     u8     demod_address;
0218     void  *priv;
0219
0220     struct mutex mutex;
0221
0222     u32    m_instance;           /* Channel 1,2,3 or 4 */
0223
0224     int    m_chunk_size;
0225     u8 chunk[256];
0226
0227     bool   m_has_lna;
0228     bool   m_has_dvbt;
0229     bool   m_has_dvbc;
0230     bool   m_has_audio;
0231     bool   m_has_atv;
0232     bool   m_has_oob;
0233     bool   m_has_sawsw;         /* TRUE if mat_tx is available */
0234     bool   m_has_gpio1;         /* TRUE if mat_rx is available */
0235     bool   m_has_gpio2;         /* TRUE if GPIO is available */
0236     bool   m_has_irqn;          /* TRUE if IRQN is available */
0237     u16    m_osc_clock_freq;
0238     u16    m_hi_cfg_timing_div;
0239     u16    m_hi_cfg_bridge_delay;
0240     u16    m_hi_cfg_wake_up_key;
0241     u16    m_hi_cfg_timeout;
0242     u16    m_hi_cfg_ctrl;
0243     s32    m_sys_clock_freq;      /* system clock frequency in kHz */
0244
0245     enum e_drxk_state    m_drxk_state;      /* State of Drxk (init,stopped,started) */
0246     enum operation_mode m_operation_mode;  /* digital standards */
0247     struct s_cfg_agc     m_vsb_rf_agc_cfg;    /* settings for VSB RF-AGC */
0248     struct s_cfg_agc     m_vsb_if_agc_cfg;    /* settings for VSB IF-AGC */
0249     u16                m_vsb_pga_cfg;      /* settings for VSB PGA */
0250     struct s_cfg_pre_saw  m_vsb_pre_saw_cfg;   /* settings for pre SAW sense */
0251     s32    m_Quality83percent;  /* MER level (*0.1 dB) for 83% quality indication */
0252     s32    m_Quality93percent;  /* MER level (*0.1 dB) for 93% quality indication */
0253     bool   m_smart_ant_inverted;
0254     bool   m_b_debug_enable_bridge;
0255     bool   m_b_p_down_open_bridge;  /* only open DRXK bridge before power-down once it has been accessed */
0256     bool   m_b_power_down;        /* Power down when not used */
0257
0258     u32    m_iqm_fs_rate_ofs;      /* frequency shift as written to DRXK register (28bit fixpoint) */
0259
0260     bool   m_enable_mpeg_output;  /* If TRUE, enable MPEG output */
0261     bool   m_insert_rs_byte;      /* If TRUE, insert RS byte */
0262     bool   m_enable_parallel;    /* If TRUE, parallel out otherwise serial */
0263     bool   m_invert_data;        /* If TRUE, invert DATA signals */
0264     bool   m_invert_err;         /* If TRUE, invert ERR signal */
0265     bool   m_invert_str;         /* If TRUE, invert STR signals */
0266     bool   m_invert_val;         /* If TRUE, invert VAL signals */
0267     bool   m_invert_clk;         /* If TRUE, invert CLK signals */
0268     bool   m_dvbc_static_clk;
0269     bool   m_dvbt_static_clk;     /* If TRUE, static MPEG clockrate will
0270                      be used, otherwise clockrate will
0271                      adapt to the bitrate of the TS */
0272     u32    m_dvbt_bitrate;
0273     u32    m_dvbc_bitrate;
0274
0275     u8     m_ts_data_strength;
0276     u8     m_ts_clockk_strength;
0277
0278     bool   m_itut_annex_c;      /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */
0279
0280     enum drxmpeg_str_width_t  m_width_str;    /* MPEG start width */
0281     u32    m_mpeg_ts_static_bitrate;          /* Maximum bitrate in b/s in case
0282                             static clockrate is selected */
0283
0284     /* LARGE_INTEGER   m_startTime; */     /* Contains the time of the last demod start */
0285     s32    m_mpeg_lock_time_out;      /* WaitForLockStatus Timeout (counts from start time) */
0286     s32    m_demod_lock_time_out;     /* WaitForLockStatus Timeout (counts from start time) */
0287
0288     bool   m_disable_te_ihandling;
0289
0290     bool   m_rf_agc_pol;
0291     bool   m_if_agc_pol;
0292
0293     struct s_cfg_agc    m_atv_rf_agc_cfg;  /* settings for ATV RF-AGC */
0294     struct s_cfg_agc    m_atv_if_agc_cfg;  /* settings for ATV IF-AGC */
0295     struct s_cfg_pre_saw m_atv_pre_saw_cfg; /* settings for ATV pre SAW sense */
0296     bool              m_phase_correction_bypass;
0297     s16               m_atv_top_vid_peak;
0298     u16               m_atv_top_noise_th;
0299     enum e_drxk_sif_attenuation m_sif_attenuation;
0300     bool              m_enable_cvbs_output;
0301     bool              m_enable_sif_output;
0302     bool              m_b_mirror_freq_spect;
0303     enum e_drxk_constellation  m_constellation; /* constellation type of the channel */
0304     u32               m_curr_symbol_rate;       /* Current QAM symbol rate */
0305     struct s_cfg_agc    m_qam_rf_agc_cfg;          /* settings for QAM RF-AGC */
0306     struct s_cfg_agc    m_qam_if_agc_cfg;          /* settings for QAM IF-AGC */
0307     u16               m_qam_pga_cfg;            /* settings for QAM PGA */
0308     struct s_cfg_pre_saw m_qam_pre_saw_cfg;         /* settings for QAM pre SAW sense */
0309     enum e_drxk_interleave_mode m_qam_interleave_mode; /* QAM Interleave mode */
0310     u16               m_fec_rs_plen;
0311     u16               m_fec_rs_prescale;
0312
0313     enum drxk_cfg_dvbt_sqi_speed m_sqi_speed;
0314
0315     u16               m_gpio;
0316     u16               m_gpio_cfg;
0317
0318     struct s_cfg_agc    m_dvbt_rf_agc_cfg;     /* settings for QAM RF-AGC */
0319     struct s_cfg_agc    m_dvbt_if_agc_cfg;     /* settings for QAM IF-AGC */
0320     struct s_cfg_pre_saw m_dvbt_pre_saw_cfg;    /* settings for QAM pre SAW sense */
0321
0322     u16               m_agcfast_clip_ctrl_delay;
0323     bool              m_adc_comp_passed;
0324     u16               m_adcCompCoef[64];
0325     u16               m_adc_state;
0326
0327     u8               *m_microcode;
0328     int               m_microcode_length;
0329     bool          m_drxk_a3_rom_code;
0330     bool              m_drxk_a3_patch_code;
0331
0332     bool              m_rfmirror;
0333     u8                m_device_spin;
0334     u32               m_iqm_rc_rate;
0335
0336     enum drx_power_mode m_current_power_mode;
0337
0338     /* when true, avoids other devices to use the I2C bus */
0339     bool          drxk_i2c_exclusive_lock;
0340
0341     /*
0342      * Configurable parameters at the driver. They stores the values found
0343      * at struct drxk_config.
0344      */
0345
0346     u16 uio_mask;   /* Bits used by UIO */
0347
0348     bool    enable_merr_cfg;
0349     bool    single_master;
0350     bool    no_i2c_bridge;
0351     bool    antenna_dvbt;
0352     u16 antenna_gpio;
0353
0354     enum fe_status fe_status;
0355
0356     /* Firmware */
0357     const char *microcode_name;
0358     struct completion fw_wait_load;
0359     const struct firmware *fw;
0360     int qam_demod_parameter_count;
0361 };
0362
0363 #define NEVER_LOCK 0
0364 #define NOT_LOCKED 1
0365 #define DEMOD_LOCK 2
0366 #define FEC_LOCK   3
0367 #define MPEG_LOCK  4
0368