media/dvb-frontends/drxk_hard.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * drxk_hard: DRX-K DVB-C/T demodulator driver
0004  *
0005  * Copyright (C) 2010-2011 Digital Devices GmbH
0006  */
0007
0008 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0009
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/moduleparam.h>
0013 #include <linux/init.h>
0014 #include <linux/delay.h>
0015 #include <linux/firmware.h>
0016 #include <linux/i2c.h>
0017 #include <linux/hardirq.h>
0018 #include <asm/div64.h>
0019
0020 #include <media/dvb_frontend.h>
0021 #include "drxk.h"
0022 #include "drxk_hard.h"
0023 #include <media/dvb_math.h>
0024
0025 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
0026 static int power_down_qam(struct drxk_state *state);
0027 static int set_dvbt_standard(struct drxk_state *state,
0028                enum operation_mode o_mode);
0029 static int set_qam_standard(struct drxk_state *state,
0030               enum operation_mode o_mode);
0031 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
0032           s32 tuner_freq_offset);
0033 static int set_dvbt_standard(struct drxk_state *state,
0034                enum operation_mode o_mode);
0035 static int dvbt_start(struct drxk_state *state);
0036 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
0037            s32 tuner_freq_offset);
0038 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
0039 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
0040 static int switch_antenna_to_qam(struct drxk_state *state);
0041 static int switch_antenna_to_dvbt(struct drxk_state *state);
0042
0043 static bool is_dvbt(struct drxk_state *state)
0044 {
0045     return state->m_operation_mode == OM_DVBT;
0046 }
0047
0048 static bool is_qam(struct drxk_state *state)
0049 {
0050     return state->m_operation_mode == OM_QAM_ITU_A ||
0051         state->m_operation_mode == OM_QAM_ITU_B ||
0052         state->m_operation_mode == OM_QAM_ITU_C;
0053 }
0054
0055 #define NOA1ROM 0
0056
0057 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
0058 #define DRXDAP_FASI_LONG_FORMAT(addr)  (((addr) & 0xFC30FF80) != 0)
0059
0060 #define DEFAULT_MER_83  165
0061 #define DEFAULT_MER_93  250
0062
0063 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
0064 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
0065 #endif
0066
0067 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
0068 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
0069 #endif
0070
0071 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
0072 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
0073
0074 #ifndef DRXK_KI_RAGC_ATV
0075 #define DRXK_KI_RAGC_ATV   4
0076 #endif
0077 #ifndef DRXK_KI_IAGC_ATV
0078 #define DRXK_KI_IAGC_ATV   6
0079 #endif
0080 #ifndef DRXK_KI_DAGC_ATV
0081 #define DRXK_KI_DAGC_ATV   7
0082 #endif
0083
0084 #ifndef DRXK_KI_RAGC_QAM
0085 #define DRXK_KI_RAGC_QAM   3
0086 #endif
0087 #ifndef DRXK_KI_IAGC_QAM
0088 #define DRXK_KI_IAGC_QAM   4
0089 #endif
0090 #ifndef DRXK_KI_DAGC_QAM
0091 #define DRXK_KI_DAGC_QAM   7
0092 #endif
0093 #ifndef DRXK_KI_RAGC_DVBT
0094 #define DRXK_KI_RAGC_DVBT  (IsA1WithPatchCode(state) ? 3 : 2)
0095 #endif
0096 #ifndef DRXK_KI_IAGC_DVBT
0097 #define DRXK_KI_IAGC_DVBT  (IsA1WithPatchCode(state) ? 4 : 2)
0098 #endif
0099 #ifndef DRXK_KI_DAGC_DVBT
0100 #define DRXK_KI_DAGC_DVBT  (IsA1WithPatchCode(state) ? 10 : 7)
0101 #endif
0102
0103 #ifndef DRXK_AGC_DAC_OFFSET
0104 #define DRXK_AGC_DAC_OFFSET (0x800)
0105 #endif
0106
0107 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
0108 #define DRXK_BANDWIDTH_8MHZ_IN_HZ  (0x8B8249L)
0109 #endif
0110
0111 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
0112 #define DRXK_BANDWIDTH_7MHZ_IN_HZ  (0x7A1200L)
0113 #endif
0114
0115 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
0116 #define DRXK_BANDWIDTH_6MHZ_IN_HZ  (0x68A1B6L)
0117 #endif
0118
0119 #ifndef DRXK_QAM_SYMBOLRATE_MAX
0120 #define DRXK_QAM_SYMBOLRATE_MAX         (7233000)
0121 #endif
0122
0123 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT    56
0124 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A   64
0125 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C   0x5FE0
0126 #define DRXK_BL_ROM_OFFSET_TAPS_BG      24
0127 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP  32
0128 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC    40
0129 #define DRXK_BL_ROM_OFFSET_TAPS_FM      48
0130 #define DRXK_BL_ROM_OFFSET_UCODE        0
0131
0132 #define DRXK_BLC_TIMEOUT                100
0133
0134 #define DRXK_BLCC_NR_ELEMENTS_TAPS      2
0135 #define DRXK_BLCC_NR_ELEMENTS_UCODE     6
0136
0137 #define DRXK_BLDC_NR_ELEMENTS_TAPS      28
0138
0139 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
0140 #define DRXK_OFDM_NE_NOTCH_WIDTH             (4)
0141 #endif
0142
0143 #define DRXK_QAM_SL_SIG_POWER_QAM16       (40960)
0144 #define DRXK_QAM_SL_SIG_POWER_QAM32       (20480)
0145 #define DRXK_QAM_SL_SIG_POWER_QAM64       (43008)
0146 #define DRXK_QAM_SL_SIG_POWER_QAM128      (20992)
0147 #define DRXK_QAM_SL_SIG_POWER_QAM256      (43520)
0148
0149 static unsigned int debug;
0150 module_param(debug, int, 0644);
0151 MODULE_PARM_DESC(debug, "enable debug messages");
0152
0153 #define dprintk(level, fmt, arg...) do {                \
0154 if (debug >= level)                         \
0155     printk(KERN_DEBUG KBUILD_MODNAME ": %s " fmt, __func__, ##arg); \
0156 } while (0)
0157
0158 static inline u32 Frac28a(u32 a, u32 c)
0159 {
0160     int i = 0;
0161     u32 Q1 = 0;
0162     u32 R0 = 0;
0163
0164     R0 = (a % c) << 4;  /* 32-28 == 4 shifts possible at max */
0165     Q1 = a / c;     /*
0166                  * integer part, only the 4 least significant
0167                  * bits will be visible in the result
0168                  */
0169
0170     /* division using radix 16, 7 nibbles in the result */
0171     for (i = 0; i < 7; i++) {
0172         Q1 = (Q1 << 4) | (R0 / c);
0173         R0 = (R0 % c) << 4;
0174     }
0175     /* rounding */
0176     if ((R0 >> 3) >= c)
0177         Q1++;
0178
0179     return Q1;
0180 }
0181
0182 static inline u32 log10times100(u32 value)
0183 {
0184     return (100L * intlog10(value)) >> 24;
0185 }
0186
0187 /***************************************************************************/
0188 /* I2C **********************************************************************/
0189 /***************************************************************************/
0190
0191 static int drxk_i2c_lock(struct drxk_state *state)
0192 {
0193     i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT);
0194     state->drxk_i2c_exclusive_lock = true;
0195
0196     return 0;
0197 }
0198
0199 static void drxk_i2c_unlock(struct drxk_state *state)
0200 {
0201     if (!state->drxk_i2c_exclusive_lock)
0202         return;
0203
0204     i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
0205     state->drxk_i2c_exclusive_lock = false;
0206 }
0207
0208 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
0209                  unsigned len)
0210 {
0211     if (state->drxk_i2c_exclusive_lock)
0212         return __i2c_transfer(state->i2c, msgs, len);
0213     else
0214         return i2c_transfer(state->i2c, msgs, len);
0215 }
0216
0217 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
0218 {
0219     struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
0220                     .buf = val, .len = 1}
0221     };
0222
0223     return drxk_i2c_transfer(state, msgs, 1);
0224 }
0225
0226 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
0227 {
0228     int status;
0229     struct i2c_msg msg = {
0230         .addr = adr, .flags = 0, .buf = data, .len = len };
0231
0232     dprintk(3, ":");
0233     if (debug > 2) {
0234         int i;
0235         for (i = 0; i < len; i++)
0236             pr_cont(" %02x", data[i]);
0237         pr_cont("\n");
0238     }
0239     status = drxk_i2c_transfer(state, &msg, 1);
0240     if (status >= 0 && status != 1)
0241         status = -EIO;
0242
0243     if (status < 0)
0244         pr_err("i2c write error at addr 0x%02x\n", adr);
0245
0246     return status;
0247 }
0248
0249 static int i2c_read(struct drxk_state *state,
0250             u8 adr, u8 *msg, int len, u8 *answ, int alen)
0251 {
0252     int status;
0253     struct i2c_msg msgs[2] = {
0254         {.addr = adr, .flags = 0,
0255                     .buf = msg, .len = len},
0256         {.addr = adr, .flags = I2C_M_RD,
0257          .buf = answ, .len = alen}
0258     };
0259
0260     status = drxk_i2c_transfer(state, msgs, 2);
0261     if (status != 2) {
0262         if (debug > 2)
0263             pr_cont(": ERROR!\n");
0264         if (status >= 0)
0265             status = -EIO;
0266
0267         pr_err("i2c read error at addr 0x%02x\n", adr);
0268         return status;
0269     }
0270     if (debug > 2) {
0271         int i;
0272         dprintk(2, ": read from");
0273         for (i = 0; i < len; i++)
0274             pr_cont(" %02x", msg[i]);
0275         pr_cont(", value = ");
0276         for (i = 0; i < alen; i++)
0277             pr_cont(" %02x", answ[i]);
0278         pr_cont("\n");
0279     }
0280     return 0;
0281 }
0282
0283 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
0284 {
0285     int status;
0286     u8 adr = state->demod_address, mm1[4], mm2[2], len;
0287
0288     if (state->single_master)
0289         flags |= 0xC0;
0290
0291     if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
0292         mm1[0] = (((reg << 1) & 0xFF) | 0x01);
0293         mm1[1] = ((reg >> 16) & 0xFF);
0294         mm1[2] = ((reg >> 24) & 0xFF) | flags;
0295         mm1[3] = ((reg >> 7) & 0xFF);
0296         len = 4;
0297     } else {
0298         mm1[0] = ((reg << 1) & 0xFF);
0299         mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
0300         len = 2;
0301     }
0302     dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
0303     status = i2c_read(state, adr, mm1, len, mm2, 2);
0304     if (status < 0)
0305         return status;
0306     if (data)
0307         *data = mm2[0] | (mm2[1] << 8);
0308
0309     return 0;
0310 }
0311
0312 static int read16(struct drxk_state *state, u32 reg, u16 *data)
0313 {
0314     return read16_flags(state, reg, data, 0);
0315 }
0316
0317 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
0318 {
0319     int status;
0320     u8 adr = state->demod_address, mm1[4], mm2[4], len;
0321
0322     if (state->single_master)
0323         flags |= 0xC0;
0324
0325     if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
0326         mm1[0] = (((reg << 1) & 0xFF) | 0x01);
0327         mm1[1] = ((reg >> 16) & 0xFF);
0328         mm1[2] = ((reg >> 24) & 0xFF) | flags;
0329         mm1[3] = ((reg >> 7) & 0xFF);
0330         len = 4;
0331     } else {
0332         mm1[0] = ((reg << 1) & 0xFF);
0333         mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
0334         len = 2;
0335     }
0336     dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
0337     status = i2c_read(state, adr, mm1, len, mm2, 4);
0338     if (status < 0)
0339         return status;
0340     if (data)
0341         *data = mm2[0] | (mm2[1] << 8) |
0342             (mm2[2] << 16) | (mm2[3] << 24);
0343
0344     return 0;
0345 }
0346
0347 static int read32(struct drxk_state *state, u32 reg, u32 *data)
0348 {
0349     return read32_flags(state, reg, data, 0);
0350 }
0351
0352 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
0353 {
0354     u8 adr = state->demod_address, mm[6], len;
0355
0356     if (state->single_master)
0357         flags |= 0xC0;
0358     if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
0359         mm[0] = (((reg << 1) & 0xFF) | 0x01);
0360         mm[1] = ((reg >> 16) & 0xFF);
0361         mm[2] = ((reg >> 24) & 0xFF) | flags;
0362         mm[3] = ((reg >> 7) & 0xFF);
0363         len = 4;
0364     } else {
0365         mm[0] = ((reg << 1) & 0xFF);
0366         mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
0367         len = 2;
0368     }
0369     mm[len] = data & 0xff;
0370     mm[len + 1] = (data >> 8) & 0xff;
0371
0372     dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
0373     return i2c_write(state, adr, mm, len + 2);
0374 }
0375
0376 static int write16(struct drxk_state *state, u32 reg, u16 data)
0377 {
0378     return write16_flags(state, reg, data, 0);
0379 }
0380
0381 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
0382 {
0383     u8 adr = state->demod_address, mm[8], len;
0384
0385     if (state->single_master)
0386         flags |= 0xC0;
0387     if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
0388         mm[0] = (((reg << 1) & 0xFF) | 0x01);
0389         mm[1] = ((reg >> 16) & 0xFF);
0390         mm[2] = ((reg >> 24) & 0xFF) | flags;
0391         mm[3] = ((reg >> 7) & 0xFF);
0392         len = 4;
0393     } else {
0394         mm[0] = ((reg << 1) & 0xFF);
0395         mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
0396         len = 2;
0397     }
0398     mm[len] = data & 0xff;
0399     mm[len + 1] = (data >> 8) & 0xff;
0400     mm[len + 2] = (data >> 16) & 0xff;
0401     mm[len + 3] = (data >> 24) & 0xff;
0402     dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
0403
0404     return i2c_write(state, adr, mm, len + 4);
0405 }
0406
0407 static int write32(struct drxk_state *state, u32 reg, u32 data)
0408 {
0409     return write32_flags(state, reg, data, 0);
0410 }
0411
0412 static int write_block(struct drxk_state *state, u32 address,
0413               const int block_size, const u8 p_block[])
0414 {
0415     int status = 0, blk_size = block_size;
0416     u8 flags = 0;
0417
0418     if (state->single_master)
0419         flags |= 0xC0;
0420
0421     while (blk_size > 0) {
0422         int chunk = blk_size > state->m_chunk_size ?
0423             state->m_chunk_size : blk_size;
0424         u8 *adr_buf = &state->chunk[0];
0425         u32 adr_length = 0;
0426
0427         if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) {
0428             adr_buf[0] = (((address << 1) & 0xFF) | 0x01);
0429             adr_buf[1] = ((address >> 16) & 0xFF);
0430             adr_buf[2] = ((address >> 24) & 0xFF);
0431             adr_buf[3] = ((address >> 7) & 0xFF);
0432             adr_buf[2] |= flags;
0433             adr_length = 4;
0434             if (chunk == state->m_chunk_size)
0435                 chunk -= 2;
0436         } else {
0437             adr_buf[0] = ((address << 1) & 0xFF);
0438             adr_buf[1] = (((address >> 16) & 0x0F) |
0439                      ((address >> 18) & 0xF0));
0440             adr_length = 2;
0441         }
0442         memcpy(&state->chunk[adr_length], p_block, chunk);
0443         dprintk(2, "(0x%08x, 0x%02x)\n", address, flags);
0444         if (debug > 1) {
0445             int i;
0446             if (p_block)
0447                 for (i = 0; i < chunk; i++)
0448                     pr_cont(" %02x", p_block[i]);
0449             pr_cont("\n");
0450         }
0451         status = i2c_write(state, state->demod_address,
0452                    &state->chunk[0], chunk + adr_length);
0453         if (status < 0) {
0454             pr_err("%s: i2c write error at addr 0x%02x\n",
0455                    __func__, address);
0456             break;
0457         }
0458         p_block += chunk;
0459         address += (chunk >> 1);
0460         blk_size -= chunk;
0461     }
0462     return status;
0463 }
0464
0465 #ifndef DRXK_MAX_RETRIES_POWERUP
0466 #define DRXK_MAX_RETRIES_POWERUP 20
0467 #endif
0468
0469 static int power_up_device(struct drxk_state *state)
0470 {
0471     int status;
0472     u8 data = 0;
0473     u16 retry_count = 0;
0474
0475     dprintk(1, "\n");
0476
0477     status = i2c_read1(state, state->demod_address, &data);
0478     if (status < 0) {
0479         do {
0480             data = 0;
0481             status = i2c_write(state, state->demod_address,
0482                        &data, 1);
0483             usleep_range(10000, 11000);
0484             retry_count++;
0485             if (status < 0)
0486                 continue;
0487             status = i2c_read1(state, state->demod_address,
0488                        &data);
0489         } while (status < 0 &&
0490              (retry_count < DRXK_MAX_RETRIES_POWERUP));
0491         if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
0492             goto error;
0493     }
0494
0495     /* Make sure all clk domains are active */
0496     status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
0497     if (status < 0)
0498         goto error;
0499     status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
0500     if (status < 0)
0501         goto error;
0502     /* Enable pll lock tests */
0503     status = write16(state, SIO_CC_PLL_LOCK__A, 1);
0504     if (status < 0)
0505         goto error;
0506
0507     state->m_current_power_mode = DRX_POWER_UP;
0508
0509 error:
0510     if (status < 0)
0511         pr_err("Error %d on %s\n", status, __func__);
0512
0513     return status;
0514 }
0515
0516
0517 static int init_state(struct drxk_state *state)
0518 {
0519     /*
0520      * FIXME: most (all?) of the values below should be moved into
0521      * struct drxk_config, as they are probably board-specific
0522      */
0523     u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO;
0524     u32 ul_vsb_if_agc_output_level = 0;
0525     u32 ul_vsb_if_agc_min_level = 0;
0526     u32 ul_vsb_if_agc_max_level = 0x7FFF;
0527     u32 ul_vsb_if_agc_speed = 3;
0528
0529     u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO;
0530     u32 ul_vsb_rf_agc_output_level = 0;
0531     u32 ul_vsb_rf_agc_min_level = 0;
0532     u32 ul_vsb_rf_agc_max_level = 0x7FFF;
0533     u32 ul_vsb_rf_agc_speed = 3;
0534     u32 ul_vsb_rf_agc_top = 9500;
0535     u32 ul_vsb_rf_agc_cut_off_current = 4000;
0536
0537     u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO;
0538     u32 ul_atv_if_agc_output_level = 0;
0539     u32 ul_atv_if_agc_min_level = 0;
0540     u32 ul_atv_if_agc_max_level = 0;
0541     u32 ul_atv_if_agc_speed = 3;
0542
0543     u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF;
0544     u32 ul_atv_rf_agc_output_level = 0;
0545     u32 ul_atv_rf_agc_min_level = 0;
0546     u32 ul_atv_rf_agc_max_level = 0;
0547     u32 ul_atv_rf_agc_top = 9500;
0548     u32 ul_atv_rf_agc_cut_off_current = 4000;
0549     u32 ul_atv_rf_agc_speed = 3;
0550
0551     u32 ulQual83 = DEFAULT_MER_83;
0552     u32 ulQual93 = DEFAULT_MER_93;
0553
0554     u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
0555     u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
0556
0557     /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
0558     /* io_pad_cfg_mode output mode is drive always */
0559     /* io_pad_cfg_drive is set to power 2 (23 mA) */
0560     u32 ul_gpio_cfg = 0x0113;
0561     u32 ul_invert_ts_clock = 0;
0562     u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
0563     u32 ul_dvbt_bitrate = 50000000;
0564     u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
0565
0566     u32 ul_insert_rs_byte = 0;
0567
0568     u32 ul_rf_mirror = 1;
0569     u32 ul_power_down = 0;
0570
0571     dprintk(1, "\n");
0572
0573     state->m_has_lna = false;
0574     state->m_has_dvbt = false;
0575     state->m_has_dvbc = false;
0576     state->m_has_atv = false;
0577     state->m_has_oob = false;
0578     state->m_has_audio = false;
0579
0580     if (!state->m_chunk_size)
0581         state->m_chunk_size = 124;
0582
0583     state->m_osc_clock_freq = 0;
0584     state->m_smart_ant_inverted = false;
0585     state->m_b_p_down_open_bridge = false;
0586
0587     /* real system clock frequency in kHz */
0588     state->m_sys_clock_freq = 151875;
0589     /* Timing div, 250ns/Psys */
0590     /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
0591     state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *
0592                    HI_I2C_DELAY) / 1000;
0593     /* Clipping */
0594     if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
0595         state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
0596     state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
0597     /* port/bridge/power down ctrl */
0598     state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
0599
0600     state->m_b_power_down = (ul_power_down != 0);
0601
0602     state->m_drxk_a3_patch_code = false;
0603
0604     /* Init AGC and PGA parameters */
0605     /* VSB IF */
0606     state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;
0607     state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;
0608     state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;
0609     state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;
0610     state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;
0611     state->m_vsb_pga_cfg = 140;
0612
0613     /* VSB RF */
0614     state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;
0615     state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;
0616     state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;
0617     state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;
0618     state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;
0619     state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;
0620     state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;
0621     state->m_vsb_pre_saw_cfg.reference = 0x07;
0622     state->m_vsb_pre_saw_cfg.use_pre_saw = true;
0623
0624     state->m_Quality83percent = DEFAULT_MER_83;
0625     state->m_Quality93percent = DEFAULT_MER_93;
0626     if (ulQual93 <= 500 && ulQual83 < ulQual93) {
0627         state->m_Quality83percent = ulQual83;
0628         state->m_Quality93percent = ulQual93;
0629     }
0630
0631     /* ATV IF */
0632     state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;
0633     state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;
0634     state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;
0635     state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;
0636     state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;
0637
0638     /* ATV RF */
0639     state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;
0640     state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;
0641     state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;
0642     state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;
0643     state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;
0644     state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;
0645     state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;
0646     state->m_atv_pre_saw_cfg.reference = 0x04;
0647     state->m_atv_pre_saw_cfg.use_pre_saw = true;
0648
0649
0650     /* DVBT RF */
0651     state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
0652     state->m_dvbt_rf_agc_cfg.output_level = 0;
0653     state->m_dvbt_rf_agc_cfg.min_output_level = 0;
0654     state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;
0655     state->m_dvbt_rf_agc_cfg.top = 0x2100;
0656     state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;
0657     state->m_dvbt_rf_agc_cfg.speed = 1;
0658
0659
0660     /* DVBT IF */
0661     state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
0662     state->m_dvbt_if_agc_cfg.output_level = 0;
0663     state->m_dvbt_if_agc_cfg.min_output_level = 0;
0664     state->m_dvbt_if_agc_cfg.max_output_level = 9000;
0665     state->m_dvbt_if_agc_cfg.top = 13424;
0666     state->m_dvbt_if_agc_cfg.cut_off_current = 0;
0667     state->m_dvbt_if_agc_cfg.speed = 3;
0668     state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;
0669     state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;
0670     /* state->m_dvbtPgaCfg = 140; */
0671
0672     state->m_dvbt_pre_saw_cfg.reference = 4;
0673     state->m_dvbt_pre_saw_cfg.use_pre_saw = false;
0674
0675     /* QAM RF */
0676     state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
0677     state->m_qam_rf_agc_cfg.output_level = 0;
0678     state->m_qam_rf_agc_cfg.min_output_level = 6023;
0679     state->m_qam_rf_agc_cfg.max_output_level = 27000;
0680     state->m_qam_rf_agc_cfg.top = 0x2380;
0681     state->m_qam_rf_agc_cfg.cut_off_current = 4000;
0682     state->m_qam_rf_agc_cfg.speed = 3;
0683
0684     /* QAM IF */
0685     state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
0686     state->m_qam_if_agc_cfg.output_level = 0;
0687     state->m_qam_if_agc_cfg.min_output_level = 0;
0688     state->m_qam_if_agc_cfg.max_output_level = 9000;
0689     state->m_qam_if_agc_cfg.top = 0x0511;
0690     state->m_qam_if_agc_cfg.cut_off_current = 0;
0691     state->m_qam_if_agc_cfg.speed = 3;
0692     state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;
0693     state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;
0694
0695     state->m_qam_pga_cfg = 140;
0696     state->m_qam_pre_saw_cfg.reference = 4;
0697     state->m_qam_pre_saw_cfg.use_pre_saw = false;
0698
0699     state->m_operation_mode = OM_NONE;
0700     state->m_drxk_state = DRXK_UNINITIALIZED;
0701
0702     /* MPEG output configuration */
0703     state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG output */
0704     state->m_insert_rs_byte = false;    /* If TRUE; insert RS byte */
0705     state->m_invert_data = false;   /* If TRUE; invert DATA signals */
0706     state->m_invert_err = false;    /* If TRUE; invert ERR signal */
0707     state->m_invert_str = false;    /* If TRUE; invert STR signals */
0708     state->m_invert_val = false;    /* If TRUE; invert VAL signals */
0709     state->m_invert_clk = (ul_invert_ts_clock != 0);    /* If TRUE; invert CLK signals */
0710
0711     /* If TRUE; static MPEG clockrate will be used;
0712        otherwise clockrate will adapt to the bitrate of the TS */
0713
0714     state->m_dvbt_bitrate = ul_dvbt_bitrate;
0715     state->m_dvbc_bitrate = ul_dvbc_bitrate;
0716
0717     state->m_ts_data_strength = (ul_ts_data_strength & 0x07);
0718
0719     /* Maximum bitrate in b/s in case static clockrate is selected */
0720     state->m_mpeg_ts_static_bitrate = 19392658;
0721     state->m_disable_te_ihandling = false;
0722
0723     if (ul_insert_rs_byte)
0724         state->m_insert_rs_byte = true;
0725
0726     state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
0727     if (ul_mpeg_lock_time_out < 10000)
0728         state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;
0729     state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
0730     if (ul_demod_lock_time_out < 10000)
0731         state->m_demod_lock_time_out = ul_demod_lock_time_out;
0732
0733     /* QAM defaults */
0734     state->m_constellation = DRX_CONSTELLATION_AUTO;
0735     state->m_qam_interleave_mode = DRXK_QAM_I12_J17;
0736     state->m_fec_rs_plen = 204 * 8; /* fecRsPlen  annex A */
0737     state->m_fec_rs_prescale = 1;
0738
0739     state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
0740     state->m_agcfast_clip_ctrl_delay = 0;
0741
0742     state->m_gpio_cfg = ul_gpio_cfg;
0743
0744     state->m_b_power_down = false;
0745     state->m_current_power_mode = DRX_POWER_DOWN;
0746
0747     state->m_rfmirror = (ul_rf_mirror == 0);
0748     state->m_if_agc_pol = false;
0749     return 0;
0750 }
0751
0752 static int drxx_open(struct drxk_state *state)
0753 {
0754     int status = 0;
0755     u32 jtag = 0;
0756     u16 bid = 0;
0757     u16 key = 0;
0758
0759     dprintk(1, "\n");
0760     /* stop lock indicator process */
0761     status = write16(state, SCU_RAM_GPIO__A,
0762              SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
0763     if (status < 0)
0764         goto error;
0765     /* Check device id */
0766     status = read16(state, SIO_TOP_COMM_KEY__A, &key);
0767     if (status < 0)
0768         goto error;
0769     status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
0770     if (status < 0)
0771         goto error;
0772     status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
0773     if (status < 0)
0774         goto error;
0775     status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
0776     if (status < 0)
0777         goto error;
0778     status = write16(state, SIO_TOP_COMM_KEY__A, key);
0779 error:
0780     if (status < 0)
0781         pr_err("Error %d on %s\n", status, __func__);
0782     return status;
0783 }
0784
0785 static int get_device_capabilities(struct drxk_state *state)
0786 {
0787     u16 sio_pdr_ohw_cfg = 0;
0788     u32 sio_top_jtagid_lo = 0;
0789     int status;
0790     const char *spin = "";
0791
0792     dprintk(1, "\n");
0793
0794     /* driver 0.9.0 */
0795     /* stop lock indicator process */
0796     status = write16(state, SCU_RAM_GPIO__A,
0797              SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
0798     if (status < 0)
0799         goto error;
0800     status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
0801     if (status < 0)
0802         goto error;
0803     status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
0804     if (status < 0)
0805         goto error;
0806     status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
0807     if (status < 0)
0808         goto error;
0809
0810     switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
0811     case 0:
0812         /* ignore (bypass ?) */
0813         break;
0814     case 1:
0815         /* 27 MHz */
0816         state->m_osc_clock_freq = 27000;
0817         break;
0818     case 2:
0819         /* 20.25 MHz */
0820         state->m_osc_clock_freq = 20250;
0821         break;
0822     case 3:
0823         /* 4 MHz */
0824         state->m_osc_clock_freq = 20250;
0825         break;
0826     default:
0827         pr_err("Clock Frequency is unknown\n");
0828         return -EINVAL;
0829     }
0830     /*
0831         Determine device capabilities
0832         Based on pinning v14
0833         */
0834     status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
0835     if (status < 0)
0836         goto error;
0837
0838     pr_info("status = 0x%08x\n", sio_top_jtagid_lo);
0839
0840     /* driver 0.9.0 */
0841     switch ((sio_top_jtagid_lo >> 29) & 0xF) {
0842     case 0:
0843         state->m_device_spin = DRXK_SPIN_A1;
0844         spin = "A1";
0845         break;
0846     case 2:
0847         state->m_device_spin = DRXK_SPIN_A2;
0848         spin = "A2";
0849         break;
0850     case 3:
0851         state->m_device_spin = DRXK_SPIN_A3;
0852         spin = "A3";
0853         break;
0854     default:
0855         state->m_device_spin = DRXK_SPIN_UNKNOWN;
0856         status = -EINVAL;
0857         pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF);
0858         goto error2;
0859     }
0860     switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
0861     case 0x13:
0862         /* typeId = DRX3913K_TYPE_ID */
0863         state->m_has_lna = false;
0864         state->m_has_oob = false;
0865         state->m_has_atv = false;
0866         state->m_has_audio = false;
0867         state->m_has_dvbt = true;
0868         state->m_has_dvbc = true;
0869         state->m_has_sawsw = true;
0870         state->m_has_gpio2 = false;
0871         state->m_has_gpio1 = false;
0872         state->m_has_irqn = false;
0873         break;
0874     case 0x15:
0875         /* typeId = DRX3915K_TYPE_ID */
0876         state->m_has_lna = false;
0877         state->m_has_oob = false;
0878         state->m_has_atv = true;
0879         state->m_has_audio = false;
0880         state->m_has_dvbt = true;
0881         state->m_has_dvbc = false;
0882         state->m_has_sawsw = true;
0883         state->m_has_gpio2 = true;
0884         state->m_has_gpio1 = true;
0885         state->m_has_irqn = false;
0886         break;
0887     case 0x16:
0888         /* typeId = DRX3916K_TYPE_ID */
0889         state->m_has_lna = false;
0890         state->m_has_oob = false;
0891         state->m_has_atv = true;
0892         state->m_has_audio = false;
0893         state->m_has_dvbt = true;
0894         state->m_has_dvbc = false;
0895         state->m_has_sawsw = true;
0896         state->m_has_gpio2 = true;
0897         state->m_has_gpio1 = true;
0898         state->m_has_irqn = false;
0899         break;
0900     case 0x18:
0901         /* typeId = DRX3918K_TYPE_ID */
0902         state->m_has_lna = false;
0903         state->m_has_oob = false;
0904         state->m_has_atv = true;
0905         state->m_has_audio = true;
0906         state->m_has_dvbt = true;
0907         state->m_has_dvbc = false;
0908         state->m_has_sawsw = true;
0909         state->m_has_gpio2 = true;
0910         state->m_has_gpio1 = true;
0911         state->m_has_irqn = false;
0912         break;
0913     case 0x21:
0914         /* typeId = DRX3921K_TYPE_ID */
0915         state->m_has_lna = false;
0916         state->m_has_oob = false;
0917         state->m_has_atv = true;
0918         state->m_has_audio = true;
0919         state->m_has_dvbt = true;
0920         state->m_has_dvbc = true;
0921         state->m_has_sawsw = true;
0922         state->m_has_gpio2 = true;
0923         state->m_has_gpio1 = true;
0924         state->m_has_irqn = false;
0925         break;
0926     case 0x23:
0927         /* typeId = DRX3923K_TYPE_ID */
0928         state->m_has_lna = false;
0929         state->m_has_oob = false;
0930         state->m_has_atv = true;
0931         state->m_has_audio = true;
0932         state->m_has_dvbt = true;
0933         state->m_has_dvbc = true;
0934         state->m_has_sawsw = true;
0935         state->m_has_gpio2 = true;
0936         state->m_has_gpio1 = true;
0937         state->m_has_irqn = false;
0938         break;
0939     case 0x25:
0940         /* typeId = DRX3925K_TYPE_ID */
0941         state->m_has_lna = false;
0942         state->m_has_oob = false;
0943         state->m_has_atv = true;
0944         state->m_has_audio = true;
0945         state->m_has_dvbt = true;
0946         state->m_has_dvbc = true;
0947         state->m_has_sawsw = true;
0948         state->m_has_gpio2 = true;
0949         state->m_has_gpio1 = true;
0950         state->m_has_irqn = false;
0951         break;
0952     case 0x26:
0953         /* typeId = DRX3926K_TYPE_ID */
0954         state->m_has_lna = false;
0955         state->m_has_oob = false;
0956         state->m_has_atv = true;
0957         state->m_has_audio = false;
0958         state->m_has_dvbt = true;
0959         state->m_has_dvbc = true;
0960         state->m_has_sawsw = true;
0961         state->m_has_gpio2 = true;
0962         state->m_has_gpio1 = true;
0963         state->m_has_irqn = false;
0964         break;
0965     default:
0966         pr_err("DeviceID 0x%02x not supported\n",
0967             ((sio_top_jtagid_lo >> 12) & 0xFF));
0968         status = -EINVAL;
0969         goto error2;
0970     }
0971
0972     pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
0973            ((sio_top_jtagid_lo >> 12) & 0xFF), spin,
0974            state->m_osc_clock_freq / 1000,
0975            state->m_osc_clock_freq % 1000);
0976
0977 error:
0978     if (status < 0)
0979         pr_err("Error %d on %s\n", status, __func__);
0980
0981 error2:
0982     return status;
0983 }
0984
0985 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
0986 {
0987     int status;
0988     bool powerdown_cmd;
0989
0990     dprintk(1, "\n");
0991
0992     /* Write command */
0993     status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
0994     if (status < 0)
0995         goto error;
0996     if (cmd == SIO_HI_RA_RAM_CMD_RESET)
0997         usleep_range(1000, 2000);
0998
0999     powerdown_cmd =
1000         (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1001             ((state->m_hi_cfg_ctrl) &
1002              SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1003             SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1004     if (!powerdown_cmd) {
1005         /* Wait until command rdy */
1006         u32 retry_count = 0;
1007         u16 wait_cmd;
1008
1009         do {
1010             usleep_range(1000, 2000);
1011             retry_count += 1;
1012             status = read16(state, SIO_HI_RA_RAM_CMD__A,
1013                       &wait_cmd);
1014         } while ((status < 0 || wait_cmd) && (retry_count < DRXK_MAX_RETRIES));
1015         if (status < 0)
1016             goto error;
1017         status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
1018     }
1019 error:
1020     if (status < 0)
1021         pr_err("Error %d on %s\n", status, __func__);
1022
1023     return status;
1024 }
1025
1026 static int hi_cfg_command(struct drxk_state *state)
1027 {
1028     int status;
1029
1030     dprintk(1, "\n");
1031
1032     mutex_lock(&state->mutex);
1033
1034     status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1035              state->m_hi_cfg_timeout);
1036     if (status < 0)
1037         goto error;
1038     status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1039              state->m_hi_cfg_ctrl);
1040     if (status < 0)
1041         goto error;
1042     status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1043              state->m_hi_cfg_wake_up_key);
1044     if (status < 0)
1045         goto error;
1046     status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1047              state->m_hi_cfg_bridge_delay);
1048     if (status < 0)
1049         goto error;
1050     status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1051              state->m_hi_cfg_timing_div);
1052     if (status < 0)
1053         goto error;
1054     status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1055              SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1056     if (status < 0)
1057         goto error;
1058     status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);
1059     if (status < 0)
1060         goto error;
1061
1062     state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1063 error:
1064     mutex_unlock(&state->mutex);
1065     if (status < 0)
1066         pr_err("Error %d on %s\n", status, __func__);
1067     return status;
1068 }
1069
1070 static int init_hi(struct drxk_state *state)
1071 {
1072     dprintk(1, "\n");
1073
1074     state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
1075     state->m_hi_cfg_timeout = 0x96FF;
1076     /* port/bridge/power down ctrl */
1077     state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1078
1079     return hi_cfg_command(state);
1080 }
1081
1082 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
1083 {
1084     int status;
1085     u16 sio_pdr_mclk_cfg = 0;
1086     u16 sio_pdr_mdx_cfg = 0;
1087     u16 err_cfg = 0;
1088
1089     dprintk(1, ": mpeg %s, %s mode\n",
1090         mpeg_enable ? "enable" : "disable",
1091         state->m_enable_parallel ? "parallel" : "serial");
1092
1093     /* stop lock indicator process */
1094     status = write16(state, SCU_RAM_GPIO__A,
1095              SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1096     if (status < 0)
1097         goto error;
1098
1099     /*  MPEG TS pad configuration */
1100     status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1101     if (status < 0)
1102         goto error;
1103
1104     if (!mpeg_enable) {
1105         /*  Set MPEG TS pads to inputmode */
1106         status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1107         if (status < 0)
1108             goto error;
1109         status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1110         if (status < 0)
1111             goto error;
1112         status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1113         if (status < 0)
1114             goto error;
1115         status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1116         if (status < 0)
1117             goto error;
1118         status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1119         if (status < 0)
1120             goto error;
1121         status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1122         if (status < 0)
1123             goto error;
1124         status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1125         if (status < 0)
1126             goto error;
1127         status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1128         if (status < 0)
1129             goto error;
1130         status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1131         if (status < 0)
1132             goto error;
1133         status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1134         if (status < 0)
1135             goto error;
1136         status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1137         if (status < 0)
1138             goto error;
1139         status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1140         if (status < 0)
1141             goto error;
1142     } else {
1143         /* Enable MPEG output */
1144         sio_pdr_mdx_cfg =
1145             ((state->m_ts_data_strength <<
1146             SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1147         sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<
1148                     SIO_PDR_MCLK_CFG_DRIVE__B) |
1149                     0x0003);
1150
1151         status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
1152         if (status < 0)
1153             goto error;
1154
1155         if (state->enable_merr_cfg)
1156             err_cfg = sio_pdr_mdx_cfg;
1157
1158         status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1159         if (status < 0)
1160             goto error;
1161         status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1162         if (status < 0)
1163             goto error;
1164
1165         if (state->m_enable_parallel) {
1166             /* parallel -> enable MD1 to MD7 */
1167             status = write16(state, SIO_PDR_MD1_CFG__A,
1168                      sio_pdr_mdx_cfg);
1169             if (status < 0)
1170                 goto error;
1171             status = write16(state, SIO_PDR_MD2_CFG__A,
1172                      sio_pdr_mdx_cfg);
1173             if (status < 0)
1174                 goto error;
1175             status = write16(state, SIO_PDR_MD3_CFG__A,
1176                      sio_pdr_mdx_cfg);
1177             if (status < 0)
1178                 goto error;
1179             status = write16(state, SIO_PDR_MD4_CFG__A,
1180                      sio_pdr_mdx_cfg);
1181             if (status < 0)
1182                 goto error;
1183             status = write16(state, SIO_PDR_MD5_CFG__A,
1184                      sio_pdr_mdx_cfg);
1185             if (status < 0)
1186                 goto error;
1187             status = write16(state, SIO_PDR_MD6_CFG__A,
1188                      sio_pdr_mdx_cfg);
1189             if (status < 0)
1190                 goto error;
1191             status = write16(state, SIO_PDR_MD7_CFG__A,
1192                      sio_pdr_mdx_cfg);
1193             if (status < 0)
1194                 goto error;
1195         } else {
1196             sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<
1197                         SIO_PDR_MD0_CFG_DRIVE__B)
1198                     | 0x0003);
1199             /* serial -> disable MD1 to MD7 */
1200             status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1201             if (status < 0)
1202                 goto error;
1203             status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1204             if (status < 0)
1205                 goto error;
1206             status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1207             if (status < 0)
1208                 goto error;
1209             status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1210             if (status < 0)
1211                 goto error;
1212             status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1213             if (status < 0)
1214                 goto error;
1215             status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1216             if (status < 0)
1217                 goto error;
1218             status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1219             if (status < 0)
1220                 goto error;
1221         }
1222         status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
1223         if (status < 0)
1224             goto error;
1225         status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
1226         if (status < 0)
1227             goto error;
1228     }
1229     /*  Enable MB output over MPEG pads and ctl input */
1230     status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1231     if (status < 0)
1232         goto error;
1233     /*  Write nomagic word to enable pdr reg write */
1234     status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1235 error:
1236     if (status < 0)
1237         pr_err("Error %d on %s\n", status, __func__);
1238     return status;
1239 }
1240
1241 static int mpegts_disable(struct drxk_state *state)
1242 {
1243     dprintk(1, "\n");
1244
1245     return mpegts_configure_pins(state, false);
1246 }
1247
1248 static int bl_chain_cmd(struct drxk_state *state,
1249               u16 rom_offset, u16 nr_of_elements, u32 time_out)
1250 {
1251     u16 bl_status = 0;
1252     int status;
1253     unsigned long end;
1254
1255     dprintk(1, "\n");
1256     mutex_lock(&state->mutex);
1257     status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1258     if (status < 0)
1259         goto error;
1260     status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
1261     if (status < 0)
1262         goto error;
1263     status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
1264     if (status < 0)
1265         goto error;
1266     status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1267     if (status < 0)
1268         goto error;
1269
1270     end = jiffies + msecs_to_jiffies(time_out);
1271     do {
1272         usleep_range(1000, 2000);
1273         status = read16(state, SIO_BL_STATUS__A, &bl_status);
1274         if (status < 0)
1275             goto error;
1276     } while ((bl_status == 0x1) &&
1277             ((time_is_after_jiffies(end))));
1278
1279     if (bl_status == 0x1) {
1280         pr_err("SIO not ready\n");
1281         status = -EINVAL;
1282         goto error2;
1283     }
1284 error:
1285     if (status < 0)
1286         pr_err("Error %d on %s\n", status, __func__);
1287 error2:
1288     mutex_unlock(&state->mutex);
1289     return status;
1290 }
1291
1292
1293 static int download_microcode(struct drxk_state *state,
1294                  const u8 p_mc_image[], u32 length)
1295 {
1296     const u8 *p_src = p_mc_image;
1297     u32 address;
1298     u16 n_blocks;
1299     u16 block_size;
1300     u32 offset = 0;
1301     u32 i;
1302     int status = 0;
1303
1304     dprintk(1, "\n");
1305
1306     /* down the drain (we don't care about MAGIC_WORD) */
1307 #if 0
1308     /* For future reference */
1309     drain = (p_src[0] << 8) | p_src[1];
1310 #endif
1311     p_src += sizeof(u16);
1312     offset += sizeof(u16);
1313     n_blocks = (p_src[0] << 8) | p_src[1];
1314     p_src += sizeof(u16);
1315     offset += sizeof(u16);
1316
1317     for (i = 0; i < n_blocks; i += 1) {
1318         address = (p_src[0] << 24) | (p_src[1] << 16) |
1319             (p_src[2] << 8) | p_src[3];
1320         p_src += sizeof(u32);
1321         offset += sizeof(u32);
1322
1323         block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16);
1324         p_src += sizeof(u16);
1325         offset += sizeof(u16);
1326
1327 #if 0
1328         /* For future reference */
1329         flags = (p_src[0] << 8) | p_src[1];
1330 #endif
1331         p_src += sizeof(u16);
1332         offset += sizeof(u16);
1333
1334 #if 0
1335         /* For future reference */
1336         block_crc = (p_src[0] << 8) | p_src[1];
1337 #endif
1338         p_src += sizeof(u16);
1339         offset += sizeof(u16);
1340
1341         if (offset + block_size > length) {
1342             pr_err("Firmware is corrupted.\n");
1343             return -EINVAL;
1344         }
1345
1346         status = write_block(state, address, block_size, p_src);
1347         if (status < 0) {
1348             pr_err("Error %d while loading firmware\n", status);
1349             break;
1350         }
1351         p_src += block_size;
1352         offset += block_size;
1353     }
1354     return status;
1355 }
1356
1357 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
1358 {
1359     int status;
1360     u16 data = 0;
1361     u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1362     u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1363     unsigned long end;
1364
1365     dprintk(1, "\n");
1366
1367     if (!enable) {
1368         desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1369         desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1370     }
1371
1372     status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1373     if (status >= 0 && data == desired_status) {
1374         /* tokenring already has correct status */
1375         return status;
1376     }
1377     /* Disable/enable dvbt tokenring bridge   */
1378     status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
1379
1380     end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1381     do {
1382         status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1383         if ((status >= 0 && data == desired_status)
1384             || time_is_after_jiffies(end))
1385             break;
1386         usleep_range(1000, 2000);
1387     } while (1);
1388     if (data != desired_status) {
1389         pr_err("SIO not ready\n");
1390         return -EINVAL;
1391     }
1392     return status;
1393 }
1394
1395 static int mpegts_stop(struct drxk_state *state)
1396 {
1397     int status = 0;
1398     u16 fec_oc_snc_mode = 0;
1399     u16 fec_oc_ipr_mode = 0;
1400
1401     dprintk(1, "\n");
1402
1403     /* Graceful shutdown (byte boundaries) */
1404     status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1405     if (status < 0)
1406         goto error;
1407     fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1408     status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1409     if (status < 0)
1410         goto error;
1411
1412     /* Suppress MCLK during absence of data */
1413     status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
1414     if (status < 0)
1415         goto error;
1416     fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1417     status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
1418
1419 error:
1420     if (status < 0)
1421         pr_err("Error %d on %s\n", status, __func__);
1422
1423     return status;
1424 }
1425
1426 static int scu_command(struct drxk_state *state,
1427                u16 cmd, u8 parameter_len,
1428                u16 *parameter, u8 result_len, u16 *result)
1429 {
1430 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1431 #error DRXK register mapping no longer compatible with this routine!
1432 #endif
1433     u16 cur_cmd = 0;
1434     int status = -EINVAL;
1435     unsigned long end;
1436     u8 buffer[34];
1437     int cnt = 0, ii;
1438     const char *p;
1439     char errname[30];
1440
1441     dprintk(1, "\n");
1442
1443     if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) ||
1444         ((result_len > 0) && (result == NULL))) {
1445         pr_err("Error %d on %s\n", status, __func__);
1446         return status;
1447     }
1448
1449     mutex_lock(&state->mutex);
1450
1451     /* assume that the command register is ready
1452         since it is checked afterwards */
1453     if (parameter) {
1454         for (ii = parameter_len - 1; ii >= 0; ii -= 1) {
1455             buffer[cnt++] = (parameter[ii] & 0xFF);
1456             buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1457         }
1458     }
1459     buffer[cnt++] = (cmd & 0xFF);
1460     buffer[cnt++] = ((cmd >> 8) & 0xFF);
1461
1462     write_block(state, SCU_RAM_PARAM_0__A -
1463             (parameter_len - 1), cnt, buffer);
1464     /* Wait until SCU has processed command */
1465     end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1466     do {
1467         usleep_range(1000, 2000);
1468         status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
1469         if (status < 0)
1470             goto error;
1471     } while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1472     if (cur_cmd != DRX_SCU_READY) {
1473         pr_err("SCU not ready\n");
1474         status = -EIO;
1475         goto error2;
1476     }
1477     /* read results */
1478     if ((result_len > 0) && (result != NULL)) {
1479         s16 err;
1480         int ii;
1481
1482         for (ii = result_len - 1; ii >= 0; ii -= 1) {
1483             status = read16(state, SCU_RAM_PARAM_0__A - ii,
1484                     &result[ii]);
1485             if (status < 0)
1486                 goto error;
1487         }
1488
1489         /* Check if an error was reported by SCU */
1490         err = (s16)result[0];
1491         if (err >= 0)
1492             goto error;
1493
1494         /* check for the known error codes */
1495         switch (err) {
1496         case SCU_RESULT_UNKCMD:
1497             p = "SCU_RESULT_UNKCMD";
1498             break;
1499         case SCU_RESULT_UNKSTD:
1500             p = "SCU_RESULT_UNKSTD";
1501             break;
1502         case SCU_RESULT_SIZE:
1503             p = "SCU_RESULT_SIZE";
1504             break;
1505         case SCU_RESULT_INVPAR:
1506             p = "SCU_RESULT_INVPAR";
1507             break;
1508         default: /* Other negative values are errors */
1509             sprintf(errname, "ERROR: %d\n", err);
1510             p = errname;
1511         }
1512         pr_err("%s while sending cmd 0x%04x with params:", p, cmd);
1513         print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1514         status = -EINVAL;
1515         goto error2;
1516     }
1517
1518 error:
1519     if (status < 0)
1520         pr_err("Error %d on %s\n", status, __func__);
1521 error2:
1522     mutex_unlock(&state->mutex);
1523     return status;
1524 }
1525
1526 static int set_iqm_af(struct drxk_state *state, bool active)
1527 {
1528     u16 data = 0;
1529     int status;
1530
1531     dprintk(1, "\n");
1532
1533     /* Configure IQM */
1534     status = read16(state, IQM_AF_STDBY__A, &data);
1535     if (status < 0)
1536         goto error;
1537
1538     if (!active) {
1539         data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1540                 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1541                 | IQM_AF_STDBY_STDBY_PD_STANDBY
1542                 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1543                 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1544     } else {
1545         data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1546                 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1547                 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1548                 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1549                 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1550             );
1551     }
1552     status = write16(state, IQM_AF_STDBY__A, data);
1553
1554 error:
1555     if (status < 0)
1556         pr_err("Error %d on %s\n", status, __func__);
1557     return status;
1558 }
1559
1560 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)
1561 {
1562     int status = 0;
1563     u16 sio_cc_pwd_mode = 0;
1564
1565     dprintk(1, "\n");
1566
1567     /* Check arguments */
1568     if (mode == NULL)
1569         return -EINVAL;
1570
1571     switch (*mode) {
1572     case DRX_POWER_UP:
1573         sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
1574         break;
1575     case DRXK_POWER_DOWN_OFDM:
1576         sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1577         break;
1578     case DRXK_POWER_DOWN_CORE:
1579         sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1580         break;
1581     case DRXK_POWER_DOWN_PLL:
1582         sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
1583         break;
1584     case DRX_POWER_DOWN:
1585         sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
1586         break;
1587     default:
1588         /* Unknow sleep mode */
1589         return -EINVAL;
1590     }
1591
1592     /* If already in requested power mode, do nothing */
1593     if (state->m_current_power_mode == *mode)
1594         return 0;
1595
1596     /* For next steps make sure to start from DRX_POWER_UP mode */
1597     if (state->m_current_power_mode != DRX_POWER_UP) {
1598         status = power_up_device(state);
1599         if (status < 0)
1600             goto error;
1601         status = dvbt_enable_ofdm_token_ring(state, true);
1602         if (status < 0)
1603             goto error;
1604     }
1605
1606     if (*mode == DRX_POWER_UP) {
1607         /* Restore analog & pin configuration */
1608     } else {
1609         /* Power down to requested mode */
1610         /* Backup some register settings */
1611         /* Set pins with possible pull-ups connected
1612            to them in input mode */
1613         /* Analog power down */
1614         /* ADC power down */
1615         /* Power down device */
1616         /* stop all comm_exec */
1617         /* Stop and power down previous standard */
1618         switch (state->m_operation_mode) {
1619         case OM_DVBT:
1620             status = mpegts_stop(state);
1621             if (status < 0)
1622                 goto error;
1623             status = power_down_dvbt(state, false);
1624             if (status < 0)
1625                 goto error;
1626             break;
1627         case OM_QAM_ITU_A:
1628         case OM_QAM_ITU_C:
1629             status = mpegts_stop(state);
1630             if (status < 0)
1631                 goto error;
1632             status = power_down_qam(state);
1633             if (status < 0)
1634                 goto error;
1635             break;
1636         default:
1637             break;
1638         }
1639         status = dvbt_enable_ofdm_token_ring(state, false);
1640         if (status < 0)
1641             goto error;
1642         status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
1643         if (status < 0)
1644             goto error;
1645         status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1646         if (status < 0)
1647             goto error;
1648
1649         if (*mode != DRXK_POWER_DOWN_OFDM) {
1650             state->m_hi_cfg_ctrl |=
1651                 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1652             status = hi_cfg_command(state);
1653             if (status < 0)
1654                 goto error;
1655         }
1656     }
1657     state->m_current_power_mode = *mode;
1658
1659 error:
1660     if (status < 0)
1661         pr_err("Error %d on %s\n", status, __func__);
1662
1663     return status;
1664 }
1665
1666 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
1667 {
1668     enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
1669     u16 cmd_result = 0;
1670     u16 data = 0;
1671     int status;
1672
1673     dprintk(1, "\n");
1674
1675     status = read16(state, SCU_COMM_EXEC__A, &data);
1676     if (status < 0)
1677         goto error;
1678     if (data == SCU_COMM_EXEC_ACTIVE) {
1679         /* Send OFDM stop command */
1680         status = scu_command(state,
1681                      SCU_RAM_COMMAND_STANDARD_OFDM
1682                      | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
1683                      0, NULL, 1, &cmd_result);
1684         if (status < 0)
1685             goto error;
1686         /* Send OFDM reset command */
1687         status = scu_command(state,
1688                      SCU_RAM_COMMAND_STANDARD_OFDM
1689                      | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
1690                      0, NULL, 1, &cmd_result);
1691         if (status < 0)
1692             goto error;
1693     }
1694
1695     /* Reset datapath for OFDM, processors first */
1696     status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1697     if (status < 0)
1698         goto error;
1699     status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1700     if (status < 0)
1701         goto error;
1702     status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1703     if (status < 0)
1704         goto error;
1705
1706     /* powerdown AFE                   */
1707     status = set_iqm_af(state, false);
1708     if (status < 0)
1709         goto error;
1710
1711     /* powerdown to OFDM mode          */
1712     if (set_power_mode) {
1713         status = ctrl_power_mode(state, &power_mode);
1714         if (status < 0)
1715             goto error;
1716     }
1717 error:
1718     if (status < 0)
1719         pr_err("Error %d on %s\n", status, __func__);
1720     return status;
1721 }
1722
1723 static int setoperation_mode(struct drxk_state *state,
1724                 enum operation_mode o_mode)
1725 {
1726     int status = 0;
1727
1728     dprintk(1, "\n");
1729     /*
1730        Stop and power down previous standard
1731        TODO investigate total power down instead of partial
1732        power down depending on "previous" standard.
1733      */
1734
1735     /* disable HW lock indicator */
1736     status = write16(state, SCU_RAM_GPIO__A,
1737              SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1738     if (status < 0)
1739         goto error;
1740
1741     /* Device is already at the required mode */
1742     if (state->m_operation_mode == o_mode)
1743         return 0;
1744
1745     switch (state->m_operation_mode) {
1746         /* OM_NONE was added for start up */
1747     case OM_NONE:
1748         break;
1749     case OM_DVBT:
1750         status = mpegts_stop(state);
1751         if (status < 0)
1752             goto error;
1753         status = power_down_dvbt(state, true);
1754         if (status < 0)
1755             goto error;
1756         state->m_operation_mode = OM_NONE;
1757         break;
1758     case OM_QAM_ITU_A:
1759     case OM_QAM_ITU_C:
1760         status = mpegts_stop(state);
1761         if (status < 0)
1762             goto error;
1763         status = power_down_qam(state);
1764         if (status < 0)
1765             goto error;
1766         state->m_operation_mode = OM_NONE;
1767         break;
1768     case OM_QAM_ITU_B:
1769     default:
1770         status = -EINVAL;
1771         goto error;
1772     }
1773
1774     /*
1775         Power up new standard
1776         */
1777     switch (o_mode) {
1778     case OM_DVBT:
1779         dprintk(1, ": DVB-T\n");
1780         state->m_operation_mode = o_mode;
1781         status = set_dvbt_standard(state, o_mode);
1782         if (status < 0)
1783             goto error;
1784         break;
1785     case OM_QAM_ITU_A:
1786     case OM_QAM_ITU_C:
1787         dprintk(1, ": DVB-C Annex %c\n",
1788             (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');
1789         state->m_operation_mode = o_mode;
1790         status = set_qam_standard(state, o_mode);
1791         if (status < 0)
1792             goto error;
1793         break;
1794     case OM_QAM_ITU_B:
1795     default:
1796         status = -EINVAL;
1797     }
1798 error:
1799     if (status < 0)
1800         pr_err("Error %d on %s\n", status, __func__);
1801     return status;
1802 }
1803
1804 static int start(struct drxk_state *state, s32 offset_freq,
1805          s32 intermediate_frequency)
1806 {
1807     int status = -EINVAL;
1808
1809     u16 i_freqk_hz;
1810     s32 offsetk_hz = offset_freq / 1000;
1811
1812     dprintk(1, "\n");
1813     if (state->m_drxk_state != DRXK_STOPPED &&
1814         state->m_drxk_state != DRXK_DTV_STARTED)
1815         goto error;
1816
1817     state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);
1818
1819     if (intermediate_frequency < 0) {
1820         state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;
1821         intermediate_frequency = -intermediate_frequency;
1822     }
1823
1824     switch (state->m_operation_mode) {
1825     case OM_QAM_ITU_A:
1826     case OM_QAM_ITU_C:
1827         i_freqk_hz = (intermediate_frequency / 1000);
1828         status = set_qam(state, i_freqk_hz, offsetk_hz);
1829         if (status < 0)
1830             goto error;
1831         state->m_drxk_state = DRXK_DTV_STARTED;
1832         break;
1833     case OM_DVBT:
1834         i_freqk_hz = (intermediate_frequency / 1000);
1835         status = mpegts_stop(state);
1836         if (status < 0)
1837             goto error;
1838         status = set_dvbt(state, i_freqk_hz, offsetk_hz);
1839         if (status < 0)
1840             goto error;
1841         status = dvbt_start(state);
1842         if (status < 0)
1843             goto error;
1844         state->m_drxk_state = DRXK_DTV_STARTED;
1845         break;
1846     default:
1847         break;
1848     }
1849 error:
1850     if (status < 0)
1851         pr_err("Error %d on %s\n", status, __func__);
1852     return status;
1853 }
1854
1855 static int shut_down(struct drxk_state *state)
1856 {
1857     dprintk(1, "\n");
1858
1859     mpegts_stop(state);
1860     return 0;
1861 }
1862
1863 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)
1864 {
1865     int status = -EINVAL;
1866
1867     dprintk(1, "\n");
1868
1869     if (p_lock_status == NULL)
1870         goto error;
1871
1872     *p_lock_status = NOT_LOCKED;
1873
1874     /* define the SCU command code */
1875     switch (state->m_operation_mode) {
1876     case OM_QAM_ITU_A:
1877     case OM_QAM_ITU_B:
1878     case OM_QAM_ITU_C:
1879         status = get_qam_lock_status(state, p_lock_status);
1880         break;
1881     case OM_DVBT:
1882         status = get_dvbt_lock_status(state, p_lock_status);
1883         break;
1884     default:
1885         pr_debug("Unsupported operation mode %d in %s\n",
1886             state->m_operation_mode, __func__);
1887         return 0;
1888     }
1889 error:
1890     if (status < 0)
1891         pr_err("Error %d on %s\n", status, __func__);
1892     return status;
1893 }
1894
1895 static int mpegts_start(struct drxk_state *state)
1896 {
1897     int status;
1898
1899     u16 fec_oc_snc_mode = 0;
1900
1901     /* Allow OC to sync again */
1902     status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1903     if (status < 0)
1904         goto error;
1905     fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1906     status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1907     if (status < 0)
1908         goto error;
1909     status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1910 error:
1911     if (status < 0)
1912         pr_err("Error %d on %s\n", status, __func__);
1913     return status;
1914 }
1915
1916 static int mpegts_dto_init(struct drxk_state *state)
1917 {
1918     int status;
1919
1920     dprintk(1, "\n");
1921
1922     /* Rate integration settings */
1923     status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1924     if (status < 0)
1925         goto error;
1926     status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1927     if (status < 0)
1928         goto error;
1929     status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1930     if (status < 0)
1931         goto error;
1932     status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1933     if (status < 0)
1934         goto error;
1935     status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1936     if (status < 0)
1937         goto error;
1938     status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1939     if (status < 0)
1940         goto error;
1941     status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1942     if (status < 0)
1943         goto error;
1944     status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1945     if (status < 0)
1946         goto error;
1947
1948     /* Additional configuration */
1949     status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1950     if (status < 0)
1951         goto error;
1952     status = write16(state, FEC_OC_SNC_LWM__A, 2);
1953     if (status < 0)
1954         goto error;
1955     status = write16(state, FEC_OC_SNC_HWM__A, 12);
1956 error:
1957     if (status < 0)
1958         pr_err("Error %d on %s\n", status, __func__);
1959
1960     return status;
1961 }
1962
1963 static int mpegts_dto_setup(struct drxk_state *state,
1964               enum operation_mode o_mode)
1965 {
1966     int status;
1967
1968     u16 fec_oc_reg_mode = 0;    /* FEC_OC_MODE       register value */
1969     u16 fec_oc_reg_ipr_mode = 0;    /* FEC_OC_IPR_MODE   register value */
1970     u16 fec_oc_dto_mode = 0;    /* FEC_OC_IPR_INVERT register value */
1971     u16 fec_oc_fct_mode = 0;    /* FEC_OC_IPR_INVERT register value */
1972     u16 fec_oc_dto_period = 2;  /* FEC_OC_IPR_INVERT register value */
1973     u16 fec_oc_dto_burst_len = 188; /* FEC_OC_IPR_INVERT register value */
1974     u32 fec_oc_rcn_ctl_rate = 0;    /* FEC_OC_IPR_INVERT register value */
1975     u16 fec_oc_tmd_mode = 0;
1976     u16 fec_oc_tmd_int_upd_rate = 0;
1977     u32 max_bit_rate = 0;
1978     bool static_clk = false;
1979
1980     dprintk(1, "\n");
1981
1982     /* Check insertion of the Reed-Solomon parity bytes */
1983     status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
1984     if (status < 0)
1985         goto error;
1986     status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
1987     if (status < 0)
1988         goto error;
1989     fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
1990     fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
1991     if (state->m_insert_rs_byte) {
1992         /* enable parity symbol forward */
1993         fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
1994         /* MVAL disable during parity bytes */
1995         fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
1996         /* TS burst length to 204 */
1997         fec_oc_dto_burst_len = 204;
1998     }
1999
2000     /* Check serial or parallel output */
2001     fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2002     if (!state->m_enable_parallel) {
2003         /* MPEG data output is serial -> set ipr_mode[0] */
2004         fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2005     }
2006
2007     switch (o_mode) {
2008     case OM_DVBT:
2009         max_bit_rate = state->m_dvbt_bitrate;
2010         fec_oc_tmd_mode = 3;
2011         fec_oc_rcn_ctl_rate = 0xC00000;
2012         static_clk = state->m_dvbt_static_clk;
2013         break;
2014     case OM_QAM_ITU_A:
2015     case OM_QAM_ITU_C:
2016         fec_oc_tmd_mode = 0x0004;
2017         fec_oc_rcn_ctl_rate = 0xD2B4EE; /* good for >63 Mb/s */
2018         max_bit_rate = state->m_dvbc_bitrate;
2019         static_clk = state->m_dvbc_static_clk;
2020         break;
2021     default:
2022         status = -EINVAL;
2023     }       /* switch (standard) */
2024     if (status < 0)
2025         goto error;
2026
2027     /* Configure DTO's */
2028     if (static_clk) {
2029         u32 bit_rate = 0;
2030
2031         /* Rational DTO for MCLK source (static MCLK rate),
2032             Dynamic DTO for optimal grouping
2033             (avoid intra-packet gaps),
2034             DTO offset enable to sync TS burst with MSTRT */
2035         fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2036                 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2037         fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2038                 FEC_OC_FCT_MODE_VIRT_ENA__M);
2039
2040         /* Check user defined bitrate */
2041         bit_rate = max_bit_rate;
2042         if (bit_rate > 75900000UL) {    /* max is 75.9 Mb/s */
2043             bit_rate = 75900000UL;
2044         }
2045         /* Rational DTO period:
2046             dto_period = (Fsys / bitrate) - 2
2047
2048             result should be floored,
2049             to make sure >= requested bitrate
2050             */
2051         fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)
2052                         * 1000) / bit_rate);
2053         if (fec_oc_dto_period <= 2)
2054             fec_oc_dto_period = 0;
2055         else
2056             fec_oc_dto_period -= 2;
2057         fec_oc_tmd_int_upd_rate = 8;
2058     } else {
2059         /* (commonAttr->static_clk == false) => dynamic mode */
2060         fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M;
2061         fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE;
2062         fec_oc_tmd_int_upd_rate = 5;
2063     }
2064
2065     /* Write appropriate registers with requested configuration */
2066     status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
2067     if (status < 0)
2068         goto error;
2069     status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
2070     if (status < 0)
2071         goto error;
2072     status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
2073     if (status < 0)
2074         goto error;
2075     status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
2076     if (status < 0)
2077         goto error;
2078     status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
2079     if (status < 0)
2080         goto error;
2081     status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
2082     if (status < 0)
2083         goto error;
2084
2085     /* Rate integration settings */
2086     status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2087     if (status < 0)
2088         goto error;
2089     status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2090              fec_oc_tmd_int_upd_rate);
2091     if (status < 0)
2092         goto error;
2093     status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
2094 error:
2095     if (status < 0)
2096         pr_err("Error %d on %s\n", status, __func__);
2097     return status;
2098 }
2099
2100 static int mpegts_configure_polarity(struct drxk_state *state)
2101 {
2102     u16 fec_oc_reg_ipr_invert = 0;
2103
2104     /* Data mask for the output data byte */
2105     u16 invert_data_mask =
2106         FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2107         FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2108         FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2109         FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2110
2111     dprintk(1, "\n");
2112
2113     /* Control selective inversion of output bits */
2114     fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2115     if (state->m_invert_data)
2116         fec_oc_reg_ipr_invert |= invert_data_mask;
2117     fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2118     if (state->m_invert_err)
2119         fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2120     fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2121     if (state->m_invert_str)
2122         fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2123     fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2124     if (state->m_invert_val)
2125         fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
2126     fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2127     if (state->m_invert_clk)
2128         fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
2129
2130     return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
2131 }
2132
2133 #define   SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2134
2135 static int set_agc_rf(struct drxk_state *state,
2136             struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2137 {
2138     int status = -EINVAL;
2139     u16 data = 0;
2140     struct s_cfg_agc *p_if_agc_settings;
2141
2142     dprintk(1, "\n");
2143
2144     if (p_agc_cfg == NULL)
2145         goto error;
2146
2147     switch (p_agc_cfg->ctrl_mode) {
2148     case DRXK_AGC_CTRL_AUTO:
2149         /* Enable RF AGC DAC */
2150         status = read16(state, IQM_AF_STDBY__A, &data);
2151         if (status < 0)
2152             goto error;
2153         data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2154         status = write16(state, IQM_AF_STDBY__A, data);
2155         if (status < 0)
2156             goto error;
2157         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2158         if (status < 0)
2159             goto error;
2160
2161         /* Enable SCU RF AGC loop */
2162         data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2163
2164         /* Polarity */
2165         if (state->m_rf_agc_pol)
2166             data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2167         else
2168             data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2169         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2170         if (status < 0)
2171             goto error;
2172
2173         /* Set speed (using complementary reduction value) */
2174         status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2175         if (status < 0)
2176             goto error;
2177
2178         data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2179         data |= (~(p_agc_cfg->speed <<
2180                 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2181                 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2182
2183         status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2184         if (status < 0)
2185             goto error;
2186
2187         if (is_dvbt(state))
2188             p_if_agc_settings = &state->m_dvbt_if_agc_cfg;
2189         else if (is_qam(state))
2190             p_if_agc_settings = &state->m_qam_if_agc_cfg;
2191         else
2192             p_if_agc_settings = &state->m_atv_if_agc_cfg;
2193         if (p_if_agc_settings == NULL) {
2194             status = -EINVAL;
2195             goto error;
2196         }
2197
2198         /* Set TOP, only if IF-AGC is in AUTO mode */
2199         if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) {
2200             status = write16(state,
2201                      SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2202                      p_agc_cfg->top);
2203             if (status < 0)
2204                 goto error;
2205         }
2206
2207         /* Cut-Off current */
2208         status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2209                  p_agc_cfg->cut_off_current);
2210         if (status < 0)
2211             goto error;
2212
2213         /* Max. output level */
2214         status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2215                  p_agc_cfg->max_output_level);
2216         if (status < 0)
2217             goto error;
2218
2219         break;
2220
2221     case DRXK_AGC_CTRL_USER:
2222         /* Enable RF AGC DAC */
2223         status = read16(state, IQM_AF_STDBY__A, &data);
2224         if (status < 0)
2225             goto error;
2226         data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2227         status = write16(state, IQM_AF_STDBY__A, data);
2228         if (status < 0)
2229             goto error;
2230
2231         /* Disable SCU RF AGC loop */
2232         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2233         if (status < 0)
2234             goto error;
2235         data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2236         if (state->m_rf_agc_pol)
2237             data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2238         else
2239             data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2240         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2241         if (status < 0)
2242             goto error;
2243
2244         /* SCU c.o.c. to 0, enabling full control range */
2245         status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2246         if (status < 0)
2247             goto error;
2248
2249         /* Write value to output pin */
2250         status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2251                  p_agc_cfg->output_level);
2252         if (status < 0)
2253             goto error;
2254         break;
2255
2256     case DRXK_AGC_CTRL_OFF:
2257         /* Disable RF AGC DAC */
2258         status = read16(state, IQM_AF_STDBY__A, &data);
2259         if (status < 0)
2260             goto error;
2261         data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2262         status = write16(state, IQM_AF_STDBY__A, data);
2263         if (status < 0)
2264             goto error;
2265
2266         /* Disable SCU RF AGC loop */
2267         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2268         if (status < 0)
2269             goto error;
2270         data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2271         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2272         if (status < 0)
2273             goto error;
2274         break;
2275
2276     default:
2277         status = -EINVAL;
2278
2279     }
2280 error:
2281     if (status < 0)
2282         pr_err("Error %d on %s\n", status, __func__);
2283     return status;
2284 }
2285
2286 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2287
2288 static int set_agc_if(struct drxk_state *state,
2289             struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2290 {
2291     u16 data = 0;
2292     int status = 0;
2293     struct s_cfg_agc *p_rf_agc_settings;
2294
2295     dprintk(1, "\n");
2296
2297     switch (p_agc_cfg->ctrl_mode) {
2298     case DRXK_AGC_CTRL_AUTO:
2299
2300         /* Enable IF AGC DAC */
2301         status = read16(state, IQM_AF_STDBY__A, &data);
2302         if (status < 0)
2303             goto error;
2304         data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2305         status = write16(state, IQM_AF_STDBY__A, data);
2306         if (status < 0)
2307             goto error;
2308
2309         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2310         if (status < 0)
2311             goto error;
2312
2313         /* Enable SCU IF AGC loop */
2314         data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2315
2316         /* Polarity */
2317         if (state->m_if_agc_pol)
2318             data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2319         else
2320             data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2321         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2322         if (status < 0)
2323             goto error;
2324
2325         /* Set speed (using complementary reduction value) */
2326         status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2327         if (status < 0)
2328             goto error;
2329         data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2330         data |= (~(p_agc_cfg->speed <<
2331                 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2332                 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2333
2334         status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2335         if (status < 0)
2336             goto error;
2337
2338         if (is_qam(state))
2339             p_rf_agc_settings = &state->m_qam_rf_agc_cfg;
2340         else
2341             p_rf_agc_settings = &state->m_atv_rf_agc_cfg;
2342         if (p_rf_agc_settings == NULL)
2343             return -1;
2344         /* Restore TOP */
2345         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2346                  p_rf_agc_settings->top);
2347         if (status < 0)
2348             goto error;
2349         break;
2350
2351     case DRXK_AGC_CTRL_USER:
2352
2353         /* Enable IF AGC DAC */
2354         status = read16(state, IQM_AF_STDBY__A, &data);
2355         if (status < 0)
2356             goto error;
2357         data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2358         status = write16(state, IQM_AF_STDBY__A, data);
2359         if (status < 0)
2360             goto error;
2361
2362         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2363         if (status < 0)
2364             goto error;
2365
2366         /* Disable SCU IF AGC loop */
2367         data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2368
2369         /* Polarity */
2370         if (state->m_if_agc_pol)
2371             data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2372         else
2373             data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2374         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2375         if (status < 0)
2376             goto error;
2377
2378         /* Write value to output pin */
2379         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2380                  p_agc_cfg->output_level);
2381         if (status < 0)
2382             goto error;
2383         break;
2384
2385     case DRXK_AGC_CTRL_OFF:
2386
2387         /* Disable If AGC DAC */
2388         status = read16(state, IQM_AF_STDBY__A, &data);
2389         if (status < 0)
2390             goto error;
2391         data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2392         status = write16(state, IQM_AF_STDBY__A, data);
2393         if (status < 0)
2394             goto error;
2395
2396         /* Disable SCU IF AGC loop */
2397         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2398         if (status < 0)
2399             goto error;
2400         data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2401         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2402         if (status < 0)
2403             goto error;
2404         break;
2405     }       /* switch (agcSettingsIf->ctrl_mode) */
2406
2407     /* always set the top to support
2408         configurations without if-loop */
2409     status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
2410 error:
2411     if (status < 0)
2412         pr_err("Error %d on %s\n", status, __func__);
2413     return status;
2414 }
2415
2416 static int get_qam_signal_to_noise(struct drxk_state *state,
2417                    s32 *p_signal_to_noise)
2418 {
2419     int status = 0;
2420     u16 qam_sl_err_power = 0;   /* accum. error between
2421                     raw and sliced symbols */
2422     u32 qam_sl_sig_power = 0;   /* used for MER, depends of
2423                     QAM modulation */
2424     u32 qam_sl_mer = 0; /* QAM MER */
2425
2426     dprintk(1, "\n");
2427
2428     /* MER calculation */
2429
2430     /* get the register value needed for MER */
2431     status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
2432     if (status < 0) {
2433         pr_err("Error %d on %s\n", status, __func__);
2434         return -EINVAL;
2435     }
2436
2437     switch (state->props.modulation) {
2438     case QAM_16:
2439         qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2440         break;
2441     case QAM_32:
2442         qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2443         break;
2444     case QAM_64:
2445         qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2446         break;
2447     case QAM_128:
2448         qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2449         break;
2450     default:
2451     case QAM_256:
2452         qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2453         break;
2454     }
2455
2456     if (qam_sl_err_power > 0) {
2457         qam_sl_mer = log10times100(qam_sl_sig_power) -
2458             log10times100((u32) qam_sl_err_power);
2459     }
2460     *p_signal_to_noise = qam_sl_mer;
2461
2462     return status;
2463 }
2464
2465 static int get_dvbt_signal_to_noise(struct drxk_state *state,
2466                 s32 *p_signal_to_noise)
2467 {
2468     int status;
2469     u16 reg_data = 0;
2470     u32 eq_reg_td_sqr_err_i = 0;
2471     u32 eq_reg_td_sqr_err_q = 0;
2472     u16 eq_reg_td_sqr_err_exp = 0;
2473     u16 eq_reg_td_tps_pwr_ofs = 0;
2474     u16 eq_reg_td_req_smb_cnt = 0;
2475     u32 tps_cnt = 0;
2476     u32 sqr_err_iq = 0;
2477     u32 a = 0;
2478     u32 b = 0;
2479     u32 c = 0;
2480     u32 i_mer = 0;
2481     u16 transmission_params = 0;
2482
2483     dprintk(1, "\n");
2484
2485     status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2486             &eq_reg_td_tps_pwr_ofs);
2487     if (status < 0)
2488         goto error;
2489     status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2490             &eq_reg_td_req_smb_cnt);
2491     if (status < 0)
2492         goto error;
2493     status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2494             &eq_reg_td_sqr_err_exp);
2495     if (status < 0)
2496         goto error;
2497     status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2498             &reg_data);
2499     if (status < 0)
2500         goto error;
2501     /* Extend SQR_ERR_I operational range */
2502     eq_reg_td_sqr_err_i = (u32) reg_data;
2503     if ((eq_reg_td_sqr_err_exp > 11) &&
2504         (eq_reg_td_sqr_err_i < 0x00000FFFUL)) {
2505         eq_reg_td_sqr_err_i += 0x00010000UL;
2506     }
2507     status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &reg_data);
2508     if (status < 0)
2509         goto error;
2510     /* Extend SQR_ERR_Q operational range */
2511     eq_reg_td_sqr_err_q = (u32) reg_data;
2512     if ((eq_reg_td_sqr_err_exp > 11) &&
2513         (eq_reg_td_sqr_err_q < 0x00000FFFUL))
2514         eq_reg_td_sqr_err_q += 0x00010000UL;
2515
2516     status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2517             &transmission_params);
2518     if (status < 0)
2519         goto error;
2520
2521     /* Check input data for MER */
2522
2523     /* MER calculation (in 0.1 dB) without math.h */
2524     if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0))
2525         i_mer = 0;
2526     else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) {
2527         /* No error at all, this must be the HW reset value
2528             * Apparently no first measurement yet
2529             * Set MER to 0.0 */
2530         i_mer = 0;
2531     } else {
2532         sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) <<
2533             eq_reg_td_sqr_err_exp;
2534         if ((transmission_params &
2535             OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2536             == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2537             tps_cnt = 17;
2538         else
2539             tps_cnt = 68;
2540
2541         /* IMER = 100 * log10 (x)
2542             where x = (eq_reg_td_tps_pwr_ofs^2 *
2543             eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq
2544
2545             => IMER = a + b -c
2546             where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2)
2547             b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt)
2548             c = 100 * log10 (sqr_err_iq)
2549             */
2550
2551         /* log(x) x = 9bits * 9bits->18 bits  */
2552         a = log10times100(eq_reg_td_tps_pwr_ofs *
2553                     eq_reg_td_tps_pwr_ofs);
2554         /* log(x) x = 16bits * 7bits->23 bits  */
2555         b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt);
2556         /* log(x) x = (16bits + 16bits) << 15 ->32 bits  */
2557         c = log10times100(sqr_err_iq);
2558
2559         i_mer = a + b - c;
2560     }
2561     *p_signal_to_noise = i_mer;
2562
2563 error:
2564     if (status < 0)
2565         pr_err("Error %d on %s\n", status, __func__);
2566     return status;
2567 }
2568
2569 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)
2570 {
2571     dprintk(1, "\n");
2572
2573     *p_signal_to_noise = 0;
2574     switch (state->m_operation_mode) {
2575     case OM_DVBT:
2576         return get_dvbt_signal_to_noise(state, p_signal_to_noise);
2577     case OM_QAM_ITU_A:
2578     case OM_QAM_ITU_C:
2579         return get_qam_signal_to_noise(state, p_signal_to_noise);
2580     default:
2581         break;
2582     }
2583     return 0;
2584 }
2585
2586 #if 0
2587 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2588 {
2589     /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2590     int status = 0;
2591
2592     dprintk(1, "\n");
2593
2594     static s32 QE_SN[] = {
2595         51,     /* QPSK 1/2 */
2596         69,     /* QPSK 2/3 */
2597         79,     /* QPSK 3/4 */
2598         89,     /* QPSK 5/6 */
2599         97,     /* QPSK 7/8 */
2600         108,        /* 16-QAM 1/2 */
2601         131,        /* 16-QAM 2/3 */
2602         146,        /* 16-QAM 3/4 */
2603         156,        /* 16-QAM 5/6 */
2604         160,        /* 16-QAM 7/8 */
2605         165,        /* 64-QAM 1/2 */
2606         187,        /* 64-QAM 2/3 */
2607         202,        /* 64-QAM 3/4 */
2608         216,        /* 64-QAM 5/6 */
2609         225,        /* 64-QAM 7/8 */
2610     };
2611
2612     *p_quality = 0;
2613
2614     do {
2615         s32 signal_to_noise = 0;
2616         u16 constellation = 0;
2617         u16 code_rate = 0;
2618         u32 signal_to_noise_rel;
2619         u32 ber_quality;
2620
2621         status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2622         if (status < 0)
2623             break;
2624         status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2625                 &constellation);
2626         if (status < 0)
2627             break;
2628         constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2629
2630         status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2631                 &code_rate);
2632         if (status < 0)
2633             break;
2634         code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2635
2636         if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2637             code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2638             break;
2639         signal_to_noise_rel = signal_to_noise -
2640             QE_SN[constellation * 5 + code_rate];
2641         ber_quality = 100;
2642
2643         if (signal_to_noise_rel < -70)
2644             *p_quality = 0;
2645         else if (signal_to_noise_rel < 30)
2646             *p_quality = ((signal_to_noise_rel + 70) *
2647                      ber_quality) / 100;
2648         else
2649             *p_quality = ber_quality;
2650     } while (0);
2651     return 0;
2652 };
2653
2654 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2655 {
2656     int status = 0;
2657     *p_quality = 0;
2658
2659     dprintk(1, "\n");
2660
2661     do {
2662         u32 signal_to_noise = 0;
2663         u32 ber_quality = 100;
2664         u32 signal_to_noise_rel = 0;
2665
2666         status = get_qam_signal_to_noise(state, &signal_to_noise);
2667         if (status < 0)
2668             break;
2669
2670         switch (state->props.modulation) {
2671         case QAM_16:
2672             signal_to_noise_rel = signal_to_noise - 200;
2673             break;
2674         case QAM_32:
2675             signal_to_noise_rel = signal_to_noise - 230;
2676             break;  /* Not in NorDig */
2677         case QAM_64:
2678             signal_to_noise_rel = signal_to_noise - 260;
2679             break;
2680         case QAM_128:
2681             signal_to_noise_rel = signal_to_noise - 290;
2682             break;
2683         default:
2684         case QAM_256:
2685             signal_to_noise_rel = signal_to_noise - 320;
2686             break;
2687         }
2688
2689         if (signal_to_noise_rel < -70)
2690             *p_quality = 0;
2691         else if (signal_to_noise_rel < 30)
2692             *p_quality = ((signal_to_noise_rel + 70) *
2693                      ber_quality) / 100;
2694         else
2695             *p_quality = ber_quality;
2696     } while (0);
2697
2698     return status;
2699 }
2700
2701 static int get_quality(struct drxk_state *state, s32 *p_quality)
2702 {
2703     dprintk(1, "\n");
2704
2705     switch (state->m_operation_mode) {
2706     case OM_DVBT:
2707         return get_dvbt_quality(state, p_quality);
2708     case OM_QAM_ITU_A:
2709         return get_dvbc_quality(state, p_quality);
2710     default:
2711         break;
2712     }
2713
2714     return 0;
2715 }
2716 #endif
2717
2718 /* Free data ram in SIO HI */
2719 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2720 #define SIO_HI_RA_RAM_USR_END__A   0x420060
2721
2722 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2723 #define DRXK_HI_ATOMIC_BUF_END   (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2724 #define DRXK_HI_ATOMIC_READ      SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2725 #define DRXK_HI_ATOMIC_WRITE     SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2726
2727 #define DRXDAP_FASI_ADDR2BLOCK(addr)  (((addr) >> 22) & 0x3F)
2728 #define DRXDAP_FASI_ADDR2BANK(addr)   (((addr) >> 16) & 0x3F)
2729 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2730
2731 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
2732 {
2733     int status = -EINVAL;
2734
2735     dprintk(1, "\n");
2736
2737     if (state->m_drxk_state == DRXK_UNINITIALIZED)
2738         return 0;
2739     if (state->m_drxk_state == DRXK_POWERED_DOWN)
2740         goto error;
2741
2742     if (state->no_i2c_bridge)
2743         return 0;
2744
2745     status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2746              SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2747     if (status < 0)
2748         goto error;
2749     if (b_enable_bridge) {
2750         status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2751                  SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2752         if (status < 0)
2753             goto error;
2754     } else {
2755         status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2756                  SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2757         if (status < 0)
2758             goto error;
2759     }
2760
2761     status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);
2762
2763 error:
2764     if (status < 0)
2765         pr_err("Error %d on %s\n", status, __func__);
2766     return status;
2767 }
2768
2769 static int set_pre_saw(struct drxk_state *state,
2770              struct s_cfg_pre_saw *p_pre_saw_cfg)
2771 {
2772     int status = -EINVAL;
2773
2774     dprintk(1, "\n");
2775
2776     if ((p_pre_saw_cfg == NULL)
2777         || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M))
2778         goto error;
2779
2780     status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
2781 error:
2782     if (status < 0)
2783         pr_err("Error %d on %s\n", status, __func__);
2784     return status;
2785 }
2786
2787 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,
2788                u16 rom_offset, u16 nr_of_elements, u32 time_out)
2789 {
2790     u16 bl_status = 0;
2791     u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF);
2792     u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF);
2793     int status;
2794     unsigned long end;
2795
2796     dprintk(1, "\n");
2797
2798     mutex_lock(&state->mutex);
2799     status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2800     if (status < 0)
2801         goto error;
2802     status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2803     if (status < 0)
2804         goto error;
2805     status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2806     if (status < 0)
2807         goto error;
2808     status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
2809     if (status < 0)
2810         goto error;
2811     status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
2812     if (status < 0)
2813         goto error;
2814     status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2815     if (status < 0)
2816         goto error;
2817
2818     end = jiffies + msecs_to_jiffies(time_out);
2819     do {
2820         status = read16(state, SIO_BL_STATUS__A, &bl_status);
2821         if (status < 0)
2822             goto error;
2823     } while ((bl_status == 0x1) && time_is_after_jiffies(end));
2824     if (bl_status == 0x1) {
2825         pr_err("SIO not ready\n");
2826         status = -EINVAL;
2827         goto error2;
2828     }
2829 error:
2830     if (status < 0)
2831         pr_err("Error %d on %s\n", status, __func__);
2832 error2:
2833     mutex_unlock(&state->mutex);
2834     return status;
2835
2836 }
2837
2838 static int adc_sync_measurement(struct drxk_state *state, u16 *count)
2839 {
2840     u16 data = 0;
2841     int status;
2842
2843     dprintk(1, "\n");
2844
2845     /* start measurement */
2846     status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2847     if (status < 0)
2848         goto error;
2849     status = write16(state, IQM_AF_START_LOCK__A, 1);
2850     if (status < 0)
2851         goto error;
2852
2853     *count = 0;
2854     status = read16(state, IQM_AF_PHASE0__A, &data);
2855     if (status < 0)
2856         goto error;
2857     if (data == 127)
2858         *count = *count + 1;
2859     status = read16(state, IQM_AF_PHASE1__A, &data);
2860     if (status < 0)
2861         goto error;
2862     if (data == 127)
2863         *count = *count + 1;
2864     status = read16(state, IQM_AF_PHASE2__A, &data);
2865     if (status < 0)
2866         goto error;
2867     if (data == 127)
2868         *count = *count + 1;
2869
2870 error:
2871     if (status < 0)
2872         pr_err("Error %d on %s\n", status, __func__);
2873     return status;
2874 }
2875
2876 static int adc_synchronization(struct drxk_state *state)
2877 {
2878     u16 count = 0;
2879     int status;
2880
2881     dprintk(1, "\n");
2882
2883     status = adc_sync_measurement(state, &count);
2884     if (status < 0)
2885         goto error;
2886
2887     if (count == 1) {
2888         /* Try sampling on a different edge */
2889         u16 clk_neg = 0;
2890
2891         status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
2892         if (status < 0)
2893             goto error;
2894         if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2895             IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2896             clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2897             clk_neg |=
2898                 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2899         } else {
2900             clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2901             clk_neg |=
2902                 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2903         }
2904         status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
2905         if (status < 0)
2906             goto error;
2907         status = adc_sync_measurement(state, &count);
2908         if (status < 0)
2909             goto error;
2910     }
2911
2912     if (count < 2)
2913         status = -EINVAL;
2914 error:
2915     if (status < 0)
2916         pr_err("Error %d on %s\n", status, __func__);
2917     return status;
2918 }
2919
2920 static int set_frequency_shifter(struct drxk_state *state,
2921                    u16 intermediate_freqk_hz,
2922                    s32 tuner_freq_offset, bool is_dtv)
2923 {
2924     bool select_pos_image = false;
2925     u32 rf_freq_residual = tuner_freq_offset;
2926     u32 fm_frequency_shift = 0;
2927     bool tuner_mirror = !state->m_b_mirror_freq_spect;
2928     u32 adc_freq;
2929     bool adc_flip;
2930     int status;
2931     u32 if_freq_actual;
2932     u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);
2933     u32 frequency_shift;
2934     bool image_to_select;
2935
2936     dprintk(1, "\n");
2937
2938     /*
2939        Program frequency shifter
2940        No need to account for mirroring on RF
2941      */
2942     if (is_dtv) {
2943         if ((state->m_operation_mode == OM_QAM_ITU_A) ||
2944             (state->m_operation_mode == OM_QAM_ITU_C) ||
2945             (state->m_operation_mode == OM_DVBT))
2946             select_pos_image = true;
2947         else
2948             select_pos_image = false;
2949     }
2950     if (tuner_mirror)
2951         /* tuner doesn't mirror */
2952         if_freq_actual = intermediate_freqk_hz +
2953             rf_freq_residual + fm_frequency_shift;
2954     else
2955         /* tuner mirrors */
2956         if_freq_actual = intermediate_freqk_hz -
2957             rf_freq_residual - fm_frequency_shift;
2958     if (if_freq_actual > sampling_frequency / 2) {
2959         /* adc mirrors */
2960         adc_freq = sampling_frequency - if_freq_actual;
2961         adc_flip = true;
2962     } else {
2963         /* adc doesn't mirror */
2964         adc_freq = if_freq_actual;
2965         adc_flip = false;
2966     }
2967
2968     frequency_shift = adc_freq;
2969     image_to_select = state->m_rfmirror ^ tuner_mirror ^
2970         adc_flip ^ select_pos_image;
2971     state->m_iqm_fs_rate_ofs =
2972         Frac28a((frequency_shift), sampling_frequency);
2973
2974     if (image_to_select)
2975         state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;
2976
2977     /* Program frequency shifter with tuner offset compensation */
2978     /* frequency_shift += tuner_freq_offset; TODO */
2979     status = write32(state, IQM_FS_RATE_OFS_LO__A,
2980              state->m_iqm_fs_rate_ofs);
2981     if (status < 0)
2982         pr_err("Error %d on %s\n", status, __func__);
2983     return status;
2984 }
2985
2986 static int init_agc(struct drxk_state *state, bool is_dtv)
2987 {
2988     u16 ingain_tgt = 0;
2989     u16 ingain_tgt_min = 0;
2990     u16 ingain_tgt_max = 0;
2991     u16 clp_cyclen = 0;
2992     u16 clp_sum_min = 0;
2993     u16 clp_dir_to = 0;
2994     u16 sns_sum_min = 0;
2995     u16 sns_sum_max = 0;
2996     u16 clp_sum_max = 0;
2997     u16 sns_dir_to = 0;
2998     u16 ki_innergain_min = 0;
2999     u16 if_iaccu_hi_tgt = 0;
3000     u16 if_iaccu_hi_tgt_min = 0;
3001     u16 if_iaccu_hi_tgt_max = 0;
3002     u16 data = 0;
3003     u16 fast_clp_ctrl_delay = 0;
3004     u16 clp_ctrl_mode = 0;
3005     int status = 0;
3006
3007     dprintk(1, "\n");
3008
3009     /* Common settings */
3010     sns_sum_max = 1023;
3011     if_iaccu_hi_tgt_min = 2047;
3012     clp_cyclen = 500;
3013     clp_sum_max = 1023;
3014
3015     /* AGCInit() not available for DVBT; init done in microcode */
3016     if (!is_qam(state)) {
3017         pr_err("%s: mode %d is not DVB-C\n",
3018                __func__, state->m_operation_mode);
3019         return -EINVAL;
3020     }
3021
3022     /* FIXME: Analog TV AGC require different settings */
3023
3024     /* Standard specific settings */
3025     clp_sum_min = 8;
3026     clp_dir_to = (u16) -9;
3027     clp_ctrl_mode = 0;
3028     sns_sum_min = 8;
3029     sns_dir_to = (u16) -9;
3030     ki_innergain_min = (u16) -1030;
3031     if_iaccu_hi_tgt_max = 0x2380;
3032     if_iaccu_hi_tgt = 0x2380;
3033     ingain_tgt_min = 0x0511;
3034     ingain_tgt = 0x0511;
3035     ingain_tgt_max = 5119;
3036     fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
3037
3038     status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3039              fast_clp_ctrl_delay);
3040     if (status < 0)
3041         goto error;
3042
3043     status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
3044     if (status < 0)
3045         goto error;
3046     status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
3047     if (status < 0)
3048         goto error;
3049     status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
3050     if (status < 0)
3051         goto error;
3052     status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3053     if (status < 0)
3054         goto error;
3055     status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3056              if_iaccu_hi_tgt_min);
3057     if (status < 0)
3058         goto error;
3059     status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3060              if_iaccu_hi_tgt_max);
3061     if (status < 0)
3062         goto error;
3063     status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3064     if (status < 0)
3065         goto error;
3066     status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3067     if (status < 0)
3068         goto error;
3069     status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3070     if (status < 0)
3071         goto error;
3072     status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3073     if (status < 0)
3074         goto error;
3075     status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
3076     if (status < 0)
3077         goto error;
3078     status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
3079     if (status < 0)
3080         goto error;
3081
3082     status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3083              ki_innergain_min);
3084     if (status < 0)
3085         goto error;
3086     status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3087              if_iaccu_hi_tgt);
3088     if (status < 0)
3089         goto error;
3090     status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
3091     if (status < 0)
3092         goto error;
3093
3094     status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3095     if (status < 0)
3096         goto error;
3097     status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3098     if (status < 0)
3099         goto error;
3100     status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3101     if (status < 0)
3102         goto error;
3103
3104     status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3105     if (status < 0)
3106         goto error;
3107     status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
3108     if (status < 0)
3109         goto error;
3110     status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
3111     if (status < 0)
3112         goto error;
3113     status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
3114     if (status < 0)
3115         goto error;
3116     status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
3117     if (status < 0)
3118         goto error;
3119     status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3120     if (status < 0)
3121         goto error;
3122     status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3123     if (status < 0)
3124         goto error;
3125     status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3126     if (status < 0)
3127         goto error;
3128     status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3129     if (status < 0)
3130         goto error;
3131     status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3132     if (status < 0)
3133         goto error;
3134     status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3135     if (status < 0)
3136         goto error;
3137     status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3138     if (status < 0)
3139         goto error;
3140     status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3141     if (status < 0)
3142         goto error;
3143     status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3144     if (status < 0)
3145         goto error;
3146     status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3147     if (status < 0)
3148         goto error;
3149     status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3150     if (status < 0)
3151         goto error;
3152     status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3153     if (status < 0)
3154         goto error;
3155     status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3156     if (status < 0)
3157         goto error;
3158     status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3159     if (status < 0)
3160         goto error;
3161
3162     /* Initialize inner-loop KI gain factors */
3163     status = read16(state, SCU_RAM_AGC_KI__A, &data);
3164     if (status < 0)
3165         goto error;
3166
3167     data = 0x0657;
3168     data &= ~SCU_RAM_AGC_KI_RF__M;
3169     data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3170     data &= ~SCU_RAM_AGC_KI_IF__M;
3171     data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3172
3173     status = write16(state, SCU_RAM_AGC_KI__A, data);
3174 error:
3175     if (status < 0)
3176         pr_err("Error %d on %s\n", status, __func__);
3177     return status;
3178 }
3179
3180 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
3181 {
3182     int status;
3183
3184     dprintk(1, "\n");
3185     if (packet_err == NULL)
3186         status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3187     else
3188         status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3189                 packet_err);
3190     if (status < 0)
3191         pr_err("Error %d on %s\n", status, __func__);
3192     return status;
3193 }
3194
3195 static int dvbt_sc_command(struct drxk_state *state,
3196              u16 cmd, u16 subcmd,
3197              u16 param0, u16 param1, u16 param2,
3198              u16 param3, u16 param4)
3199 {
3200     u16 cur_cmd = 0;
3201     u16 err_code = 0;
3202     u16 retry_cnt = 0;
3203     u16 sc_exec = 0;
3204     int status;
3205
3206     dprintk(1, "\n");
3207     status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3208     if (sc_exec != 1) {
3209         /* SC is not running */
3210         status = -EINVAL;
3211     }
3212     if (status < 0)
3213         goto error;
3214
3215     /* Wait until sc is ready to receive command */
3216     retry_cnt = 0;
3217     do {
3218         usleep_range(1000, 2000);
3219         status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3220         retry_cnt++;
3221     } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3222     if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3223         goto error;
3224
3225     /* Write sub-command */
3226     switch (cmd) {
3227         /* All commands using sub-cmd */
3228     case OFDM_SC_RA_RAM_CMD_PROC_START:
3229     case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3230     case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3231         status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3232         if (status < 0)
3233             goto error;
3234         break;
3235     default:
3236         /* Do nothing */
3237         break;
3238     }
3239
3240     /* Write needed parameters and the command */
3241     status = 0;
3242     switch (cmd) {
3243         /* All commands using 5 parameters */
3244         /* All commands using 4 parameters */
3245         /* All commands using 3 parameters */
3246         /* All commands using 2 parameters */
3247     case OFDM_SC_RA_RAM_CMD_PROC_START:
3248     case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3249     case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3250         status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3251         fallthrough;    /* All commands using 1 parameters */
3252     case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3253     case OFDM_SC_RA_RAM_CMD_USER_IO:
3254         status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3255         fallthrough;    /* All commands using 0 parameters */
3256     case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3257     case OFDM_SC_RA_RAM_CMD_NULL:
3258         /* Write command */
3259         status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3260         break;
3261     default:
3262         /* Unknown command */
3263         status = -EINVAL;
3264     }
3265     if (status < 0)
3266         goto error;
3267
3268     /* Wait until sc is ready processing command */
3269     retry_cnt = 0;
3270     do {
3271         usleep_range(1000, 2000);
3272         status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3273         retry_cnt++;
3274     } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3275     if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3276         goto error;
3277
3278     /* Check for illegal cmd */
3279     status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3280     if (err_code == 0xFFFF) {
3281         /* illegal command */
3282         status = -EINVAL;
3283     }
3284     if (status < 0)
3285         goto error;
3286
3287     /* Retrieve results parameters from SC */
3288     switch (cmd) {
3289         /* All commands yielding 5 results */
3290         /* All commands yielding 4 results */
3291         /* All commands yielding 3 results */
3292         /* All commands yielding 2 results */
3293         /* All commands yielding 1 result */
3294     case OFDM_SC_RA_RAM_CMD_USER_IO:
3295     case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3296         status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3297         break;
3298         /* All commands yielding 0 results */
3299     case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3300     case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3301     case OFDM_SC_RA_RAM_CMD_PROC_START:
3302     case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3303     case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3304     case OFDM_SC_RA_RAM_CMD_NULL:
3305         break;
3306     default:
3307         /* Unknown command */
3308         status = -EINVAL;
3309         break;
3310     }           /* switch (cmd->cmd) */
3311 error:
3312     if (status < 0)
3313         pr_err("Error %d on %s\n", status, __func__);
3314     return status;
3315 }
3316
3317 static int power_up_dvbt(struct drxk_state *state)
3318 {
3319     enum drx_power_mode power_mode = DRX_POWER_UP;
3320     int status;
3321
3322     dprintk(1, "\n");
3323     status = ctrl_power_mode(state, &power_mode);
3324     if (status < 0)
3325         pr_err("Error %d on %s\n", status, __func__);
3326     return status;
3327 }
3328
3329 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
3330 {
3331     int status;
3332
3333     dprintk(1, "\n");
3334     if (*enabled)
3335         status = write16(state, IQM_CF_BYPASSDET__A, 0);
3336     else
3337         status = write16(state, IQM_CF_BYPASSDET__A, 1);
3338     if (status < 0)
3339         pr_err("Error %d on %s\n", status, __func__);
3340     return status;
3341 }
3342
3343 #define DEFAULT_FR_THRES_8K     4000
3344 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
3345 {
3346
3347     int status;
3348
3349     dprintk(1, "\n");
3350     if (*enabled) {
3351         /* write mask to 1 */
3352         status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3353                    DEFAULT_FR_THRES_8K);
3354     } else {
3355         /* write mask to 0 */
3356         status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3357     }
3358     if (status < 0)
3359         pr_err("Error %d on %s\n", status, __func__);
3360
3361     return status;
3362 }
3363
3364 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
3365                 struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
3366 {
3367     u16 data = 0;
3368     int status;
3369
3370     dprintk(1, "\n");
3371     status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3372     if (status < 0)
3373         goto error;
3374
3375     switch (echo_thres->fft_mode) {
3376     case DRX_FFTMODE_2K:
3377         data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3378         data |= ((echo_thres->threshold <<
3379             OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3380             & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3381         break;
3382     case DRX_FFTMODE_8K:
3383         data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3384         data |= ((echo_thres->threshold <<
3385             OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3386             & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3387         break;
3388     default:
3389         return -EINVAL;
3390     }
3391
3392     status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3393 error:
3394     if (status < 0)
3395         pr_err("Error %d on %s\n", status, __func__);
3396     return status;
3397 }
3398
3399 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,
3400                    enum drxk_cfg_dvbt_sqi_speed *speed)
3401 {
3402     int status = -EINVAL;
3403
3404     dprintk(1, "\n");
3405
3406     switch (*speed) {
3407     case DRXK_DVBT_SQI_SPEED_FAST:
3408     case DRXK_DVBT_SQI_SPEED_MEDIUM:
3409     case DRXK_DVBT_SQI_SPEED_SLOW:
3410         break;
3411     default:
3412         goto error;
3413     }
3414     status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3415                (u16) *speed);
3416 error:
3417     if (status < 0)
3418         pr_err("Error %d on %s\n", status, __func__);
3419     return status;
3420 }
3421
3422 /*============================================================================*/
3423
3424 /*
3425 * \brief Activate DVBT specific presets
3426 * \param demod instance of demodulator.
3427 * \return DRXStatus_t.
3428 *
3429 * Called in DVBTSetStandard
3430 *
3431 */
3432 static int dvbt_activate_presets(struct drxk_state *state)
3433 {
3434     int status;
3435     bool setincenable = false;
3436     bool setfrenable = true;
3437
3438     struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K };
3439     struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K };
3440
3441     dprintk(1, "\n");
3442     status = dvbt_ctrl_set_inc_enable(state, &setincenable);
3443     if (status < 0)
3444         goto error;
3445     status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
3446     if (status < 0)
3447         goto error;
3448     status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
3449     if (status < 0)
3450         goto error;
3451     status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3452     if (status < 0)
3453         goto error;
3454     status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3455              state->m_dvbt_if_agc_cfg.ingain_tgt_max);
3456 error:
3457     if (status < 0)
3458         pr_err("Error %d on %s\n", status, __func__);
3459     return status;
3460 }
3461
3462 /*============================================================================*/
3463
3464 /*
3465 * \brief Initialize channelswitch-independent settings for DVBT.
3466 * \param demod instance of demodulator.
3467 * \return DRXStatus_t.
3468 *
3469 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3470 * the DVB-T taps from the drxk_filters.h are used.
3471 */
3472 static int set_dvbt_standard(struct drxk_state *state,
3473                enum operation_mode o_mode)
3474 {
3475     u16 cmd_result = 0;
3476     u16 data = 0;
3477     int status;
3478
3479     dprintk(1, "\n");
3480
3481     power_up_dvbt(state);
3482     /* added antenna switch */
3483     switch_antenna_to_dvbt(state);
3484     /* send OFDM reset command */
3485     status = scu_command(state,
3486                  SCU_RAM_COMMAND_STANDARD_OFDM
3487                  | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
3488                  0, NULL, 1, &cmd_result);
3489     if (status < 0)
3490         goto error;
3491
3492     /* send OFDM setenv command */
3493     status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3494                  | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
3495                  0, NULL, 1, &cmd_result);
3496     if (status < 0)
3497         goto error;
3498
3499     /* reset datapath for OFDM, processors first */
3500     status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3501     if (status < 0)
3502         goto error;
3503     status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3504     if (status < 0)
3505         goto error;
3506     status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3507     if (status < 0)
3508         goto error;
3509
3510     /* IQM setup */
3511     /* synchronize on ofdstate->m_festart */
3512     status = write16(state, IQM_AF_UPD_SEL__A, 1);
3513     if (status < 0)
3514         goto error;
3515     /* window size for clipping ADC detection */
3516     status = write16(state, IQM_AF_CLP_LEN__A, 0);
3517     if (status < 0)
3518         goto error;
3519     /* window size for for sense pre-SAW detection */
3520     status = write16(state, IQM_AF_SNS_LEN__A, 0);
3521     if (status < 0)
3522         goto error;
3523     /* sense threshold for sense pre-SAW detection */
3524     status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3525     if (status < 0)
3526         goto error;
3527     status = set_iqm_af(state, true);
3528     if (status < 0)
3529         goto error;
3530
3531     status = write16(state, IQM_AF_AGC_RF__A, 0);
3532     if (status < 0)
3533         goto error;
3534
3535     /* Impulse noise cruncher setup */
3536     status = write16(state, IQM_AF_INC_LCT__A, 0);  /* crunch in IQM_CF */
3537     if (status < 0)
3538         goto error;
3539     status = write16(state, IQM_CF_DET_LCT__A, 0);  /* detect in IQM_CF */
3540     if (status < 0)
3541         goto error;
3542     status = write16(state, IQM_CF_WND_LEN__A, 3);  /* peak detector window length */
3543     if (status < 0)
3544         goto error;
3545
3546     status = write16(state, IQM_RC_STRETCH__A, 16);
3547     if (status < 0)
3548         goto error;
3549     status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3550     if (status < 0)
3551         goto error;
3552     status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3553     if (status < 0)
3554         goto error;
3555     status = write16(state, IQM_CF_SCALE__A, 1600);
3556     if (status < 0)
3557         goto error;
3558     status = write16(state, IQM_CF_SCALE_SH__A, 0);
3559     if (status < 0)
3560         goto error;
3561
3562     /* virtual clipping threshold for clipping ADC detection */
3563     status = write16(state, IQM_AF_CLP_TH__A, 448);
3564     if (status < 0)
3565         goto error;
3566     status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3567     if (status < 0)
3568         goto error;
3569
3570     status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3571                   DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3572     if (status < 0)
3573         goto error;
3574
3575     status = write16(state, IQM_CF_PKDTH__A, 2);    /* peak detector threshold */
3576     if (status < 0)
3577         goto error;
3578     status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3579     if (status < 0)
3580         goto error;
3581     /* enable power measurement interrupt */
3582     status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3583     if (status < 0)
3584         goto error;
3585     status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3586     if (status < 0)
3587         goto error;
3588
3589     /* IQM will not be reset from here, sync ADC and update/init AGC */
3590     status = adc_synchronization(state);
3591     if (status < 0)
3592         goto error;
3593     status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
3594     if (status < 0)
3595         goto error;
3596
3597     /* Halt SCU to enable safe non-atomic accesses */
3598     status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3599     if (status < 0)
3600         goto error;
3601
3602     status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
3603     if (status < 0)
3604         goto error;
3605     status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
3606     if (status < 0)
3607         goto error;
3608
3609     /* Set Noise Estimation notch width and enable DC fix */
3610     status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3611     if (status < 0)
3612         goto error;
3613     data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3614     status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3615     if (status < 0)
3616         goto error;
3617
3618     /* Activate SCU to enable SCU commands */
3619     status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3620     if (status < 0)
3621         goto error;
3622
3623     if (!state->m_drxk_a3_rom_code) {
3624         /* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay  */
3625         status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3626                  state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
3627         if (status < 0)
3628             goto error;
3629     }
3630
3631     /* OFDM_SC setup */
3632 #ifdef COMPILE_FOR_NONRT
3633     status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3634     if (status < 0)
3635         goto error;
3636     status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3637     if (status < 0)
3638         goto error;
3639 #endif
3640
3641     /* FEC setup */
3642     status = write16(state, FEC_DI_INPUT_CTL__A, 1);    /* OFDM input */
3643     if (status < 0)
3644         goto error;
3645
3646
3647 #ifdef COMPILE_FOR_NONRT
3648     status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3649     if (status < 0)
3650         goto error;
3651 #else
3652     status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3653     if (status < 0)
3654         goto error;
3655 #endif
3656     status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3657     if (status < 0)
3658         goto error;
3659
3660     /* Setup MPEG bus */
3661     status = mpegts_dto_setup(state, OM_DVBT);
3662     if (status < 0)
3663         goto error;
3664     /* Set DVBT Presets */
3665     status = dvbt_activate_presets(state);
3666     if (status < 0)
3667         goto error;
3668
3669 error:
3670     if (status < 0)
3671         pr_err("Error %d on %s\n", status, __func__);
3672     return status;
3673 }
3674
3675 /*============================================================================*/
3676 /*
3677 * \brief start dvbt demodulating for channel.
3678 * \param demod instance of demodulator.
3679 * \return DRXStatus_t.
3680 */
3681 static int dvbt_start(struct drxk_state *state)
3682 {
3683     u16 param1;
3684     int status;
3685     /* drxk_ofdm_sc_cmd_t scCmd; */
3686
3687     dprintk(1, "\n");
3688     /* start correct processes to get in lock */
3689     /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3690     param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3691     status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
3692                  OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1,
3693                  0, 0, 0);
3694     if (status < 0)
3695         goto error;
3696     /* start FEC OC */
3697     status = mpegts_start(state);
3698     if (status < 0)
3699         goto error;
3700     status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3701     if (status < 0)
3702         goto error;
3703 error:
3704     if (status < 0)
3705         pr_err("Error %d on %s\n", status, __func__);
3706     return status;
3707 }
3708
3709
3710 /*============================================================================*/
3711
3712 /*
3713 * \brief Set up dvbt demodulator for channel.
3714 * \param demod instance of demodulator.
3715 * \return DRXStatus_t.
3716 * // original DVBTSetChannel()
3717 */
3718 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3719            s32 tuner_freq_offset)
3720 {
3721     u16 cmd_result = 0;
3722     u16 transmission_params = 0;
3723     u32 iqm_rc_rate_ofs = 0;
3724     u32 bandwidth = 0;
3725     u16 param1;
3726     int status;
3727
3728     dprintk(1, "IF =%d, TFO = %d\n",
3729         intermediate_freqk_hz, tuner_freq_offset);
3730
3731     status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3732                 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
3733                 0, NULL, 1, &cmd_result);
3734     if (status < 0)
3735         goto error;
3736
3737     /* Halt SCU to enable safe non-atomic accesses */
3738     status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3739     if (status < 0)
3740         goto error;
3741
3742     /* Stop processors */
3743     status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3744     if (status < 0)
3745         goto error;
3746     status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3747     if (status < 0)
3748         goto error;
3749
3750     /* Mandatory fix, always stop CP, required to set spl offset back to
3751         hardware default (is set to 0 by ucode during pilot detection */
3752     status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3753     if (status < 0)
3754         goto error;
3755
3756     /*== Write channel settings to device ================================*/
3757
3758     /* mode */
3759     switch (state->props.transmission_mode) {
3760     case TRANSMISSION_MODE_AUTO:
3761     case TRANSMISSION_MODE_8K:
3762     default:
3763         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3764         break;
3765     case TRANSMISSION_MODE_2K:
3766         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3767         break;
3768     }
3769
3770     /* guard */
3771     switch (state->props.guard_interval) {
3772     default:
3773     case GUARD_INTERVAL_AUTO: /* try first guess DRX_GUARD_1DIV4 */
3774     case GUARD_INTERVAL_1_4:
3775         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3776         break;
3777     case GUARD_INTERVAL_1_32:
3778         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3779         break;
3780     case GUARD_INTERVAL_1_16:
3781         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3782         break;
3783     case GUARD_INTERVAL_1_8:
3784         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3785         break;
3786     }
3787
3788     /* hierarchy */
3789     switch (state->props.hierarchy) {
3790     case HIERARCHY_AUTO:
3791     case HIERARCHY_NONE:
3792     default:    /* try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3793     case HIERARCHY_1:
3794         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3795         break;
3796     case HIERARCHY_2:
3797         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3798         break;
3799     case HIERARCHY_4:
3800         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3801         break;
3802     }
3803
3804
3805     /* modulation */
3806     switch (state->props.modulation) {
3807     case QAM_AUTO:
3808     default:    /* try first guess DRX_CONSTELLATION_QAM64 */
3809     case QAM_64:
3810         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3811         break;
3812     case QPSK:
3813         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3814         break;
3815     case QAM_16:
3816         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3817         break;
3818     }
3819 #if 0
3820     /* No hierarchical channels support in BDA */
3821     /* Priority (only for hierarchical channels) */
3822     switch (channel->priority) {
3823     case DRX_PRIORITY_LOW:
3824         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3825         WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3826             OFDM_EC_SB_PRIOR_LO);
3827         break;
3828     case DRX_PRIORITY_HIGH:
3829         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3830         WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3831             OFDM_EC_SB_PRIOR_HI));
3832         break;
3833     case DRX_PRIORITY_UNKNOWN:
3834     default:
3835         status = -EINVAL;
3836         goto error;
3837     }
3838 #else
3839     /* Set Priority high */
3840     transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3841     status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3842     if (status < 0)
3843         goto error;
3844 #endif
3845
3846     /* coderate */
3847     switch (state->props.code_rate_HP) {
3848     case FEC_AUTO:
3849     default:    /* try first guess DRX_CODERATE_2DIV3 */
3850     case FEC_2_3:
3851         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3852         break;
3853     case FEC_1_2:
3854         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3855         break;
3856     case FEC_3_4:
3857         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3858         break;
3859     case FEC_5_6:
3860         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3861         break;
3862     case FEC_7_8:
3863         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3864         break;
3865     }
3866
3867     /*
3868      * SAW filter selection: normally not necessary, but if wanted
3869      * the application can select a SAW filter via the driver by
3870      * using UIOs
3871      */
3872
3873     /* First determine real bandwidth (Hz) */
3874     /* Also set delay for impulse noise cruncher */
3875     /*
3876      * Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is
3877      * changed by SC for fix for some 8K,1/8 guard but is restored by
3878      * InitEC and ResetEC functions
3879      */
3880     switch (state->props.bandwidth_hz) {
3881     case 0:
3882         state->props.bandwidth_hz = 8000000;
3883         fallthrough;
3884     case 8000000:
3885         bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3886         status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3887                  3052);
3888         if (status < 0)
3889             goto error;
3890         /* cochannel protection for PAL 8 MHz */
3891         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3892                  7);
3893         if (status < 0)
3894             goto error;
3895         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3896                  7);
3897         if (status < 0)
3898             goto error;
3899         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3900                  7);
3901         if (status < 0)
3902             goto error;
3903         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3904                  1);
3905         if (status < 0)
3906             goto error;
3907         break;
3908     case 7000000:
3909         bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3910         status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3911                  3491);
3912         if (status < 0)
3913             goto error;
3914         /* cochannel protection for PAL 7 MHz */
3915         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3916                  8);
3917         if (status < 0)
3918             goto error;
3919         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3920                  8);
3921         if (status < 0)
3922             goto error;
3923         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3924                  4);
3925         if (status < 0)
3926             goto error;
3927         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3928                  1);
3929         if (status < 0)
3930             goto error;
3931         break;
3932     case 6000000:
3933         bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3934         status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3935                  4073);
3936         if (status < 0)
3937             goto error;
3938         /* cochannel protection for NTSC 6 MHz */
3939         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3940                  19);
3941         if (status < 0)
3942             goto error;
3943         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3944                  19);
3945         if (status < 0)
3946             goto error;
3947         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3948                  14);
3949         if (status < 0)
3950             goto error;
3951         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3952                  1);
3953         if (status < 0)
3954             goto error;
3955         break;
3956     default:
3957         status = -EINVAL;
3958         goto error;
3959     }
3960
3961     if (iqm_rc_rate_ofs == 0) {
3962         /* Now compute IQM_RC_RATE_OFS
3963             (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
3964             =>
3965             ((SysFreq / BandWidth) * (2^21)) - (2^23)
3966             */
3967         /* (SysFreq / BandWidth) * (2^28)  */
3968         /*
3969          * assert (MAX(sysClk)/MIN(bandwidth) < 16)
3970          *  => assert(MAX(sysClk) < 16*MIN(bandwidth))
3971          *  => assert(109714272 > 48000000) = true
3972          * so Frac 28 can be used
3973          */
3974         iqm_rc_rate_ofs = Frac28a((u32)
3975                     ((state->m_sys_clock_freq *
3976                         1000) / 3), bandwidth);
3977         /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
3978         if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40)
3979             iqm_rc_rate_ofs += 0x80L;
3980         iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7;
3981         /* ((SysFreq / BandWidth) * (2^21)) - (2^23)  */
3982         iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23);
3983     }
3984
3985     iqm_rc_rate_ofs &=
3986         ((((u32) IQM_RC_RATE_OFS_HI__M) <<
3987         IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
3988     status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
3989     if (status < 0)
3990         goto error;
3991
3992     /* Bandwidth setting done */
3993
3994 #if 0
3995     status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
3996     if (status < 0)
3997         goto error;
3998 #endif
3999     status = set_frequency_shifter(state, intermediate_freqk_hz,
4000                        tuner_freq_offset, true);
4001     if (status < 0)
4002         goto error;
4003
4004     /*== start SC, write channel settings to SC ==========================*/
4005
4006     /* Activate SCU to enable SCU commands */
4007     status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4008     if (status < 0)
4009         goto error;
4010
4011     /* Enable SC after setting all other parameters */
4012     status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4013     if (status < 0)
4014         goto error;
4015     status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4016     if (status < 0)
4017         goto error;
4018
4019
4020     status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4021                  | SCU_RAM_COMMAND_CMD_DEMOD_START,
4022                  0, NULL, 1, &cmd_result);
4023     if (status < 0)
4024         goto error;
4025
4026     /* Write SC parameter registers, set all AUTO flags in operation mode */
4027     param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4028             OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4029             OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4030             OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4031             OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4032     status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4033                 0, transmission_params, param1, 0, 0, 0);
4034     if (status < 0)
4035         goto error;
4036
4037     if (!state->m_drxk_a3_rom_code)
4038         status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
4039 error:
4040     if (status < 0)
4041         pr_err("Error %d on %s\n", status, __func__);
4042
4043     return status;
4044 }
4045
4046
4047 /*============================================================================*/
4048
4049 /*
4050 * \brief Retrieve lock status .
4051 * \param demod    Pointer to demodulator instance.
4052 * \param lockStat Pointer to lock status structure.
4053 * \return DRXStatus_t.
4054 *
4055 */
4056 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)
4057 {
4058     int status;
4059     const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4060                     OFDM_SC_RA_RAM_LOCK_FEC__M);
4061     const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4062     const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4063
4064     u16 sc_ra_ram_lock = 0;
4065     u16 sc_comm_exec = 0;
4066
4067     dprintk(1, "\n");
4068
4069     *p_lock_status = NOT_LOCKED;
4070     /* driver 0.9.0 */
4071     /* Check if SC is running */
4072     status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
4073     if (status < 0)
4074         goto end;
4075     if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP)
4076         goto end;
4077
4078     status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
4079     if (status < 0)
4080         goto end;
4081
4082     if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask)
4083         *p_lock_status = MPEG_LOCK;
4084     else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask)
4085         *p_lock_status = FEC_LOCK;
4086     else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask)
4087         *p_lock_status = DEMOD_LOCK;
4088     else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4089         *p_lock_status = NEVER_LOCK;
4090 end:
4091     if (status < 0)
4092         pr_err("Error %d on %s\n", status, __func__);
4093
4094     return status;
4095 }
4096
4097 static int power_up_qam(struct drxk_state *state)
4098 {
4099     enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
4100     int status;
4101
4102     dprintk(1, "\n");
4103     status = ctrl_power_mode(state, &power_mode);
4104     if (status < 0)
4105         pr_err("Error %d on %s\n", status, __func__);
4106
4107     return status;
4108 }
4109
4110
4111 /* Power Down QAM */
4112 static int power_down_qam(struct drxk_state *state)
4113 {
4114     u16 data = 0;
4115     u16 cmd_result;
4116     int status = 0;
4117
4118     dprintk(1, "\n");
4119     status = read16(state, SCU_COMM_EXEC__A, &data);
4120     if (status < 0)
4121         goto error;
4122     if (data == SCU_COMM_EXEC_ACTIVE) {
4123         /*
4124             STOP demodulator
4125             QAM and HW blocks
4126             */
4127         /* stop all comstate->m_exec */
4128         status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4129         if (status < 0)
4130             goto error;
4131         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4132                      | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
4133                      0, NULL, 1, &cmd_result);
4134         if (status < 0)
4135             goto error;
4136     }
4137     /* powerdown AFE                   */
4138     status = set_iqm_af(state, false);
4139
4140 error:
4141     if (status < 0)
4142         pr_err("Error %d on %s\n", status, __func__);
4143
4144     return status;
4145 }
4146
4147 /*============================================================================*/
4148
4149 /*
4150 * \brief Setup of the QAM Measurement intervals for signal quality
4151 * \param demod instance of demod.
4152 * \param modulation current modulation.
4153 * \return DRXStatus_t.
4154 *
4155 *  NOTE:
4156 *  Take into account that for certain settings the errorcounters can overflow.
4157 *  The implementation does not check this.
4158 *
4159 */
4160 static int set_qam_measurement(struct drxk_state *state,
4161                  enum e_drxk_constellation modulation,
4162                  u32 symbol_rate)
4163 {
4164     u32 fec_bits_desired = 0;   /* BER accounting period */
4165     u32 fec_rs_period_total = 0;    /* Total period */
4166     u16 fec_rs_prescale = 0;    /* ReedSolomon Measurement Prescale */
4167     u16 fec_rs_period = 0;  /* Value for corresponding I2C register */
4168     int status = 0;
4169
4170     dprintk(1, "\n");
4171
4172     fec_rs_prescale = 1;
4173     /* fec_bits_desired = symbol_rate [kHz] *
4174         FrameLenght [ms] *
4175         (modulation + 1) *
4176         SyncLoss (== 1) *
4177         ViterbiLoss (==1)
4178         */
4179     switch (modulation) {
4180     case DRX_CONSTELLATION_QAM16:
4181         fec_bits_desired = 4 * symbol_rate;
4182         break;
4183     case DRX_CONSTELLATION_QAM32:
4184         fec_bits_desired = 5 * symbol_rate;
4185         break;
4186     case DRX_CONSTELLATION_QAM64:
4187         fec_bits_desired = 6 * symbol_rate;
4188         break;
4189     case DRX_CONSTELLATION_QAM128:
4190         fec_bits_desired = 7 * symbol_rate;
4191         break;
4192     case DRX_CONSTELLATION_QAM256:
4193         fec_bits_desired = 8 * symbol_rate;
4194         break;
4195     default:
4196         status = -EINVAL;
4197     }
4198     if (status < 0)
4199         goto error;
4200
4201     fec_bits_desired /= 1000;   /* symbol_rate [Hz] -> symbol_rate [kHz] */
4202     fec_bits_desired *= 500;    /* meas. period [ms] */
4203
4204     /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4205     /* fec_rs_period_total = fec_bits_desired / 1632 */
4206     fec_rs_period_total = (fec_bits_desired / 1632UL) + 1;  /* roughly ceil */
4207
4208     /* fec_rs_period_total =  fec_rs_prescale * fec_rs_period  */
4209     fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16);
4210     if (fec_rs_prescale == 0) {
4211         /* Divide by zero (though impossible) */
4212         status = -EINVAL;
4213         if (status < 0)
4214             goto error;
4215     }
4216     fec_rs_period =
4217         ((u16) fec_rs_period_total +
4218         (fec_rs_prescale >> 1)) / fec_rs_prescale;
4219
4220     /* write corresponding registers */
4221     status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4222     if (status < 0)
4223         goto error;
4224     status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4225              fec_rs_prescale);
4226     if (status < 0)
4227         goto error;
4228     status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
4229 error:
4230     if (status < 0)
4231         pr_err("Error %d on %s\n", status, __func__);
4232     return status;
4233 }
4234
4235 static int set_qam16(struct drxk_state *state)
4236 {
4237     int status = 0;
4238
4239     dprintk(1, "\n");
4240     /* QAM Equalizer Setup */
4241     /* Equalizer */
4242     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4243     if (status < 0)
4244         goto error;
4245     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4246     if (status < 0)
4247         goto error;
4248     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4249     if (status < 0)
4250         goto error;
4251     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4252     if (status < 0)
4253         goto error;
4254     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4255     if (status < 0)
4256         goto error;
4257     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4258     if (status < 0)
4259         goto error;
4260     /* Decision Feedback Equalizer */
4261     status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4262     if (status < 0)
4263         goto error;
4264     status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4265     if (status < 0)
4266         goto error;
4267     status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4268     if (status < 0)
4269         goto error;
4270     status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4271     if (status < 0)
4272         goto error;
4273     status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4274     if (status < 0)
4275         goto error;
4276     status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4277     if (status < 0)
4278         goto error;
4279
4280     status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4281     if (status < 0)
4282         goto error;
4283     status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4284     if (status < 0)
4285         goto error;
4286     status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4287     if (status < 0)
4288         goto error;
4289
4290     /* QAM Slicer Settings */
4291     status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4292              DRXK_QAM_SL_SIG_POWER_QAM16);
4293     if (status < 0)
4294         goto error;
4295
4296     /* QAM Loop Controller Coeficients */
4297     status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4298     if (status < 0)
4299         goto error;
4300     status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4301     if (status < 0)
4302         goto error;
4303     status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4304     if (status < 0)
4305         goto error;
4306     status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4307     if (status < 0)
4308         goto error;
4309     status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4310     if (status < 0)
4311         goto error;
4312     status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4313     if (status < 0)
4314         goto error;
4315     status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4316     if (status < 0)
4317         goto error;
4318     status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4319     if (status < 0)
4320         goto error;
4321
4322     status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4323     if (status < 0)
4324         goto error;
4325     status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4326     if (status < 0)
4327         goto error;
4328     status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4329     if (status < 0)
4330         goto error;
4331     status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4332     if (status < 0)
4333         goto error;
4334     status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4335     if (status < 0)
4336         goto error;
4337     status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4338     if (status < 0)
4339         goto error;
4340     status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4341     if (status < 0)
4342         goto error;
4343     status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4344     if (status < 0)
4345         goto error;
4346     status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4347     if (status < 0)
4348         goto error;
4349     status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4350     if (status < 0)
4351         goto error;
4352     status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4353     if (status < 0)
4354         goto error;
4355     status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4356     if (status < 0)
4357         goto error;
4358
4359
4360     /* QAM State Machine (FSM) Thresholds */
4361
4362     status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4363     if (status < 0)
4364         goto error;
4365     status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4366     if (status < 0)
4367         goto error;
4368     status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4369     if (status < 0)
4370         goto error;
4371     status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4372     if (status < 0)
4373         goto error;
4374     status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4375     if (status < 0)
4376         goto error;
4377     status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4378     if (status < 0)
4379         goto error;
4380
4381     status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4382     if (status < 0)
4383         goto error;
4384     status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4385     if (status < 0)
4386         goto error;
4387     status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4388     if (status < 0)
4389         goto error;
4390
4391
4392     /* QAM FSM Tracking Parameters */
4393
4394     status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4395     if (status < 0)
4396         goto error;
4397     status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4398     if (status < 0)
4399         goto error;
4400     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4401     if (status < 0)
4402         goto error;
4403     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4404     if (status < 0)
4405         goto error;
4406     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4407     if (status < 0)
4408         goto error;
4409     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4410     if (status < 0)
4411         goto error;
4412     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4413     if (status < 0)
4414         goto error;
4415
4416 error:
4417     if (status < 0)
4418         pr_err("Error %d on %s\n", status, __func__);
4419     return status;
4420 }
4421
4422 /*============================================================================*/
4423
4424 /*
4425 * \brief QAM32 specific setup
4426 * \param demod instance of demod.
4427 * \return DRXStatus_t.
4428 */
4429 static int set_qam32(struct drxk_state *state)
4430 {
4431     int status = 0;
4432
4433     dprintk(1, "\n");
4434
4435     /* QAM Equalizer Setup */
4436     /* Equalizer */
4437     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4438     if (status < 0)
4439         goto error;
4440     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4441     if (status < 0)
4442         goto error;
4443     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4444     if (status < 0)
4445         goto error;
4446     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4447     if (status < 0)
4448         goto error;
4449     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4450     if (status < 0)
4451         goto error;
4452     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4453     if (status < 0)
4454         goto error;
4455
4456     /* Decision Feedback Equalizer */
4457     status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4458     if (status < 0)
4459         goto error;
4460     status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4461     if (status < 0)
4462         goto error;
4463     status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4464     if (status < 0)
4465         goto error;
4466     status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4467     if (status < 0)
4468         goto error;
4469     status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4470     if (status < 0)
4471         goto error;
4472     status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4473     if (status < 0)
4474         goto error;
4475
4476     status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4477     if (status < 0)
4478         goto error;
4479     status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4480     if (status < 0)
4481         goto error;
4482     status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4483     if (status < 0)
4484         goto error;
4485
4486     /* QAM Slicer Settings */
4487
4488     status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4489              DRXK_QAM_SL_SIG_POWER_QAM32);
4490     if (status < 0)
4491         goto error;
4492
4493
4494     /* QAM Loop Controller Coeficients */
4495
4496     status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4497     if (status < 0)
4498         goto error;
4499     status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4500     if (status < 0)
4501         goto error;
4502     status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4503     if (status < 0)
4504         goto error;
4505     status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4506     if (status < 0)
4507         goto error;
4508     status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4509     if (status < 0)
4510         goto error;
4511     status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4512     if (status < 0)
4513         goto error;
4514     status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4515     if (status < 0)
4516         goto error;
4517     status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4518     if (status < 0)
4519         goto error;
4520
4521     status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4522     if (status < 0)
4523         goto error;
4524     status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4525     if (status < 0)
4526         goto error;
4527     status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4528     if (status < 0)
4529         goto error;
4530     status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4531     if (status < 0)
4532         goto error;
4533     status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4534     if (status < 0)
4535         goto error;
4536     status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4537     if (status < 0)
4538         goto error;
4539     status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4540     if (status < 0)
4541         goto error;
4542     status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4543     if (status < 0)
4544         goto error;
4545     status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4546     if (status < 0)
4547         goto error;
4548     status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4549     if (status < 0)
4550         goto error;
4551     status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4552     if (status < 0)
4553         goto error;
4554     status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4555     if (status < 0)
4556         goto error;
4557
4558
4559     /* QAM State Machine (FSM) Thresholds */
4560
4561     status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4562     if (status < 0)
4563         goto error;
4564     status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4565     if (status < 0)
4566         goto error;
4567     status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4568     if (status < 0)
4569         goto error;
4570     status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4571     if (status < 0)
4572         goto error;
4573     status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4574     if (status < 0)
4575         goto error;
4576     status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4577     if (status < 0)
4578         goto error;
4579
4580     status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4581     if (status < 0)
4582         goto error;
4583     status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4584     if (status < 0)
4585         goto error;
4586     status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4587     if (status < 0)
4588         goto error;
4589
4590
4591     /* QAM FSM Tracking Parameters */
4592
4593     status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4594     if (status < 0)
4595         goto error;
4596     status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4597     if (status < 0)
4598         goto error;
4599     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4600     if (status < 0)
4601         goto error;
4602     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4603     if (status < 0)
4604         goto error;
4605     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4606     if (status < 0)
4607         goto error;
4608     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4609     if (status < 0)
4610         goto error;
4611     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4612 error:
4613     if (status < 0)
4614         pr_err("Error %d on %s\n", status, __func__);
4615     return status;
4616 }
4617
4618 /*============================================================================*/
4619
4620 /*
4621 * \brief QAM64 specific setup
4622 * \param demod instance of demod.
4623 * \return DRXStatus_t.
4624 */
4625 static int set_qam64(struct drxk_state *state)
4626 {
4627     int status = 0;
4628
4629     dprintk(1, "\n");
4630     /* QAM Equalizer Setup */
4631     /* Equalizer */
4632     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4633     if (status < 0)
4634         goto error;
4635     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4636     if (status < 0)
4637         goto error;
4638     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4639     if (status < 0)
4640         goto error;
4641     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4642     if (status < 0)
4643         goto error;
4644     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4645     if (status < 0)
4646         goto error;
4647     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4648     if (status < 0)
4649         goto error;
4650
4651     /* Decision Feedback Equalizer */
4652     status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4653     if (status < 0)
4654         goto error;
4655     status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4656     if (status < 0)
4657         goto error;
4658     status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4659     if (status < 0)
4660         goto error;
4661     status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4662     if (status < 0)
4663         goto error;
4664     status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4665     if (status < 0)
4666         goto error;
4667     status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4668     if (status < 0)
4669         goto error;
4670
4671     status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4672     if (status < 0)
4673         goto error;
4674     status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4675     if (status < 0)
4676         goto error;
4677     status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4678     if (status < 0)
4679         goto error;
4680
4681     /* QAM Slicer Settings */
4682     status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4683              DRXK_QAM_SL_SIG_POWER_QAM64);
4684     if (status < 0)
4685         goto error;
4686
4687
4688     /* QAM Loop Controller Coeficients */
4689
4690     status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4691     if (status < 0)
4692         goto error;
4693     status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4694     if (status < 0)
4695         goto error;
4696     status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4697     if (status < 0)
4698         goto error;
4699     status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4700     if (status < 0)
4701         goto error;
4702     status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4703     if (status < 0)
4704         goto error;
4705     status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4706     if (status < 0)
4707         goto error;
4708     status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4709     if (status < 0)
4710         goto error;
4711     status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4712     if (status < 0)
4713         goto error;
4714
4715     status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4716     if (status < 0)
4717         goto error;
4718     status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4719     if (status < 0)
4720         goto error;
4721     status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4722     if (status < 0)
4723         goto error;
4724     status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4725     if (status < 0)
4726         goto error;
4727     status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4728     if (status < 0)
4729         goto error;
4730     status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4731     if (status < 0)
4732         goto error;
4733     status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4734     if (status < 0)
4735         goto error;
4736     status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4737     if (status < 0)
4738         goto error;
4739     status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4740     if (status < 0)
4741         goto error;
4742     status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4743     if (status < 0)
4744         goto error;
4745     status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4746     if (status < 0)
4747         goto error;
4748     status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4749     if (status < 0)
4750         goto error;
4751
4752
4753     /* QAM State Machine (FSM) Thresholds */
4754
4755     status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4756     if (status < 0)
4757         goto error;
4758     status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4759     if (status < 0)
4760         goto error;
4761     status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4762     if (status < 0)
4763         goto error;
4764     status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4765     if (status < 0)
4766         goto error;
4767     status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4768     if (status < 0)
4769         goto error;
4770     status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4771     if (status < 0)
4772         goto error;
4773
4774     status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4775     if (status < 0)
4776         goto error;
4777     status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4778     if (status < 0)
4779         goto error;
4780     status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4781     if (status < 0)
4782         goto error;
4783
4784
4785     /* QAM FSM Tracking Parameters */
4786
4787     status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4788     if (status < 0)
4789         goto error;
4790     status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4791     if (status < 0)
4792         goto error;
4793     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4794     if (status < 0)
4795         goto error;
4796     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4797     if (status < 0)
4798         goto error;
4799     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4800     if (status < 0)
4801         goto error;
4802     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4803     if (status < 0)
4804         goto error;
4805     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4806 error:
4807     if (status < 0)
4808         pr_err("Error %d on %s\n", status, __func__);
4809
4810     return status;
4811 }
4812
4813 /*============================================================================*/
4814
4815 /*
4816 * \brief QAM128 specific setup
4817 * \param demod: instance of demod.
4818 * \return DRXStatus_t.
4819 */
4820 static int set_qam128(struct drxk_state *state)
4821 {
4822     int status = 0;
4823
4824     dprintk(1, "\n");
4825     /* QAM Equalizer Setup */
4826     /* Equalizer */
4827     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4828     if (status < 0)
4829         goto error;
4830     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4831     if (status < 0)
4832         goto error;
4833     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4834     if (status < 0)
4835         goto error;
4836     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4837     if (status < 0)
4838         goto error;
4839     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4840     if (status < 0)
4841         goto error;
4842     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4843     if (status < 0)
4844         goto error;
4845
4846     /* Decision Feedback Equalizer */
4847     status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4848     if (status < 0)
4849         goto error;
4850     status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4851     if (status < 0)
4852         goto error;
4853     status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4854     if (status < 0)
4855         goto error;
4856     status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4857     if (status < 0)
4858         goto error;
4859     status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4860     if (status < 0)
4861         goto error;
4862     status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4863     if (status < 0)
4864         goto error;
4865
4866     status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4867     if (status < 0)
4868         goto error;
4869     status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4870     if (status < 0)
4871         goto error;
4872     status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4873     if (status < 0)
4874         goto error;
4875
4876
4877     /* QAM Slicer Settings */
4878
4879     status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4880              DRXK_QAM_SL_SIG_POWER_QAM128);
4881     if (status < 0)
4882         goto error;
4883
4884
4885     /* QAM Loop Controller Coeficients */
4886
4887     status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4888     if (status < 0)
4889         goto error;
4890     status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4891     if (status < 0)
4892         goto error;
4893     status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4894     if (status < 0)
4895         goto error;
4896     status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4897     if (status < 0)
4898         goto error;
4899     status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4900     if (status < 0)
4901         goto error;
4902     status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4903     if (status < 0)
4904         goto error;
4905     status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4906     if (status < 0)
4907         goto error;
4908     status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4909     if (status < 0)
4910         goto error;
4911
4912     status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4913     if (status < 0)
4914         goto error;
4915     status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4916     if (status < 0)
4917         goto error;
4918     status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4919     if (status < 0)
4920         goto error;
4921     status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4922     if (status < 0)
4923         goto error;
4924     status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4925     if (status < 0)
4926         goto error;
4927     status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4928     if (status < 0)
4929         goto error;
4930     status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4931     if (status < 0)
4932         goto error;
4933     status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4934     if (status < 0)
4935         goto error;
4936     status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4937     if (status < 0)
4938         goto error;
4939     status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4940     if (status < 0)
4941         goto error;
4942     status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4943     if (status < 0)
4944         goto error;
4945     status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4946     if (status < 0)
4947         goto error;
4948
4949
4950     /* QAM State Machine (FSM) Thresholds */
4951
4952     status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4953     if (status < 0)
4954         goto error;
4955     status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4956     if (status < 0)
4957         goto error;
4958     status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4959     if (status < 0)
4960         goto error;
4961     status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4962     if (status < 0)
4963         goto error;
4964     status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4965     if (status < 0)
4966         goto error;
4967     status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4968     if (status < 0)
4969         goto error;
4970
4971     status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4972     if (status < 0)
4973         goto error;
4974     status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
4975     if (status < 0)
4976         goto error;
4977
4978     status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
4979     if (status < 0)
4980         goto error;
4981
4982     /* QAM FSM Tracking Parameters */
4983
4984     status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
4985     if (status < 0)
4986         goto error;
4987     status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
4988     if (status < 0)
4989         goto error;
4990     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
4991     if (status < 0)
4992         goto error;
4993     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
4994     if (status < 0)
4995         goto error;
4996     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
4997     if (status < 0)
4998         goto error;
4999     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5000     if (status < 0)
5001         goto error;
5002     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5003 error:
5004     if (status < 0)
5005         pr_err("Error %d on %s\n", status, __func__);
5006
5007     return status;
5008 }
5009
5010 /*============================================================================*/
5011
5012 /*
5013 * \brief QAM256 specific setup
5014 * \param demod: instance of demod.
5015 * \return DRXStatus_t.
5016 */
5017 static int set_qam256(struct drxk_state *state)
5018 {
5019     int status = 0;
5020
5021     dprintk(1, "\n");
5022     /* QAM Equalizer Setup */
5023     /* Equalizer */
5024     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5025     if (status < 0)
5026         goto error;
5027     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5028     if (status < 0)
5029         goto error;
5030     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5031     if (status < 0)
5032         goto error;
5033     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5034     if (status < 0)
5035         goto error;
5036     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5037     if (status < 0)
5038         goto error;
5039     status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5040     if (status < 0)
5041         goto error;
5042
5043     /* Decision Feedback Equalizer */
5044     status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5045     if (status < 0)
5046         goto error;
5047     status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5048     if (status < 0)
5049         goto error;
5050     status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5051     if (status < 0)
5052         goto error;
5053     status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5054     if (status < 0)
5055         goto error;
5056     status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5057     if (status < 0)
5058         goto error;
5059     status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5060     if (status < 0)
5061         goto error;
5062
5063     status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5064     if (status < 0)
5065         goto error;
5066     status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5067     if (status < 0)
5068         goto error;
5069     status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5070     if (status < 0)
5071         goto error;
5072
5073     /* QAM Slicer Settings */
5074
5075     status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5076              DRXK_QAM_SL_SIG_POWER_QAM256);
5077     if (status < 0)
5078         goto error;
5079
5080
5081     /* QAM Loop Controller Coeficients */
5082
5083     status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5084     if (status < 0)
5085         goto error;
5086     status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5087     if (status < 0)
5088         goto error;
5089     status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5090     if (status < 0)
5091         goto error;
5092     status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5093     if (status < 0)
5094         goto error;
5095     status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5096     if (status < 0)
5097         goto error;
5098     status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5099     if (status < 0)
5100         goto error;
5101     status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5102     if (status < 0)
5103         goto error;
5104     status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5105     if (status < 0)
5106         goto error;
5107
5108     status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5109     if (status < 0)
5110         goto error;
5111     status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5112     if (status < 0)
5113         goto error;
5114     status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5115     if (status < 0)
5116         goto error;
5117     status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5118     if (status < 0)
5119         goto error;
5120     status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5121     if (status < 0)
5122         goto error;
5123     status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5124     if (status < 0)
5125         goto error;
5126     status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5127     if (status < 0)
5128         goto error;
5129     status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5130     if (status < 0)
5131         goto error;
5132     status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5133     if (status < 0)
5134         goto error;
5135     status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5136     if (status < 0)
5137         goto error;
5138     status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5139     if (status < 0)
5140         goto error;
5141     status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5142     if (status < 0)
5143         goto error;
5144
5145
5146     /* QAM State Machine (FSM) Thresholds */
5147
5148     status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5149     if (status < 0)
5150         goto error;
5151     status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5152     if (status < 0)
5153         goto error;
5154     status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5155     if (status < 0)
5156         goto error;
5157     status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5158     if (status < 0)
5159         goto error;
5160     status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5161     if (status < 0)
5162         goto error;
5163     status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5164     if (status < 0)
5165         goto error;
5166
5167     status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5168     if (status < 0)
5169         goto error;
5170     status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5171     if (status < 0)
5172         goto error;
5173     status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5174     if (status < 0)
5175         goto error;
5176
5177
5178     /* QAM FSM Tracking Parameters */
5179
5180     status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5181     if (status < 0)
5182         goto error;
5183     status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5184     if (status < 0)
5185         goto error;
5186     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5187     if (status < 0)
5188         goto error;
5189     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5190     if (status < 0)
5191         goto error;
5192     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5193     if (status < 0)
5194         goto error;
5195     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5196     if (status < 0)
5197         goto error;
5198     status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5199 error:
5200     if (status < 0)
5201         pr_err("Error %d on %s\n", status, __func__);
5202     return status;
5203 }
5204
5205
5206 /*============================================================================*/
5207 /*
5208 * \brief Reset QAM block.
5209 * \param demod:   instance of demod.
5210 * \param channel: pointer to channel data.
5211 * \return DRXStatus_t.
5212 */
5213 static int qam_reset_qam(struct drxk_state *state)
5214 {
5215     int status;
5216     u16 cmd_result;
5217
5218     dprintk(1, "\n");
5219     /* Stop QAM comstate->m_exec */
5220     status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5221     if (status < 0)
5222         goto error;
5223
5224     status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5225                  | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
5226                  0, NULL, 1, &cmd_result);
5227 error:
5228     if (status < 0)
5229         pr_err("Error %d on %s\n", status, __func__);
5230     return status;
5231 }
5232
5233 /*============================================================================*/
5234
5235 /*
5236 * \brief Set QAM symbolrate.
5237 * \param demod:   instance of demod.
5238 * \param channel: pointer to channel data.
5239 * \return DRXStatus_t.
5240 */
5241 static int qam_set_symbolrate(struct drxk_state *state)
5242 {
5243     u32 adc_frequency = 0;
5244     u32 symb_freq = 0;
5245     u32 iqm_rc_rate = 0;
5246     u16 ratesel = 0;
5247     u32 lc_symb_rate = 0;
5248     int status;
5249
5250     dprintk(1, "\n");
5251     /* Select & calculate correct IQM rate */
5252     adc_frequency = (state->m_sys_clock_freq * 1000) / 3;
5253     ratesel = 0;
5254     if (state->props.symbol_rate <= 1188750)
5255         ratesel = 3;
5256     else if (state->props.symbol_rate <= 2377500)
5257         ratesel = 2;
5258     else if (state->props.symbol_rate <= 4755000)
5259         ratesel = 1;
5260     status = write16(state, IQM_FD_RATESEL__A, ratesel);
5261     if (status < 0)
5262         goto error;
5263
5264     /*
5265         IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5266         */
5267     symb_freq = state->props.symbol_rate * (1 << ratesel);
5268     if (symb_freq == 0) {
5269         /* Divide by zero */
5270         status = -EINVAL;
5271         goto error;
5272     }
5273     iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) +
5274         (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) -
5275         (1 << 23);
5276     status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
5277     if (status < 0)
5278         goto error;
5279     state->m_iqm_rc_rate = iqm_rc_rate;
5280     /*
5281         LcSymbFreq = round (.125 *  symbolrate / adc_freq * (1<<15))
5282         */
5283     symb_freq = state->props.symbol_rate;
5284     if (adc_frequency == 0) {
5285         /* Divide by zero */
5286         status = -EINVAL;
5287         goto error;
5288     }
5289     lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) +
5290         (Frac28a((symb_freq % adc_frequency), adc_frequency) >>
5291         16);
5292     if (lc_symb_rate > 511)
5293         lc_symb_rate = 511;
5294     status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
5295
5296 error:
5297     if (status < 0)
5298         pr_err("Error %d on %s\n", status, __func__);
5299     return status;
5300 }
5301
5302 /*============================================================================*/
5303
5304 /*
5305 * \brief Get QAM lock status.
5306 * \param demod:   instance of demod.
5307 * \param channel: pointer to channel data.
5308 * \return DRXStatus_t.
5309 */
5310
5311 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
5312 {
5313     int status;
5314     u16 result[2] = { 0, 0 };
5315
5316     dprintk(1, "\n");
5317     *p_lock_status = NOT_LOCKED;
5318     status = scu_command(state,
5319             SCU_RAM_COMMAND_STANDARD_QAM |
5320             SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5321             result);
5322     if (status < 0)
5323         pr_err("Error %d on %s\n", status, __func__);
5324
5325     if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5326         /* 0x0000 NOT LOCKED */
5327     } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5328         /* 0x4000 DEMOD LOCKED */
5329         *p_lock_status = DEMOD_LOCK;
5330     } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5331         /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5332         *p_lock_status = MPEG_LOCK;
5333     } else {
5334         /* 0xC000 NEVER LOCKED */
5335         /* (system will never be able to lock to the signal) */
5336         /*
5337          * TODO: check this, intermediate & standard specific lock
5338          * states are not taken into account here
5339          */
5340         *p_lock_status = NEVER_LOCK;
5341     }
5342     return status;
5343 }
5344
5345 #define QAM_MIRROR__M         0x03
5346 #define QAM_MIRROR_NORMAL     0x00
5347 #define QAM_MIRRORED          0x01
5348 #define QAM_MIRROR_AUTO_ON    0x02
5349 #define QAM_LOCKRANGE__M      0x10
5350 #define QAM_LOCKRANGE_NORMAL  0x10
5351
5352 static int qam_demodulator_command(struct drxk_state *state,
5353                  int number_of_parameters)
5354 {
5355     int status;
5356     u16 cmd_result;
5357     u16 set_param_parameters[4] = { 0, 0, 0, 0 };
5358
5359     set_param_parameters[0] = state->m_constellation;   /* modulation     */
5360     set_param_parameters[1] = DRXK_QAM_I12_J17; /* interleave mode   */
5361
5362     if (number_of_parameters == 2) {
5363         u16 set_env_parameters[1] = { 0 };
5364
5365         if (state->m_operation_mode == OM_QAM_ITU_C)
5366             set_env_parameters[0] = QAM_TOP_ANNEX_C;
5367         else
5368             set_env_parameters[0] = QAM_TOP_ANNEX_A;
5369
5370         status = scu_command(state,
5371                      SCU_RAM_COMMAND_STANDARD_QAM
5372                      | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5373                      1, set_env_parameters, 1, &cmd_result);
5374         if (status < 0)
5375             goto error;
5376
5377         status = scu_command(state,
5378                      SCU_RAM_COMMAND_STANDARD_QAM
5379                      | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5380                      number_of_parameters, set_param_parameters,
5381                      1, &cmd_result);
5382     } else if (number_of_parameters == 4) {
5383         if (state->m_operation_mode == OM_QAM_ITU_C)
5384             set_param_parameters[2] = QAM_TOP_ANNEX_C;
5385         else
5386             set_param_parameters[2] = QAM_TOP_ANNEX_A;
5387
5388         set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON);
5389         /* Env parameters */
5390         /* check for LOCKRANGE Extended */
5391         /* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */
5392
5393         status = scu_command(state,
5394                      SCU_RAM_COMMAND_STANDARD_QAM
5395                      | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5396                      number_of_parameters, set_param_parameters,
5397                      1, &cmd_result);
5398     } else {
5399         pr_warn("Unknown QAM demodulator parameter count %d\n",
5400             number_of_parameters);
5401         status = -EINVAL;
5402     }
5403
5404 error:
5405     if (status < 0)
5406         pr_warn("Warning %d on %s\n", status, __func__);
5407     return status;
5408 }
5409
5410 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5411           s32 tuner_freq_offset)
5412 {
5413     int status;
5414     u16 cmd_result;
5415     int qam_demod_param_count = state->qam_demod_parameter_count;
5416
5417     dprintk(1, "\n");
5418     /*
5419      * STEP 1: reset demodulator
5420      *  resets FEC DI and FEC RS
5421      *  resets QAM block
5422      *  resets SCU variables
5423      */
5424     status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5425     if (status < 0)
5426         goto error;
5427     status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5428     if (status < 0)
5429         goto error;
5430     status = qam_reset_qam(state);
5431     if (status < 0)
5432         goto error;
5433
5434     /*
5435      * STEP 2: configure demodulator
5436      *  -set params; resets IQM,QAM,FEC HW; initializes some
5437      *       SCU variables
5438      */
5439     status = qam_set_symbolrate(state);
5440     if (status < 0)
5441         goto error;
5442
5443     /* Set params */
5444     switch (state->props.modulation) {
5445     case QAM_256:
5446         state->m_constellation = DRX_CONSTELLATION_QAM256;
5447         break;
5448     case QAM_AUTO:
5449     case QAM_64:
5450         state->m_constellation = DRX_CONSTELLATION_QAM64;
5451         break;
5452     case QAM_16:
5453         state->m_constellation = DRX_CONSTELLATION_QAM16;
5454         break;
5455     case QAM_32:
5456         state->m_constellation = DRX_CONSTELLATION_QAM32;
5457         break;
5458     case QAM_128:
5459         state->m_constellation = DRX_CONSTELLATION_QAM128;
5460         break;
5461     default:
5462         status = -EINVAL;
5463         break;
5464     }
5465     if (status < 0)
5466         goto error;
5467
5468     /* Use the 4-parameter if it's requested or we're probing for
5469      * the correct command. */
5470     if (state->qam_demod_parameter_count == 4
5471         || !state->qam_demod_parameter_count) {
5472         qam_demod_param_count = 4;
5473         status = qam_demodulator_command(state, qam_demod_param_count);
5474     }
5475
5476     /* Use the 2-parameter command if it was requested or if we're
5477      * probing for the correct command and the 4-parameter command
5478      * failed. */
5479     if (state->qam_demod_parameter_count == 2
5480         || (!state->qam_demod_parameter_count && status < 0)) {
5481         qam_demod_param_count = 2;
5482         status = qam_demodulator_command(state, qam_demod_param_count);
5483     }
5484
5485     if (status < 0) {
5486         dprintk(1, "Could not set demodulator parameters.\n");
5487         dprintk(1,
5488             "Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n",
5489             state->qam_demod_parameter_count,
5490             state->microcode_name);
5491         goto error;
5492     } else if (!state->qam_demod_parameter_count) {
5493         dprintk(1,
5494             "Auto-probing the QAM command parameters was successful - using %d parameters.\n",
5495             qam_demod_param_count);
5496
5497         /*
5498          * One of our commands was successful. We don't need to
5499          * auto-probe anymore, now that we got the correct command.
5500          */
5501         state->qam_demod_parameter_count = qam_demod_param_count;
5502     }
5503
5504     /*
5505      * STEP 3: enable the system in a mode where the ADC provides valid
5506      * signal setup modulation independent registers
5507      */
5508 #if 0
5509     status = set_frequency(channel, tuner_freq_offset));
5510     if (status < 0)
5511         goto error;
5512 #endif
5513     status = set_frequency_shifter(state, intermediate_freqk_hz,
5514                        tuner_freq_offset, true);
5515     if (status < 0)
5516         goto error;
5517
5518     /* Setup BER measurement */
5519     status = set_qam_measurement(state, state->m_constellation,
5520                      state->props.symbol_rate);
5521     if (status < 0)
5522         goto error;
5523
5524     /* Reset default values */
5525     status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5526     if (status < 0)
5527         goto error;
5528     status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5529     if (status < 0)
5530         goto error;
5531
5532     /* Reset default LC values */
5533     status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5534     if (status < 0)
5535         goto error;
5536     status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5537     if (status < 0)
5538         goto error;
5539     status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5540     if (status < 0)
5541         goto error;
5542     status = write16(state, QAM_LC_MODE__A, 7);
5543     if (status < 0)
5544         goto error;
5545
5546     status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5547     if (status < 0)
5548         goto error;
5549     status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5550     if (status < 0)
5551         goto error;
5552     status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5553     if (status < 0)
5554         goto error;
5555     status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5556     if (status < 0)
5557         goto error;
5558     status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5559     if (status < 0)
5560         goto error;
5561     status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5562     if (status < 0)
5563         goto error;
5564     status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5565     if (status < 0)
5566         goto error;
5567     status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5568     if (status < 0)
5569         goto error;
5570     status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5571     if (status < 0)
5572         goto error;
5573     status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5574     if (status < 0)
5575         goto error;
5576     status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5577     if (status < 0)
5578         goto error;
5579     status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5580     if (status < 0)
5581         goto error;
5582     status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5583     if (status < 0)
5584         goto error;
5585     status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5586     if (status < 0)
5587         goto error;
5588     status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5589     if (status < 0)
5590         goto error;
5591
5592     /* Mirroring, QAM-block starting point not inverted */
5593     status = write16(state, QAM_SY_SP_INV__A,
5594              QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5595     if (status < 0)
5596         goto error;
5597
5598     /* Halt SCU to enable safe non-atomic accesses */
5599     status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5600     if (status < 0)
5601         goto error;
5602
5603     /* STEP 4: modulation specific setup */
5604     switch (state->props.modulation) {
5605     case QAM_16:
5606         status = set_qam16(state);
5607         break;
5608     case QAM_32:
5609         status = set_qam32(state);
5610         break;
5611     case QAM_AUTO:
5612     case QAM_64:
5613         status = set_qam64(state);
5614         break;
5615     case QAM_128:
5616         status = set_qam128(state);
5617         break;
5618     case QAM_256:
5619         status = set_qam256(state);
5620         break;
5621     default:
5622         status = -EINVAL;
5623         break;
5624     }
5625     if (status < 0)
5626         goto error;
5627
5628     /* Activate SCU to enable SCU commands */
5629     status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5630     if (status < 0)
5631         goto error;
5632
5633     /* Re-configure MPEG output, requires knowledge of channel bitrate */
5634     /* extAttr->currentChannel.modulation = channel->modulation; */
5635     /* extAttr->currentChannel.symbolrate    = channel->symbolrate; */
5636     status = mpegts_dto_setup(state, state->m_operation_mode);
5637     if (status < 0)
5638         goto error;
5639
5640     /* start processes */
5641     status = mpegts_start(state);
5642     if (status < 0)
5643         goto error;
5644     status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5645     if (status < 0)
5646         goto error;
5647     status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5648     if (status < 0)
5649         goto error;
5650     status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5651     if (status < 0)
5652         goto error;
5653
5654     /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5655     status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5656                  | SCU_RAM_COMMAND_CMD_DEMOD_START,
5657                  0, NULL, 1, &cmd_result);
5658     if (status < 0)
5659         goto error;
5660
5661     /* update global DRXK data container */
5662 /*?     extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5663
5664 error:
5665     if (status < 0)
5666         pr_err("Error %d on %s\n", status, __func__);
5667     return status;
5668 }
5669
5670 static int set_qam_standard(struct drxk_state *state,
5671               enum operation_mode o_mode)
5672 {
5673     int status;
5674 #ifdef DRXK_QAM_TAPS
5675 #define DRXK_QAMA_TAPS_SELECT
5676 #include "drxk_filters.h"
5677 #undef DRXK_QAMA_TAPS_SELECT
5678 #endif
5679
5680     dprintk(1, "\n");
5681
5682     /* added antenna switch */
5683     switch_antenna_to_qam(state);
5684
5685     /* Ensure correct power-up mode */
5686     status = power_up_qam(state);
5687     if (status < 0)
5688         goto error;
5689     /* Reset QAM block */
5690     status = qam_reset_qam(state);
5691     if (status < 0)
5692         goto error;
5693
5694     /* Setup IQM */
5695
5696     status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5697     if (status < 0)
5698         goto error;
5699     status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5700     if (status < 0)
5701         goto error;
5702
5703     /* Upload IQM Channel Filter settings by
5704         boot loader from ROM table */
5705     switch (o_mode) {
5706     case OM_QAM_ITU_A:
5707         status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5708                       DRXK_BLCC_NR_ELEMENTS_TAPS,
5709             DRXK_BLC_TIMEOUT);
5710         break;
5711     case OM_QAM_ITU_C:
5712         status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5713                        DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5714                        DRXK_BLDC_NR_ELEMENTS_TAPS,
5715                        DRXK_BLC_TIMEOUT);
5716         if (status < 0)
5717             goto error;
5718         status = bl_direct_cmd(state,
5719                        IQM_CF_TAP_IM0__A,
5720                        DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5721                        DRXK_BLDC_NR_ELEMENTS_TAPS,
5722                        DRXK_BLC_TIMEOUT);
5723         break;
5724     default:
5725         status = -EINVAL;
5726     }
5727     if (status < 0)
5728         goto error;
5729
5730     status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
5731     if (status < 0)
5732         goto error;
5733     status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5734     if (status < 0)
5735         goto error;
5736     status = write16(state, IQM_CF_MIDTAP__A,
5737              ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5738     if (status < 0)
5739         goto error;
5740
5741     status = write16(state, IQM_RC_STRETCH__A, 21);
5742     if (status < 0)
5743         goto error;
5744     status = write16(state, IQM_AF_CLP_LEN__A, 0);
5745     if (status < 0)
5746         goto error;
5747     status = write16(state, IQM_AF_CLP_TH__A, 448);
5748     if (status < 0)
5749         goto error;
5750     status = write16(state, IQM_AF_SNS_LEN__A, 0);
5751     if (status < 0)
5752         goto error;
5753     status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5754     if (status < 0)
5755         goto error;
5756
5757     status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5758     if (status < 0)
5759         goto error;
5760     status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5761     if (status < 0)
5762         goto error;
5763     status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5764     if (status < 0)
5765         goto error;
5766     status = write16(state, IQM_AF_UPD_SEL__A, 0);
5767     if (status < 0)
5768         goto error;
5769
5770     /* IQM Impulse Noise Processing Unit */
5771     status = write16(state, IQM_CF_CLP_VAL__A, 500);
5772     if (status < 0)
5773         goto error;
5774     status = write16(state, IQM_CF_DATATH__A, 1000);
5775     if (status < 0)
5776         goto error;
5777     status = write16(state, IQM_CF_BYPASSDET__A, 1);
5778     if (status < 0)
5779         goto error;
5780     status = write16(state, IQM_CF_DET_LCT__A, 0);
5781     if (status < 0)
5782         goto error;
5783     status = write16(state, IQM_CF_WND_LEN__A, 1);
5784     if (status < 0)
5785         goto error;
5786     status = write16(state, IQM_CF_PKDTH__A, 1);
5787     if (status < 0)
5788         goto error;
5789     status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5790     if (status < 0)
5791         goto error;
5792
5793     /* turn on IQMAF. Must be done before setAgc**() */
5794     status = set_iqm_af(state, true);
5795     if (status < 0)
5796         goto error;
5797     status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5798     if (status < 0)
5799         goto error;
5800
5801     /* IQM will not be reset from here, sync ADC and update/init AGC */
5802     status = adc_synchronization(state);
5803     if (status < 0)
5804         goto error;
5805
5806     /* Set the FSM step period */
5807     status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5808     if (status < 0)
5809         goto error;
5810
5811     /* Halt SCU to enable safe non-atomic accesses */
5812     status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5813     if (status < 0)
5814         goto error;
5815
5816     /* No more resets of the IQM, current standard correctly set =>
5817         now AGCs can be configured. */
5818
5819     status = init_agc(state, true);
5820     if (status < 0)
5821         goto error;
5822     status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
5823     if (status < 0)
5824         goto error;
5825
5826     /* Configure AGC's */
5827     status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
5828     if (status < 0)
5829         goto error;
5830     status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
5831     if (status < 0)
5832         goto error;
5833
5834     /* Activate SCU to enable SCU commands */
5835     status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5836 error:
5837     if (status < 0)
5838         pr_err("Error %d on %s\n", status, __func__);
5839     return status;
5840 }
5841
5842 static int write_gpio(struct drxk_state *state)
5843 {
5844     int status;
5845     u16 value = 0;
5846
5847     dprintk(1, "\n");
5848     /* stop lock indicator process */
5849     status = write16(state, SCU_RAM_GPIO__A,
5850              SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5851     if (status < 0)
5852         goto error;
5853
5854     /*  Write magic word to enable pdr reg write               */
5855     status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5856     if (status < 0)
5857         goto error;
5858
5859     if (state->m_has_sawsw) {
5860         if (state->uio_mask & 0x0001) { /* UIO-1 */
5861             /* write to io pad configuration register - output mode */
5862             status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5863                      state->m_gpio_cfg);
5864             if (status < 0)
5865                 goto error;
5866
5867             /* use corresponding bit in io data output registar */
5868             status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5869             if (status < 0)
5870                 goto error;
5871             if ((state->m_gpio & 0x0001) == 0)
5872                 value &= 0x7FFF;    /* write zero to 15th bit - 1st UIO */
5873             else
5874                 value |= 0x8000;    /* write one to 15th bit - 1st UIO */
5875             /* write back to io data output register */
5876             status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5877             if (status < 0)
5878                 goto error;
5879         }
5880         if (state->uio_mask & 0x0002) { /* UIO-2 */
5881             /* write to io pad configuration register - output mode */
5882             status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5883                      state->m_gpio_cfg);
5884             if (status < 0)
5885                 goto error;
5886
5887             /* use corresponding bit in io data output registar */
5888             status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5889             if (status < 0)
5890                 goto error;
5891             if ((state->m_gpio & 0x0002) == 0)
5892                 value &= 0xBFFF;    /* write zero to 14th bit - 2st UIO */
5893             else
5894                 value |= 0x4000;    /* write one to 14th bit - 2st UIO */
5895             /* write back to io data output register */
5896             status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5897             if (status < 0)
5898                 goto error;
5899         }
5900         if (state->uio_mask & 0x0004) { /* UIO-3 */
5901             /* write to io pad configuration register - output mode */
5902             status = write16(state, SIO_PDR_GPIO_CFG__A,
5903                      state->m_gpio_cfg);
5904             if (status < 0)
5905                 goto error;
5906
5907             /* use corresponding bit in io data output registar */
5908             status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5909             if (status < 0)
5910                 goto error;
5911             if ((state->m_gpio & 0x0004) == 0)
5912                 value &= 0xFFFB;            /* write zero to 2nd bit - 3rd UIO */
5913             else
5914                 value |= 0x0004;            /* write one to 2nd bit - 3rd UIO */
5915             /* write back to io data output register */
5916             status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5917             if (status < 0)
5918                 goto error;
5919         }
5920     }
5921     /*  Write magic word to disable pdr reg write               */
5922     status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5923 error:
5924     if (status < 0)
5925         pr_err("Error %d on %s\n", status, __func__);
5926     return status;
5927 }
5928
5929 static int switch_antenna_to_qam(struct drxk_state *state)
5930 {
5931     int status = 0;
5932     bool gpio_state;
5933
5934     dprintk(1, "\n");
5935
5936     if (!state->antenna_gpio)
5937         return 0;
5938
5939     gpio_state = state->m_gpio & state->antenna_gpio;
5940
5941     if (state->antenna_dvbt ^ gpio_state) {
5942         /* Antenna is on DVB-T mode. Switch */
5943         if (state->antenna_dvbt)
5944             state->m_gpio &= ~state->antenna_gpio;
5945         else
5946             state->m_gpio |= state->antenna_gpio;
5947         status = write_gpio(state);
5948     }
5949     if (status < 0)
5950         pr_err("Error %d on %s\n", status, __func__);
5951     return status;
5952 }
5953
5954 static int switch_antenna_to_dvbt(struct drxk_state *state)
5955 {
5956     int status = 0;
5957     bool gpio_state;
5958
5959     dprintk(1, "\n");
5960
5961     if (!state->antenna_gpio)
5962         return 0;
5963
5964     gpio_state = state->m_gpio & state->antenna_gpio;
5965
5966     if (!(state->antenna_dvbt ^ gpio_state)) {
5967         /* Antenna is on DVB-C mode. Switch */
5968         if (state->antenna_dvbt)
5969             state->m_gpio |= state->antenna_gpio;
5970         else
5971             state->m_gpio &= ~state->antenna_gpio;
5972         status = write_gpio(state);
5973     }
5974     if (status < 0)
5975         pr_err("Error %d on %s\n", status, __func__);
5976     return status;
5977 }
5978
5979
5980 static int power_down_device(struct drxk_state *state)
5981 {
5982     /* Power down to requested mode */
5983     /* Backup some register settings */
5984     /* Set pins with possible pull-ups connected to them in input mode */
5985     /* Analog power down */
5986     /* ADC power down */
5987     /* Power down device */
5988     int status;
5989
5990     dprintk(1, "\n");
5991     if (state->m_b_p_down_open_bridge) {
5992         /* Open I2C bridge before power down of DRXK */
5993         status = ConfigureI2CBridge(state, true);
5994         if (status < 0)
5995             goto error;
5996     }
5997     /* driver 0.9.0 */
5998     status = dvbt_enable_ofdm_token_ring(state, false);
5999     if (status < 0)
6000         goto error;
6001
6002     status = write16(state, SIO_CC_PWD_MODE__A,
6003              SIO_CC_PWD_MODE_LEVEL_CLOCK);
6004     if (status < 0)
6005         goto error;
6006     status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6007     if (status < 0)
6008         goto error;
6009     state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
6010     status = hi_cfg_command(state);
6011 error:
6012     if (status < 0)
6013         pr_err("Error %d on %s\n", status, __func__);
6014
6015     return status;
6016 }
6017
6018 static int init_drxk(struct drxk_state *state)
6019 {
6020     int status = 0, n = 0;
6021     enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
6022     u16 driver_version;
6023
6024     dprintk(1, "\n");
6025     if (state->m_drxk_state == DRXK_UNINITIALIZED) {
6026         drxk_i2c_lock(state);
6027         status = power_up_device(state);
6028         if (status < 0)
6029             goto error;
6030         status = drxx_open(state);
6031         if (status < 0)
6032             goto error;
6033         /* Soft reset of OFDM-, sys- and osc-clockdomain */
6034         status = write16(state, SIO_CC_SOFT_RST__A,
6035                  SIO_CC_SOFT_RST_OFDM__M
6036                  | SIO_CC_SOFT_RST_SYS__M
6037                  | SIO_CC_SOFT_RST_OSC__M);
6038         if (status < 0)
6039             goto error;
6040         status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6041         if (status < 0)
6042             goto error;
6043         /*
6044          * TODO is this needed? If yes, how much delay in
6045          * worst case scenario
6046          */
6047         usleep_range(1000, 2000);
6048         state->m_drxk_a3_patch_code = true;
6049         status = get_device_capabilities(state);
6050         if (status < 0)
6051             goto error;
6052
6053         /* Bridge delay, uses oscilator clock */
6054         /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6055         /* SDA brdige delay */
6056         state->m_hi_cfg_bridge_delay =
6057             (u16) ((state->m_osc_clock_freq / 1000) *
6058                 HI_I2C_BRIDGE_DELAY) / 1000;
6059         /* Clipping */
6060         if (state->m_hi_cfg_bridge_delay >
6061             SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6062             state->m_hi_cfg_bridge_delay =
6063                 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6064         }
6065         /* SCL bridge delay, same as SDA for now */
6066         state->m_hi_cfg_bridge_delay +=
6067             state->m_hi_cfg_bridge_delay <<
6068             SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6069
6070         status = init_hi(state);
6071         if (status < 0)
6072             goto error;
6073         /* disable various processes */
6074 #if NOA1ROM
6075         if (!(state->m_DRXK_A1_ROM_CODE)
6076             && !(state->m_DRXK_A2_ROM_CODE))
6077 #endif
6078         {
6079             status = write16(state, SCU_RAM_GPIO__A,
6080                      SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6081             if (status < 0)
6082                 goto error;
6083         }
6084
6085         /* disable MPEG port */
6086         status = mpegts_disable(state);
6087         if (status < 0)
6088             goto error;
6089
6090         /* Stop AUD and SCU */
6091         status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6092         if (status < 0)
6093             goto error;
6094         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6095         if (status < 0)
6096             goto error;
6097
6098         /* enable token-ring bus through OFDM block for possible ucode upload */
6099         status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6100                  SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6101         if (status < 0)
6102             goto error;
6103
6104         /* include boot loader section */
6105         status = write16(state, SIO_BL_COMM_EXEC__A,
6106                  SIO_BL_COMM_EXEC_ACTIVE);
6107         if (status < 0)
6108             goto error;
6109         status = bl_chain_cmd(state, 0, 6, 100);
6110         if (status < 0)
6111             goto error;
6112
6113         if (state->fw) {
6114             status = download_microcode(state, state->fw->data,
6115                            state->fw->size);
6116             if (status < 0)
6117                 goto error;
6118         }
6119
6120         /* disable token-ring bus through OFDM block for possible ucode upload */
6121         status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6122                  SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6123         if (status < 0)
6124             goto error;
6125
6126         /* Run SCU for a little while to initialize microcode version numbers */
6127         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6128         if (status < 0)
6129             goto error;
6130         status = drxx_open(state);
6131         if (status < 0)
6132             goto error;
6133         /* added for test */
6134         msleep(30);
6135
6136         power_mode = DRXK_POWER_DOWN_OFDM;
6137         status = ctrl_power_mode(state, &power_mode);
6138         if (status < 0)
6139             goto error;
6140
6141         /* Stamp driver version number in SCU data RAM in BCD code
6142             Done to enable field application engineers to retrieve drxdriver version
6143             via I2C from SCU RAM.
6144             Not using SCU command interface for SCU register access since no
6145             microcode may be present.
6146             */
6147         driver_version =
6148             (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6149             (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6150             ((DRXK_VERSION_MAJOR % 10) << 4) +
6151             (DRXK_VERSION_MINOR % 10);
6152         status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6153                  driver_version);
6154         if (status < 0)
6155             goto error;
6156         driver_version =
6157             (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6158             (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6159             (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6160             (DRXK_VERSION_PATCH % 10);
6161         status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6162                  driver_version);
6163         if (status < 0)
6164             goto error;
6165
6166         pr_info("DRXK driver version %d.%d.%d\n",
6167             DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6168             DRXK_VERSION_PATCH);
6169
6170         /*
6171          * Dirty fix of default values for ROM/PATCH microcode
6172          * Dirty because this fix makes it impossible to setup
6173          * suitable values before calling DRX_Open. This solution
6174          * requires changes to RF AGC speed to be done via the CTRL
6175          * function after calling DRX_Open
6176          */
6177
6178         /* m_dvbt_rf_agc_cfg.speed = 3; */
6179
6180         /* Reset driver debug flags to 0 */
6181         status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6182         if (status < 0)
6183             goto error;
6184         /* driver 0.9.0 */
6185         /* Setup FEC OC:
6186             NOTE: No more full FEC resets allowed afterwards!! */
6187         status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6188         if (status < 0)
6189             goto error;
6190         /* MPEGTS functions are still the same */
6191         status = mpegts_dto_init(state);
6192         if (status < 0)
6193             goto error;
6194         status = mpegts_stop(state);
6195         if (status < 0)
6196             goto error;
6197         status = mpegts_configure_polarity(state);
6198         if (status < 0)
6199             goto error;
6200         status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
6201         if (status < 0)
6202             goto error;
6203         /* added: configure GPIO */
6204         status = write_gpio(state);
6205         if (status < 0)
6206             goto error;
6207
6208         state->m_drxk_state = DRXK_STOPPED;
6209
6210         if (state->m_b_power_down) {
6211             status = power_down_device(state);
6212             if (status < 0)
6213                 goto error;
6214             state->m_drxk_state = DRXK_POWERED_DOWN;
6215         } else
6216             state->m_drxk_state = DRXK_STOPPED;
6217
6218         /* Initialize the supported delivery systems */
6219         n = 0;
6220         if (state->m_has_dvbc) {
6221             state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6222             state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6223             strlcat(state->frontend.ops.info.name, " DVB-C",
6224                 sizeof(state->frontend.ops.info.name));
6225         }
6226         if (state->m_has_dvbt) {
6227             state->frontend.ops.delsys[n++] = SYS_DVBT;
6228             strlcat(state->frontend.ops.info.name, " DVB-T",
6229                 sizeof(state->frontend.ops.info.name));
6230         }
6231         drxk_i2c_unlock(state);
6232     }
6233 error:
6234     if (status < 0) {
6235         state->m_drxk_state = DRXK_NO_DEV;
6236         drxk_i2c_unlock(state);
6237         pr_err("Error %d on %s\n", status, __func__);
6238     }
6239
6240     return status;
6241 }
6242
6243 static void load_firmware_cb(const struct firmware *fw,
6244                  void *context)
6245 {
6246     struct drxk_state *state = context;
6247
6248     dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
6249     if (!fw) {
6250         pr_err("Could not load firmware file %s.\n",
6251             state->microcode_name);
6252         pr_info("Copy %s to your hotplug directory!\n",
6253             state->microcode_name);
6254         state->microcode_name = NULL;
6255
6256         /*
6257          * As firmware is now load asynchronous, it is not possible
6258          * anymore to fail at frontend attach. We might silently
6259          * return here, and hope that the driver won't crash.
6260          * We might also change all DVB callbacks to return -ENODEV
6261          * if the device is not initialized.
6262          * As the DRX-K devices have their own internal firmware,
6263          * let's just hope that it will match a firmware revision
6264          * compatible with this driver and proceed.
6265          */
6266     }
6267     state->fw = fw;
6268
6269     init_drxk(state);
6270 }
6271
6272 static void drxk_release(struct dvb_frontend *fe)
6273 {
6274     struct drxk_state *state = fe->demodulator_priv;
6275
6276     dprintk(1, "\n");
6277     release_firmware(state->fw);
6278
6279     kfree(state);
6280 }
6281
6282 static int drxk_sleep(struct dvb_frontend *fe)
6283 {
6284     struct drxk_state *state = fe->demodulator_priv;
6285
6286     dprintk(1, "\n");
6287
6288     if (state->m_drxk_state == DRXK_NO_DEV)
6289         return -ENODEV;
6290     if (state->m_drxk_state == DRXK_UNINITIALIZED)
6291         return 0;
6292
6293     shut_down(state);
6294     return 0;
6295 }
6296
6297 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6298 {
6299     struct drxk_state *state = fe->demodulator_priv;
6300
6301     dprintk(1, ": %s\n", enable ? "enable" : "disable");
6302
6303     if (state->m_drxk_state == DRXK_NO_DEV)
6304         return -ENODEV;
6305
6306     return ConfigureI2CBridge(state, enable ? true : false);
6307 }
6308
6309 static int drxk_set_parameters(struct dvb_frontend *fe)
6310 {
6311     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6312     u32 delsys  = p->delivery_system, old_delsys;
6313     struct drxk_state *state = fe->demodulator_priv;
6314     u32 IF;
6315
6316     dprintk(1, "\n");
6317
6318     if (state->m_drxk_state == DRXK_NO_DEV)
6319         return -ENODEV;
6320
6321     if (state->m_drxk_state == DRXK_UNINITIALIZED)
6322         return -EAGAIN;
6323
6324     if (!fe->ops.tuner_ops.get_if_frequency) {
6325         pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6326         return -EINVAL;
6327     }
6328
6329     if (fe->ops.i2c_gate_ctrl)
6330         fe->ops.i2c_gate_ctrl(fe, 1);
6331     if (fe->ops.tuner_ops.set_params)
6332         fe->ops.tuner_ops.set_params(fe);
6333     if (fe->ops.i2c_gate_ctrl)
6334         fe->ops.i2c_gate_ctrl(fe, 0);
6335
6336     old_delsys = state->props.delivery_system;
6337     state->props = *p;
6338
6339     if (old_delsys != delsys) {
6340         shut_down(state);
6341         switch (delsys) {
6342         case SYS_DVBC_ANNEX_A:
6343         case SYS_DVBC_ANNEX_C:
6344             if (!state->m_has_dvbc)
6345                 return -EINVAL;
6346             state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?
6347                         true : false;
6348             if (state->m_itut_annex_c)
6349                 setoperation_mode(state, OM_QAM_ITU_C);
6350             else
6351                 setoperation_mode(state, OM_QAM_ITU_A);
6352             break;
6353         case SYS_DVBT:
6354             if (!state->m_has_dvbt)
6355                 return -EINVAL;
6356             setoperation_mode(state, OM_DVBT);
6357             break;
6358         default:
6359             return -EINVAL;
6360         }
6361     }
6362
6363     fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6364     start(state, 0, IF);
6365
6366     /* After set_frontend, stats aren't available */
6367     p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6368     p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6369     p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6370     p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6371     p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6372     p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6373     p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6374     p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6375
6376     /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6377
6378     return 0;
6379 }
6380
6381 static int get_strength(struct drxk_state *state, u64 *strength)
6382 {
6383     int status;
6384     struct s_cfg_agc   rf_agc, if_agc;
6385     u32          total_gain  = 0;
6386     u32          atten      = 0;
6387     u32          agc_range   = 0;
6388     u16            scu_lvl  = 0;
6389     u16            scu_coc  = 0;
6390     /* FIXME: those are part of the tuner presets */
6391     u16 tuner_rf_gain         = 50; /* Default value on az6007 driver */
6392     u16 tuner_if_gain         = 40; /* Default value on az6007 driver */
6393
6394     *strength = 0;
6395
6396     if (is_dvbt(state)) {
6397         rf_agc = state->m_dvbt_rf_agc_cfg;
6398         if_agc = state->m_dvbt_if_agc_cfg;
6399     } else if (is_qam(state)) {
6400         rf_agc = state->m_qam_rf_agc_cfg;
6401         if_agc = state->m_qam_if_agc_cfg;
6402     } else {
6403         rf_agc = state->m_atv_rf_agc_cfg;
6404         if_agc = state->m_atv_if_agc_cfg;
6405     }
6406
6407     if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6408         /* SCU output_level */
6409         status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6410         if (status < 0)
6411             return status;
6412
6413         /* SCU c.o.c. */
6414         status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
6415         if (status < 0)
6416             return status;
6417
6418         if (((u32) scu_lvl + (u32) scu_coc) < 0xffff)
6419             rf_agc.output_level = scu_lvl + scu_coc;
6420         else
6421             rf_agc.output_level = 0xffff;
6422
6423         /* Take RF gain into account */
6424         total_gain += tuner_rf_gain;
6425
6426         /* clip output value */
6427         if (rf_agc.output_level < rf_agc.min_output_level)
6428             rf_agc.output_level = rf_agc.min_output_level;
6429         if (rf_agc.output_level > rf_agc.max_output_level)
6430             rf_agc.output_level = rf_agc.max_output_level;
6431
6432         agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level);
6433         if (agc_range > 0) {
6434             atten += 100UL *
6435                 ((u32)(tuner_rf_gain)) *
6436                 ((u32)(rf_agc.output_level - rf_agc.min_output_level))
6437                 / agc_range;
6438         }
6439     }
6440
6441     if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6442         status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6443                 &if_agc.output_level);
6444         if (status < 0)
6445             return status;
6446
6447         status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6448                 &if_agc.top);
6449         if (status < 0)
6450             return status;
6451
6452         /* Take IF gain into account */
6453         total_gain += (u32) tuner_if_gain;
6454
6455         /* clip output value */
6456         if (if_agc.output_level < if_agc.min_output_level)
6457             if_agc.output_level = if_agc.min_output_level;
6458         if (if_agc.output_level > if_agc.max_output_level)
6459             if_agc.output_level = if_agc.max_output_level;
6460
6461         agc_range  = (u32)(if_agc.max_output_level - if_agc.min_output_level);
6462         if (agc_range > 0) {
6463             atten += 100UL *
6464                 ((u32)(tuner_if_gain)) *
6465                 ((u32)(if_agc.output_level - if_agc.min_output_level))
6466                 / agc_range;
6467         }
6468     }
6469
6470     /*
6471      * Convert to 0..65535 scale.
6472      * If it can't be measured (AGC is disabled), just show 100%.
6473      */
6474     if (total_gain > 0)
6475         *strength = (65535UL * atten / total_gain / 100);
6476     else
6477         *strength = 65535;
6478
6479     return 0;
6480 }
6481
6482 static int drxk_get_stats(struct dvb_frontend *fe)
6483 {
6484     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6485     struct drxk_state *state = fe->demodulator_priv;
6486     int status;
6487     u32 stat;
6488     u16 reg16;
6489     u32 post_bit_count;
6490     u32 post_bit_err_count;
6491     u32 post_bit_error_scale;
6492     u32 pre_bit_err_count;
6493     u32 pre_bit_count;
6494     u32 pkt_count;
6495     u32 pkt_error_count;
6496     s32 cnr;
6497
6498     if (state->m_drxk_state == DRXK_NO_DEV)
6499         return -ENODEV;
6500     if (state->m_drxk_state == DRXK_UNINITIALIZED)
6501         return -EAGAIN;
6502
6503     /* get status */
6504     state->fe_status = 0;
6505     get_lock_status(state, &stat);
6506     if (stat == MPEG_LOCK)
6507         state->fe_status |= 0x1f;
6508     if (stat == FEC_LOCK)
6509         state->fe_status |= 0x0f;
6510     if (stat == DEMOD_LOCK)
6511         state->fe_status |= 0x07;
6512
6513     /*
6514      * Estimate signal strength from AGC
6515      */
6516     get_strength(state, &c->strength.stat[0].uvalue);
6517     c->strength.stat[0].scale = FE_SCALE_RELATIVE;
6518
6519
6520     if (stat >= DEMOD_LOCK) {
6521         get_signal_to_noise(state, &cnr);
6522         c->cnr.stat[0].svalue = cnr * 100;
6523         c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
6524     } else {
6525         c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6526     }
6527
6528     if (stat < FEC_LOCK) {
6529         c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6530         c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6531         c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6532         c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6533         c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6534         c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6535         return 0;
6536     }
6537
6538     /* Get post BER */
6539
6540     /* BER measurement is valid if at least FEC lock is achieved */
6541
6542     /*
6543      * OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be
6544      * written to set nr of symbols or bits over which to measure
6545      * EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg().
6546      */
6547
6548     /* Read registers for post/preViterbi BER calculation */
6549     status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16);
6550     if (status < 0)
6551         goto error;
6552     pre_bit_err_count = reg16;
6553
6554     status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , &reg16);
6555     if (status < 0)
6556         goto error;
6557     pre_bit_count = reg16;
6558
6559     /* Number of bit-errors */
6560     status = read16(state, FEC_RS_NR_BIT_ERRORS__A, &reg16);
6561     if (status < 0)
6562         goto error;
6563     post_bit_err_count = reg16;
6564
6565     status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, &reg16);
6566     if (status < 0)
6567         goto error;
6568     post_bit_error_scale = reg16;
6569
6570     status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, &reg16);
6571     if (status < 0)
6572         goto error;
6573     pkt_count = reg16;
6574
6575     status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &reg16);
6576     if (status < 0)
6577         goto error;
6578     pkt_error_count = reg16;
6579     write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
6580
6581     post_bit_err_count *= post_bit_error_scale;
6582
6583     post_bit_count = pkt_count * 204 * 8;
6584
6585     /* Store the results */
6586     c->block_error.stat[0].scale = FE_SCALE_COUNTER;
6587     c->block_error.stat[0].uvalue += pkt_error_count;
6588     c->block_count.stat[0].scale = FE_SCALE_COUNTER;
6589     c->block_count.stat[0].uvalue += pkt_count;
6590
6591     c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6592     c->pre_bit_error.stat[0].uvalue += pre_bit_err_count;
6593     c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6594     c->pre_bit_count.stat[0].uvalue += pre_bit_count;
6595
6596     c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6597     c->post_bit_error.stat[0].uvalue += post_bit_err_count;
6598     c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6599     c->post_bit_count.stat[0].uvalue += post_bit_count;
6600
6601 error:
6602     return status;
6603 }
6604
6605
6606 static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status)
6607 {
6608     struct drxk_state *state = fe->demodulator_priv;
6609     int rc;
6610
6611     dprintk(1, "\n");
6612
6613     rc = drxk_get_stats(fe);
6614     if (rc < 0)
6615         return rc;
6616
6617     *status = state->fe_status;
6618
6619     return 0;
6620 }
6621
6622 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6623                      u16 *strength)
6624 {
6625     struct drxk_state *state = fe->demodulator_priv;
6626     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6627
6628     dprintk(1, "\n");
6629
6630     if (state->m_drxk_state == DRXK_NO_DEV)
6631         return -ENODEV;
6632     if (state->m_drxk_state == DRXK_UNINITIALIZED)
6633         return -EAGAIN;
6634
6635     *strength = c->strength.stat[0].uvalue;
6636     return 0;
6637 }
6638
6639 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6640 {
6641     struct drxk_state *state = fe->demodulator_priv;
6642     s32 snr2;
6643
6644     dprintk(1, "\n");
6645
6646     if (state->m_drxk_state == DRXK_NO_DEV)
6647         return -ENODEV;
6648     if (state->m_drxk_state == DRXK_UNINITIALIZED)
6649         return -EAGAIN;
6650
6651     get_signal_to_noise(state, &snr2);
6652
6653     /* No negative SNR, clip to zero */
6654     if (snr2 < 0)
6655         snr2 = 0;
6656     *snr = snr2 & 0xffff;
6657     return 0;
6658 }
6659
6660 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6661 {
6662     struct drxk_state *state = fe->demodulator_priv;
6663     u16 err;
6664
6665     dprintk(1, "\n");
6666
6667     if (state->m_drxk_state == DRXK_NO_DEV)
6668         return -ENODEV;
6669     if (state->m_drxk_state == DRXK_UNINITIALIZED)
6670         return -EAGAIN;
6671
6672     dvbtqam_get_acc_pkt_err(state, &err);
6673     *ucblocks = (u32) err;
6674     return 0;
6675 }
6676
6677 static int drxk_get_tune_settings(struct dvb_frontend *fe,
6678                   struct dvb_frontend_tune_settings *sets)
6679 {
6680     struct drxk_state *state = fe->demodulator_priv;
6681     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6682
6683     dprintk(1, "\n");
6684
6685     if (state->m_drxk_state == DRXK_NO_DEV)
6686         return -ENODEV;
6687     if (state->m_drxk_state == DRXK_UNINITIALIZED)
6688         return -EAGAIN;
6689
6690     switch (p->delivery_system) {
6691     case SYS_DVBC_ANNEX_A:
6692     case SYS_DVBC_ANNEX_C:
6693     case SYS_DVBT:
6694         sets->min_delay_ms = 3000;
6695         sets->max_drift = 0;
6696         sets->step_size = 0;
6697         return 0;
6698     default:
6699         return -EINVAL;
6700     }
6701 }
6702
6703 static const struct dvb_frontend_ops drxk_ops = {
6704     /* .delsys will be filled dynamically */
6705     .info = {
6706         .name = "DRXK",
6707         .frequency_min_hz =  47 * MHz,
6708         .frequency_max_hz = 865 * MHz,
6709          /* For DVB-C */
6710         .symbol_rate_min =   870000,
6711         .symbol_rate_max = 11700000,
6712         /* For DVB-T */
6713         .frequency_stepsize_hz = 166667,
6714
6715         .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6716             FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6717             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6718             FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6719             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6720             FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6721     },
6722
6723     .release = drxk_release,
6724     .sleep = drxk_sleep,
6725     .i2c_gate_ctrl = drxk_gate_ctrl,
6726
6727     .set_frontend = drxk_set_parameters,
6728     .get_tune_settings = drxk_get_tune_settings,
6729
6730     .read_status = drxk_read_status,
6731     .read_signal_strength = drxk_read_signal_strength,
6732     .read_snr = drxk_read_snr,
6733     .read_ucblocks = drxk_read_ucblocks,
6734 };
6735
6736 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6737                  struct i2c_adapter *i2c)
6738 {
6739     struct dtv_frontend_properties *p;
6740     struct drxk_state *state = NULL;
6741     u8 adr = config->adr;
6742     int status;
6743
6744     dprintk(1, "\n");
6745     state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6746     if (!state)
6747         return NULL;
6748
6749     state->i2c = i2c;
6750     state->demod_address = adr;
6751     state->single_master = config->single_master;
6752     state->microcode_name = config->microcode_name;
6753     state->qam_demod_parameter_count = config->qam_demod_parameter_count;
6754     state->no_i2c_bridge = config->no_i2c_bridge;
6755     state->antenna_gpio = config->antenna_gpio;
6756     state->antenna_dvbt = config->antenna_dvbt;
6757     state->m_chunk_size = config->chunk_size;
6758     state->enable_merr_cfg = config->enable_merr_cfg;
6759
6760     if (config->dynamic_clk) {
6761         state->m_dvbt_static_clk = false;
6762         state->m_dvbc_static_clk = false;
6763     } else {
6764         state->m_dvbt_static_clk = true;
6765         state->m_dvbc_static_clk = true;
6766     }
6767
6768
6769     if (config->mpeg_out_clk_strength)
6770         state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;
6771     else
6772         state->m_ts_clockk_strength = 0x06;
6773
6774     if (config->parallel_ts)
6775         state->m_enable_parallel = true;
6776     else
6777         state->m_enable_parallel = false;
6778
6779     /* NOTE: as more UIO bits will be used, add them to the mask */
6780     state->uio_mask = config->antenna_gpio;
6781
6782     /* Default gpio to DVB-C */
6783     if (!state->antenna_dvbt && state->antenna_gpio)
6784         state->m_gpio |= state->antenna_gpio;
6785     else
6786         state->m_gpio &= ~state->antenna_gpio;
6787
6788     mutex_init(&state->mutex);
6789
6790     memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6791     state->frontend.demodulator_priv = state;
6792
6793     init_state(state);
6794
6795     /* Load firmware and initialize DRX-K */
6796     if (state->microcode_name) {
6797         const struct firmware *fw = NULL;
6798
6799         status = request_firmware(&fw, state->microcode_name,
6800                       state->i2c->dev.parent);
6801         if (status < 0)
6802             fw = NULL;
6803         load_firmware_cb(fw, state);
6804     } else if (init_drxk(state) < 0)
6805         goto error;
6806
6807
6808     /* Initialize stats */
6809     p = &state->frontend.dtv_property_cache;
6810     p->strength.len = 1;
6811     p->cnr.len = 1;
6812     p->block_error.len = 1;
6813     p->block_count.len = 1;
6814     p->pre_bit_error.len = 1;
6815     p->pre_bit_count.len = 1;
6816     p->post_bit_error.len = 1;
6817     p->post_bit_count.len = 1;
6818
6819     p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6820     p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6821     p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6822     p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6823     p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6824     p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6825     p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6826     p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6827
6828     pr_info("frontend initialized.\n");
6829     return &state->frontend;
6830
6831 error:
6832     pr_err("not found\n");
6833     kfree(state);
6834     return NULL;
6835 }
6836 EXPORT_SYMBOL(drxk_attach);
6837
6838 MODULE_DESCRIPTION("DRX-K driver");
6839 MODULE_AUTHOR("Ralph Metzler");
6840 MODULE_LICENSE("GPL");