media/dvb-frontends/drxd_firm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * drxd_firm.h
0004  *
0005  * Copyright (C) 2006-2007 Micronas
0006  */
0007
0008 #ifndef _DRXD_FIRM_H_
0009 #define _DRXD_FIRM_H_
0010
0011 #include <linux/types.h>
0012 #include "drxd_map_firm.h"
0013
0014 #define VERSION_MAJOR 1
0015 #define VERSION_MINOR 4
0016 #define VERSION_PATCH 23
0017
0018 #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
0019
0020 #define DRXD_MAX_RETRIES (1000)
0021 #define HI_I2C_DELAY     84
0022 #define HI_I2C_BRIDGE_DELAY   750
0023
0024 #define EQ_TD_TPS_PWR_UNKNOWN          0x00C0   /* Unknown configurations */
0025 #define EQ_TD_TPS_PWR_QPSK             0x016a
0026 #define EQ_TD_TPS_PWR_QAM16_ALPHAN     0x0195
0027 #define EQ_TD_TPS_PWR_QAM16_ALPHA1     0x0195
0028 #define EQ_TD_TPS_PWR_QAM16_ALPHA2     0x011E
0029 #define EQ_TD_TPS_PWR_QAM16_ALPHA4     0x01CE
0030 #define EQ_TD_TPS_PWR_QAM64_ALPHAN     0x019F
0031 #define EQ_TD_TPS_PWR_QAM64_ALPHA1     0x019F
0032 #define EQ_TD_TPS_PWR_QAM64_ALPHA2     0x00F8
0033 #define EQ_TD_TPS_PWR_QAM64_ALPHA4     0x014D
0034
0035 #define DRXD_DEF_AG_PWD_CONSUMER 0x000E
0036 #define DRXD_DEF_AG_PWD_PRO 0x0000
0037 #define DRXD_DEF_AG_AGC_SIO 0x0000
0038
0039 #define DRXD_FE_CTRL_MAX 1023
0040
0041 #define DRXD_OSCDEV_DO_SCAN  (16)
0042
0043 #define DRXD_OSCDEV_DONT_SCAN  (0)
0044
0045 #define DRXD_OSCDEV_STEP  (275)
0046
0047 #define DRXD_SCAN_TIMEOUT    (650)
0048
0049 #define DRXD_BANDWIDTH_8MHZ_IN_HZ  (0x8B8249L)
0050 #define DRXD_BANDWIDTH_7MHZ_IN_HZ  (0x7A1200L)
0051 #define DRXD_BANDWIDTH_6MHZ_IN_HZ  (0x68A1B6L)
0052
0053 #define IRLEN_COARSE_8K       (10)
0054 #define IRLEN_FINE_8K         (10)
0055 #define IRLEN_COARSE_2K       (7)
0056 #define IRLEN_FINE_2K         (9)
0057 #define DIFF_INVALID          (511)
0058 #define DIFF_TARGET           (4)
0059 #define DIFF_MARGIN           (1)
0060
0061 extern u8 DRXD_InitAtomicRead[];
0062 extern u8 DRXD_HiI2cPatch_1[];
0063 extern u8 DRXD_HiI2cPatch_3[];
0064
0065 extern u8 DRXD_InitSC[];
0066
0067 extern u8 DRXD_ResetCEFR[];
0068 extern u8 DRXD_InitFEA2_1[];
0069 extern u8 DRXD_InitFEA2_2[];
0070 extern u8 DRXD_InitCPA2[];
0071 extern u8 DRXD_InitCEA2[];
0072 extern u8 DRXD_InitEQA2[];
0073 extern u8 DRXD_InitECA2[];
0074 extern u8 DRXD_ResetECA2[];
0075 extern u8 DRXD_ResetECRAM[];
0076
0077 extern u8 DRXD_A2_microcode[];
0078 extern u32 DRXD_A2_microcode_length;
0079
0080 extern u8 DRXD_InitFEB1_1[];
0081 extern u8 DRXD_InitFEB1_2[];
0082 extern u8 DRXD_InitCPB1[];
0083 extern u8 DRXD_InitCEB1[];
0084 extern u8 DRXD_InitEQB1[];
0085 extern u8 DRXD_InitECB1[];
0086
0087 extern u8 DRXD_InitDiversityFront[];
0088 extern u8 DRXD_InitDiversityEnd[];
0089 extern u8 DRXD_DisableDiversity[];
0090 extern u8 DRXD_StartDiversityFront[];
0091 extern u8 DRXD_StartDiversityEnd[];
0092
0093 extern u8 DRXD_DiversityDelay8MHZ[];
0094 extern u8 DRXD_DiversityDelay6MHZ[];
0095
0096 extern u8 DRXD_B1_microcode[];
0097 extern u32 DRXD_B1_microcode_length;
0098
0099 #endif