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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * drxd_firm.c : DRXD firmware tables
0004  *
0005  * Copyright (C) 2006-2007 Micronas
0006  */
0007 
0008 /* TODO: generate this file with a script from a settings file */
0009 
0010 /* Contains A2 firmware version: 1.4.2
0011  * Contains B1 firmware version: 3.3.33
0012  * Contains settings from driver 1.4.23
0013 */
0014 
0015 #include "drxd_firm.h"
0016 
0017 #define ADDRESS(x)     ((x) & 0xFF), (((x)>>8) & 0xFF), (((x)>>16) & 0xFF), (((x)>>24) & 0xFF)
0018 #define LENGTH(x)      ((x) & 0xFF), (((x)>>8) & 0xFF)
0019 
0020 /* Is written via block write, must be little endian */
0021 #define DATA16(x)      ((x) & 0xFF), (((x)>>8) & 0xFF)
0022 
0023 #define WRBLOCK(a, l) ADDRESS(a), LENGTH(l)
0024 #define WR16(a, d) ADDRESS(a), LENGTH(1), DATA16(d)
0025 
0026 #define END_OF_TABLE      0xFF, 0xFF, 0xFF, 0xFF
0027 
0028 /* HI firmware patches */
0029 
0030 #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
0031 #define HI_TR_FUNC_SIZE 9   /* size of this function in instruction words */
0032 
0033 u8 DRXD_InitAtomicRead[] = {
0034     WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE),
0035     0x26, 0x00,     /* 0         -> ring.rdy;           */
0036     0x60, 0x04,     /* r0rami.dt -> ring.xba;           */
0037     0x61, 0x04,     /* r0rami.dt -> ring.xad;           */
0038     0xE3, 0x07,     /* HI_RA_RAM_USR_BEGIN -> ring.iad; */
0039     0x40, 0x00,     /* (long immediate)                 */
0040     0x64, 0x04,     /* r0rami.dt -> ring.len;           */
0041     0x65, 0x04,     /* r0rami.dt -> ring.ctl;           */
0042     0x26, 0x00,     /* 0         -> ring.rdy;           */
0043     0x38, 0x00,     /* 0         -> jumps.ad;           */
0044     END_OF_TABLE
0045 };
0046 
0047 /* Pins D0 and D1 of the parallel MPEG output can be used
0048    to set the I2C address of a device. */
0049 
0050 #define HI_RST_FUNC_ADDR (HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE)
0051 #define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */
0052 
0053 /* D0 Version */
0054 u8 DRXD_HiI2cPatch_1[] = {
0055     WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
0056     0xC8, 0x07, 0x01, 0x00, /* MASK      -> reg0.dt;                        */
0057     0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
0058     0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
0059     0xA2, 0x00,     /* M_BNK_ID_DAT -> ring.iba;                    */
0060     0x23, 0x00,     /* &data     -> ring.iad;                       */
0061     0x24, 0x00,     /* 0         -> ring.len;                       */
0062     0xA5, 0x02,     /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
0063     0x26, 0x00,     /* 0         -> ring.rdy;                       */
0064     0x42, 0x00,     /* &data+1   -> w0ram.ad;                       */
0065     0xC0, 0x07, 0xFF, 0x0F, /* -1        -> w0ram.dt;                       */
0066     0x63, 0x00,     /* &data+1   -> ring.iad;                       */
0067     0x65, 0x02,     /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
0068     0x26, 0x00,     /* 0         -> ring.rdy;                       */
0069     0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad;    */
0070     0xA5, 0x02,     /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
0071     0x26, 0x00,     /* 0         -> ring.rdy;                       */
0072     0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
0073     0x23, 0x00,     /* &data     -> ring.iad;                       */
0074     0x65, 0x02,     /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
0075     0x26, 0x00,     /* 0         -> ring.rdy;                       */
0076     0x42, 0x00,     /* &data+1   -> w0ram.ad;                       */
0077     0x0F, 0x04,     /* r0ram.dt  -> and.op;                         */
0078     0x1C, 0x06,     /* reg0.dt   -> and.tr;                         */
0079     0xCF, 0x04,     /* and.rs    -> add.op;                         */
0080     0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr;                        */
0081     0xD0, 0x04,     /* add.rs    -> add.tr;                         */
0082     0xC8, 0x04,     /* add.rs    -> reg0.dt;                        */
0083     0x60, 0x00,     /* reg0.dt   -> w0ram.dt;                       */
0084     0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad;                      */
0085     0x01, 0x00,     /* 0         -> w0rami.dt;                      */
0086     0x01, 0x06,     /* reg0.dt   -> w0rami.dt;                      */
0087     0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad;                      */
0088     0x01, 0x00,     /* 0         -> w0rami.dt;                      */
0089     0x01, 0x06,     /* reg0.dt   -> w0rami.dt;                      */
0090     0xC2, 0x07, 0x30, 0x00, /* CMD_BASE  -> w0rami.ad;                      */
0091     0x01, 0x00,     /* 0         -> w0rami.dt;                      */
0092     0x01, 0x00,     /* 0         -> w0rami.dt;                      */
0093     0x01, 0x00,     /* 0         -> w0rami.dt;                      */
0094     0x68, 0x00,     /* M_IC_SEL_PT1 -> i2c.sel;                     */
0095     0x29, 0x00,     /* M_IC_CMD_RESET -> i2c.cmd;                   */
0096     0x28, 0x00,     /* M_IC_SEL_PT0 -> i2c.sel;                     */
0097     0x29, 0x00,     /* M_IC_CMD_RESET -> i2c.cmd;                   */
0098     0xF8, 0x07, 0x2F, 0x00, /* 0x2F      -> jumps.ad;                       */
0099 
0100     WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
0101          (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
0102     WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
0103          (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
0104     WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
0105          (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
0106     WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
0107          (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
0108 
0109     /* Force quick and dirty reset */
0110     WR16(B_HI_CT_REG_COMM_STATE__A, 0),
0111     END_OF_TABLE
0112 };
0113 
0114 /* D0,D1 Version */
0115 u8 DRXD_HiI2cPatch_3[] = {
0116     WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
0117     0xC8, 0x07, 0x03, 0x00, /* MASK      -> reg0.dt;                        */
0118     0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
0119     0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
0120     0xA2, 0x00,     /* M_BNK_ID_DAT -> ring.iba;                    */
0121     0x23, 0x00,     /* &data     -> ring.iad;                       */
0122     0x24, 0x00,     /* 0         -> ring.len;                       */
0123     0xA5, 0x02,     /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
0124     0x26, 0x00,     /* 0         -> ring.rdy;                       */
0125     0x42, 0x00,     /* &data+1   -> w0ram.ad;                       */
0126     0xC0, 0x07, 0xFF, 0x0F, /* -1        -> w0ram.dt;                       */
0127     0x63, 0x00,     /* &data+1   -> ring.iad;                       */
0128     0x65, 0x02,     /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
0129     0x26, 0x00,     /* 0         -> ring.rdy;                       */
0130     0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad;    */
0131     0xA5, 0x02,     /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl;   */
0132     0x26, 0x00,     /* 0         -> ring.rdy;                       */
0133     0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad;         */
0134     0x23, 0x00,     /* &data     -> ring.iad;                       */
0135     0x65, 0x02,     /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl;  */
0136     0x26, 0x00,     /* 0         -> ring.rdy;                       */
0137     0x42, 0x00,     /* &data+1   -> w0ram.ad;                       */
0138     0x0F, 0x04,     /* r0ram.dt  -> and.op;                         */
0139     0x1C, 0x06,     /* reg0.dt   -> and.tr;                         */
0140     0xCF, 0x04,     /* and.rs    -> add.op;                         */
0141     0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr;                        */
0142     0xD0, 0x04,     /* add.rs    -> add.tr;                         */
0143     0xC8, 0x04,     /* add.rs    -> reg0.dt;                        */
0144     0x60, 0x00,     /* reg0.dt   -> w0ram.dt;                       */
0145     0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad;                      */
0146     0x01, 0x00,     /* 0         -> w0rami.dt;                      */
0147     0x01, 0x06,     /* reg0.dt   -> w0rami.dt;                      */
0148     0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad;                      */
0149     0x01, 0x00,     /* 0         -> w0rami.dt;                      */
0150     0x01, 0x06,     /* reg0.dt   -> w0rami.dt;                      */
0151     0xC2, 0x07, 0x30, 0x00, /* CMD_BASE  -> w0rami.ad;                      */
0152     0x01, 0x00,     /* 0         -> w0rami.dt;                      */
0153     0x01, 0x00,     /* 0         -> w0rami.dt;                      */
0154     0x01, 0x00,     /* 0         -> w0rami.dt;                      */
0155     0x68, 0x00,     /* M_IC_SEL_PT1 -> i2c.sel;                     */
0156     0x29, 0x00,     /* M_IC_CMD_RESET -> i2c.cmd;                   */
0157     0x28, 0x00,     /* M_IC_SEL_PT0 -> i2c.sel;                     */
0158     0x29, 0x00,     /* M_IC_CMD_RESET -> i2c.cmd;                   */
0159     0xF8, 0x07, 0x2F, 0x00, /* 0x2F      -> jumps.ad;                       */
0160 
0161     WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
0162          (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
0163     WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
0164          (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
0165     WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
0166          (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
0167     WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
0168          (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
0169 
0170     /* Force quick and dirty reset */
0171     WR16(B_HI_CT_REG_COMM_STATE__A, 0),
0172     END_OF_TABLE
0173 };
0174 
0175 u8 DRXD_ResetCEFR[] = {
0176     WRBLOCK(CE_REG_FR_TREAL00__A, 57),
0177     0x52, 0x00,     /* CE_REG_FR_TREAL00__A */
0178     0x00, 0x00,     /* CE_REG_FR_TIMAG00__A */
0179     0x52, 0x00,     /* CE_REG_FR_TREAL01__A */
0180     0x00, 0x00,     /* CE_REG_FR_TIMAG01__A */
0181     0x52, 0x00,     /* CE_REG_FR_TREAL02__A */
0182     0x00, 0x00,     /* CE_REG_FR_TIMAG02__A */
0183     0x52, 0x00,     /* CE_REG_FR_TREAL03__A */
0184     0x00, 0x00,     /* CE_REG_FR_TIMAG03__A */
0185     0x52, 0x00,     /* CE_REG_FR_TREAL04__A */
0186     0x00, 0x00,     /* CE_REG_FR_TIMAG04__A */
0187     0x52, 0x00,     /* CE_REG_FR_TREAL05__A */
0188     0x00, 0x00,     /* CE_REG_FR_TIMAG05__A */
0189     0x52, 0x00,     /* CE_REG_FR_TREAL06__A */
0190     0x00, 0x00,     /* CE_REG_FR_TIMAG06__A */
0191     0x52, 0x00,     /* CE_REG_FR_TREAL07__A */
0192     0x00, 0x00,     /* CE_REG_FR_TIMAG07__A */
0193     0x52, 0x00,     /* CE_REG_FR_TREAL08__A */
0194     0x00, 0x00,     /* CE_REG_FR_TIMAG08__A */
0195     0x52, 0x00,     /* CE_REG_FR_TREAL09__A */
0196     0x00, 0x00,     /* CE_REG_FR_TIMAG09__A */
0197     0x52, 0x00,     /* CE_REG_FR_TREAL10__A */
0198     0x00, 0x00,     /* CE_REG_FR_TIMAG10__A */
0199     0x52, 0x00,     /* CE_REG_FR_TREAL11__A */
0200     0x00, 0x00,     /* CE_REG_FR_TIMAG11__A */
0201 
0202     0x52, 0x00,     /* CE_REG_FR_MID_TAP__A */
0203 
0204     0x0B, 0x00,     /* CE_REG_FR_SQS_G00__A */
0205     0x0B, 0x00,     /* CE_REG_FR_SQS_G01__A */
0206     0x0B, 0x00,     /* CE_REG_FR_SQS_G02__A */
0207     0x0B, 0x00,     /* CE_REG_FR_SQS_G03__A */
0208     0x0B, 0x00,     /* CE_REG_FR_SQS_G04__A */
0209     0x0B, 0x00,     /* CE_REG_FR_SQS_G05__A */
0210     0x0B, 0x00,     /* CE_REG_FR_SQS_G06__A */
0211     0x0B, 0x00,     /* CE_REG_FR_SQS_G07__A */
0212     0x0B, 0x00,     /* CE_REG_FR_SQS_G08__A */
0213     0x0B, 0x00,     /* CE_REG_FR_SQS_G09__A */
0214     0x0B, 0x00,     /* CE_REG_FR_SQS_G10__A */
0215     0x0B, 0x00,     /* CE_REG_FR_SQS_G11__A */
0216     0x0B, 0x00,     /* CE_REG_FR_SQS_G12__A */
0217 
0218     0xFF, 0x01,     /* CE_REG_FR_RIO_G00__A */
0219     0x90, 0x01,     /* CE_REG_FR_RIO_G01__A */
0220     0x0B, 0x01,     /* CE_REG_FR_RIO_G02__A */
0221     0xC8, 0x00,     /* CE_REG_FR_RIO_G03__A */
0222     0xA0, 0x00,     /* CE_REG_FR_RIO_G04__A */
0223     0x85, 0x00,     /* CE_REG_FR_RIO_G05__A */
0224     0x72, 0x00,     /* CE_REG_FR_RIO_G06__A */
0225     0x64, 0x00,     /* CE_REG_FR_RIO_G07__A */
0226     0x59, 0x00,     /* CE_REG_FR_RIO_G08__A */
0227     0x50, 0x00,     /* CE_REG_FR_RIO_G09__A */
0228     0x49, 0x00,     /* CE_REG_FR_RIO_G10__A */
0229 
0230     0x10, 0x00,     /* CE_REG_FR_MODE__A     */
0231     0x78, 0x00,     /* CE_REG_FR_SQS_TRH__A  */
0232     0x00, 0x00,     /* CE_REG_FR_RIO_GAIN__A */
0233     0x00, 0x02,     /* CE_REG_FR_BYPASS__A   */
0234     0x0D, 0x00,     /* CE_REG_FR_PM_SET__A   */
0235     0x07, 0x00,     /* CE_REG_FR_ERR_SH__A   */
0236     0x04, 0x00,     /* CE_REG_FR_MAN_SH__A   */
0237     0x06, 0x00,     /* CE_REG_FR_TAP_SH__A   */
0238 
0239     END_OF_TABLE
0240 };
0241 
0242 u8 DRXD_InitFEA2_1[] = {
0243     WRBLOCK(FE_AD_REG_PD__A, 3),
0244     0x00, 0x00,     /* FE_AD_REG_PD__A          */
0245     0x01, 0x00,     /* FE_AD_REG_INVEXT__A      */
0246     0x00, 0x00,     /* FE_AD_REG_CLKNEG__A      */
0247 
0248     WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A, 2),
0249     0x10, 0x00,     /* FE_AG_REG_DCE_AUR_CNT__A */
0250     0x10, 0x00,     /* FE_AG_REG_DCE_RUR_CNT__A */
0251 
0252     WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A, 2),
0253     0x0E, 0x00,     /* FE_AG_REG_ACE_AUR_CNT__A */
0254     0x00, 0x00,     /* FE_AG_REG_ACE_RUR_CNT__A */
0255 
0256     WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A, 5),
0257     0x04, 0x00,     /* FE_AG_REG_EGC_FLA_RGN__A */
0258     0x1F, 0x00,     /* FE_AG_REG_EGC_SLO_RGN__A */
0259     0x00, 0x00,     /* FE_AG_REG_EGC_JMP_PSN__A */
0260     0x00, 0x00,     /* FE_AG_REG_EGC_FLA_INC__A */
0261     0x00, 0x00,     /* FE_AG_REG_EGC_FLA_DEC__A */
0262 
0263     WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A, 2),
0264     0xFF, 0x01,     /* FE_AG_REG_GC1_AGC_MAX__A */
0265     0x00, 0xFE,     /* FE_AG_REG_GC1_AGC_MIN__A */
0266 
0267     WRBLOCK(FE_AG_REG_IND_WIN__A, 29),
0268     0x00, 0x00,     /* FE_AG_REG_IND_WIN__A     */
0269     0x05, 0x00,     /* FE_AG_REG_IND_THD_LOL__A */
0270     0x0F, 0x00,     /* FE_AG_REG_IND_THD_HIL__A */
0271     0x00, 0x00,     /* FE_AG_REG_IND_DEL__A     don't care */
0272     0x1E, 0x00,     /* FE_AG_REG_IND_PD1_WRI__A */
0273     0x0C, 0x00,     /* FE_AG_REG_PDA_AUR_CNT__A */
0274     0x00, 0x00,     /* FE_AG_REG_PDA_RUR_CNT__A */
0275     0x00, 0x00,     /* FE_AG_REG_PDA_AVE_DAT__A don't care  */
0276     0x00, 0x00,     /* FE_AG_REG_PDC_RUR_CNT__A */
0277     0x01, 0x00,     /* FE_AG_REG_PDC_SET_LVL__A */
0278     0x02, 0x00,     /* FE_AG_REG_PDC_FLA_RGN__A */
0279     0x00, 0x00,     /* FE_AG_REG_PDC_JMP_PSN__A don't care  */
0280     0xFF, 0xFF,     /* FE_AG_REG_PDC_FLA_STP__A */
0281     0xFF, 0xFF,     /* FE_AG_REG_PDC_SLO_STP__A */
0282     0x00, 0x1F,     /* FE_AG_REG_PDC_PD2_WRI__A don't care  */
0283     0x00, 0x00,     /* FE_AG_REG_PDC_MAP_DAT__A don't care  */
0284     0x02, 0x00,     /* FE_AG_REG_PDC_MAX__A     */
0285     0x0C, 0x00,     /* FE_AG_REG_TGA_AUR_CNT__A */
0286     0x00, 0x00,     /* FE_AG_REG_TGA_RUR_CNT__A */
0287     0x00, 0x00,     /* FE_AG_REG_TGA_AVE_DAT__A don't care  */
0288     0x00, 0x00,     /* FE_AG_REG_TGC_RUR_CNT__A */
0289     0x22, 0x00,     /* FE_AG_REG_TGC_SET_LVL__A */
0290     0x15, 0x00,     /* FE_AG_REG_TGC_FLA_RGN__A */
0291     0x00, 0x00,     /* FE_AG_REG_TGC_JMP_PSN__A don't care  */
0292     0x01, 0x00,     /* FE_AG_REG_TGC_FLA_STP__A */
0293     0x0A, 0x00,     /* FE_AG_REG_TGC_SLO_STP__A */
0294     0x00, 0x00,     /* FE_AG_REG_TGC_MAP_DAT__A don't care  */
0295     0x10, 0x00,     /* FE_AG_REG_FGA_AUR_CNT__A */
0296     0x10, 0x00,     /* FE_AG_REG_FGA_RUR_CNT__A */
0297 
0298     WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A, 2),
0299     0x00, 0x00,     /* FE_AG_REG_BGC_FGC_WRI__A */
0300     0x00, 0x00,     /* FE_AG_REG_BGC_CGC_WRI__A */
0301 
0302     WRBLOCK(FE_FD_REG_SCL__A, 3),
0303     0x05, 0x00,     /* FE_FD_REG_SCL__A         */
0304     0x03, 0x00,     /* FE_FD_REG_MAX_LEV__A     */
0305     0x05, 0x00,     /* FE_FD_REG_NR__A          */
0306 
0307     WRBLOCK(FE_CF_REG_SCL__A, 5),
0308     0x16, 0x00,     /* FE_CF_REG_SCL__A         */
0309     0x04, 0x00,     /* FE_CF_REG_MAX_LEV__A     */
0310     0x06, 0x00,     /* FE_CF_REG_NR__A          */
0311     0x00, 0x00,     /* FE_CF_REG_IMP_VAL__A     */
0312     0x01, 0x00,     /* FE_CF_REG_MEAS_VAL__A    */
0313 
0314     WRBLOCK(FE_CU_REG_FRM_CNT_RST__A, 2),
0315     0x00, 0x08,     /* FE_CU_REG_FRM_CNT_RST__A */
0316     0x00, 0x00,     /* FE_CU_REG_FRM_CNT_STR__A */
0317 
0318     END_OF_TABLE
0319 };
0320 
0321    /* with PGA */
0322 /*   WR16COND( DRXD_WITH_PGA, FE_AG_REG_AG_PGA_MODE__A   , 0x0004), */
0323    /* without PGA */
0324 /*   WR16COND( DRXD_WITHOUT_PGA, FE_AG_REG_AG_PGA_MODE__A   , 0x0001), */
0325 /*   WR16(FE_AG_REG_AG_AGC_SIO__A,  (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
0326 /*   WR16(FE_AG_REG_AG_PWD__A        ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
0327 
0328 u8 DRXD_InitFEA2_2[] = {
0329     WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
0330     WR16(FE_AG_REG_FGM_WRI__A, 48),
0331     /* Activate measurement, activate scale */
0332     WR16(FE_FD_REG_MEAS_VAL__A, 0x0001),
0333 
0334     WR16(FE_CU_REG_COMM_EXEC__A, 0x0001),
0335     WR16(FE_CF_REG_COMM_EXEC__A, 0x0001),
0336     WR16(FE_IF_REG_COMM_EXEC__A, 0x0001),
0337     WR16(FE_FD_REG_COMM_EXEC__A, 0x0001),
0338     WR16(FE_FS_REG_COMM_EXEC__A, 0x0001),
0339     WR16(FE_AD_REG_COMM_EXEC__A, 0x0001),
0340     WR16(FE_AG_REG_COMM_EXEC__A, 0x0001),
0341     WR16(FE_AG_REG_AG_MODE_LOP__A, 0x895E),
0342 
0343     END_OF_TABLE
0344 };
0345 
0346 u8 DRXD_InitFEB1_1[] = {
0347     WR16(B_FE_AD_REG_PD__A, 0x0000),
0348     WR16(B_FE_AD_REG_CLKNEG__A, 0x0000),
0349     WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000),
0350     WR16(B_FE_AG_REG_BGC_CGC_WRI__A, 0x0000),
0351     WR16(B_FE_AG_REG_AG_MODE_LOP__A, 0x000a),
0352     WR16(B_FE_AG_REG_IND_PD1_WRI__A, 35),
0353     WR16(B_FE_AG_REG_IND_WIN__A, 0),
0354     WR16(B_FE_AG_REG_IND_THD_LOL__A, 8),
0355     WR16(B_FE_AG_REG_IND_THD_HIL__A, 8),
0356     WR16(B_FE_CF_REG_IMP_VAL__A, 1),
0357     WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7),
0358     END_OF_TABLE
0359 };
0360 
0361     /* with PGA */
0362 /*      WR16(B_FE_AG_REG_AG_PGA_MODE__A   , 0x0000, 0x0000); */
0363        /* without PGA */
0364 /*      WR16(B_FE_AG_REG_AG_PGA_MODE__A   ,
0365          B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/
0366                                          /*   WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */
0367 /*   WR16(B_FE_AG_REG_AG_PWD__A    ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
0368 
0369 u8 DRXD_InitFEB1_2[] = {
0370     WR16(B_FE_COMM_EXEC__A, 0x0001),
0371 
0372     /* RF-AGC setup */
0373     WR16(B_FE_AG_REG_PDA_AUR_CNT__A, 0x0C),
0374     WR16(B_FE_AG_REG_PDC_SET_LVL__A, 0x01),
0375     WR16(B_FE_AG_REG_PDC_FLA_RGN__A, 0x02),
0376     WR16(B_FE_AG_REG_PDC_FLA_STP__A, 0xFFFF),
0377     WR16(B_FE_AG_REG_PDC_SLO_STP__A, 0xFFFF),
0378     WR16(B_FE_AG_REG_PDC_MAX__A, 0x02),
0379     WR16(B_FE_AG_REG_TGA_AUR_CNT__A, 0x0C),
0380     WR16(B_FE_AG_REG_TGC_SET_LVL__A, 0x22),
0381     WR16(B_FE_AG_REG_TGC_FLA_RGN__A, 0x15),
0382     WR16(B_FE_AG_REG_TGC_FLA_STP__A, 0x01),
0383     WR16(B_FE_AG_REG_TGC_SLO_STP__A, 0x0A),
0384 
0385     WR16(B_FE_CU_REG_DIV_NFC_CLP__A, 0),
0386     WR16(B_FE_CU_REG_CTR_NFC_OCR__A, 25000),
0387     WR16(B_FE_CU_REG_CTR_NFC_ICR__A, 1),
0388     END_OF_TABLE
0389 };
0390 
0391 u8 DRXD_InitCPA2[] = {
0392     WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2),
0393     0x07, 0x00,     /* CP_REG_BR_SPL_OFFSET__A  */
0394     0x0A, 0x00,     /* CP_REG_BR_STR_DEL__A     */
0395 
0396     WRBLOCK(CP_REG_RT_ANG_INC0__A, 4),
0397     0x00, 0x00,     /* CP_REG_RT_ANG_INC0__A    */
0398     0x00, 0x00,     /* CP_REG_RT_ANG_INC1__A    */
0399     0x03, 0x00,     /* CP_REG_RT_DETECT_ENA__A  */
0400     0x03, 0x00,     /* CP_REG_RT_DETECT_TRH__A  */
0401 
0402     WRBLOCK(CP_REG_AC_NEXP_OFFS__A, 5),
0403     0x32, 0x00,     /* CP_REG_AC_NEXP_OFFS__A   */
0404     0x62, 0x00,     /* CP_REG_AC_AVER_POW__A    */
0405     0x82, 0x00,     /* CP_REG_AC_MAX_POW__A     */
0406     0x26, 0x00,     /* CP_REG_AC_WEIGHT_MAN__A  */
0407     0x0F, 0x00,     /* CP_REG_AC_WEIGHT_EXP__A  */
0408 
0409     WRBLOCK(CP_REG_AC_AMP_MODE__A, 2),
0410     0x02, 0x00,     /* CP_REG_AC_AMP_MODE__A    */
0411     0x01, 0x00,     /* CP_REG_AC_AMP_FIX__A     */
0412 
0413     WR16(CP_REG_INTERVAL__A, 0x0005),
0414     WR16(CP_REG_RT_EXP_MARG__A, 0x0004),
0415     WR16(CP_REG_AC_ANG_MODE__A, 0x0003),
0416 
0417     WR16(CP_REG_COMM_EXEC__A, 0x0001),
0418     END_OF_TABLE
0419 };
0420 
0421 u8 DRXD_InitCPB1[] = {
0422     WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008),
0423     WR16(B_CP_COMM_EXEC__A, 0x0001),
0424     END_OF_TABLE
0425 };
0426 
0427 u8 DRXD_InitCEA2[] = {
0428     WRBLOCK(CE_REG_AVG_POW__A, 4),
0429     0x62, 0x00,     /* CE_REG_AVG_POW__A        */
0430     0x78, 0x00,     /* CE_REG_MAX_POW__A        */
0431     0x62, 0x00,     /* CE_REG_ATT__A            */
0432     0x17, 0x00,     /* CE_REG_NRED__A           */
0433 
0434     WRBLOCK(CE_REG_NE_ERR_SELECT__A, 2),
0435     0x07, 0x00,     /* CE_REG_NE_ERR_SELECT__A  */
0436     0xEB, 0xFF,     /* CE_REG_NE_TD_CAL__A      */
0437 
0438     WRBLOCK(CE_REG_NE_MIXAVG__A, 2),
0439     0x06, 0x00,     /* CE_REG_NE_MIXAVG__A      */
0440     0x00, 0x00,     /* CE_REG_NE_NUPD_OFS__A    */
0441 
0442     WRBLOCK(CE_REG_PE_NEXP_OFFS__A, 2),
0443     0x00, 0x00,     /* CE_REG_PE_NEXP_OFFS__A   */
0444     0x00, 0x00,     /* CE_REG_PE_TIMESHIFT__A   */
0445 
0446     WRBLOCK(CE_REG_TP_A0_TAP_NEW__A, 3),
0447     0x00, 0x01,     /* CE_REG_TP_A0_TAP_NEW__A       */
0448     0x01, 0x00,     /* CE_REG_TP_A0_TAP_NEW_VALID__A */
0449     0x0E, 0x00,     /* CE_REG_TP_A0_MU_LMS_STEP__A   */
0450 
0451     WRBLOCK(CE_REG_TP_A1_TAP_NEW__A, 3),
0452     0x00, 0x00,     /* CE_REG_TP_A1_TAP_NEW__A        */
0453     0x01, 0x00,     /* CE_REG_TP_A1_TAP_NEW_VALID__A  */
0454     0x0A, 0x00,     /* CE_REG_TP_A1_MU_LMS_STEP__A    */
0455 
0456     WRBLOCK(CE_REG_FI_SHT_INCR__A, 2),
0457     0x12, 0x00,     /* CE_REG_FI_SHT_INCR__A          */
0458     0x0C, 0x00,     /* CE_REG_FI_EXP_NORM__A          */
0459 
0460     WRBLOCK(CE_REG_IR_INPUTSEL__A, 3),
0461     0x00, 0x00,     /* CE_REG_IR_INPUTSEL__A          */
0462     0x00, 0x00,     /* CE_REG_IR_STARTPOS__A          */
0463     0xFF, 0x00,     /* CE_REG_IR_NEXP_THRES__A        */
0464 
0465     WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000),
0466 
0467     END_OF_TABLE
0468 };
0469 
0470 u8 DRXD_InitCEB1[] = {
0471     WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001),
0472     WR16(B_CE_REG_FR_PM_SET__A, 0x000D),
0473 
0474     END_OF_TABLE
0475 };
0476 
0477 u8 DRXD_InitEQA2[] = {
0478     WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4),
0479     0x1E, 0x00,     /* EQ_REG_OT_QNT_THRES0__A        */
0480     0x1F, 0x00,     /* EQ_REG_OT_QNT_THRES1__A        */
0481     0x06, 0x00,     /* EQ_REG_OT_CSI_STEP__A          */
0482     0x02, 0x00,     /* EQ_REG_OT_CSI_OFFSET__A        */
0483 
0484     WR16(EQ_REG_TD_REQ_SMB_CNT__A, 0x0200),
0485     WR16(EQ_REG_IS_CLIP_EXP__A, 0x001F),
0486     WR16(EQ_REG_SN_OFFSET__A, (u16) (-7)),
0487     WR16(EQ_REG_RC_SEL_CAR__A, 0x0002),
0488     WR16(EQ_REG_COMM_EXEC__A, 0x0001),
0489     END_OF_TABLE
0490 };
0491 
0492 u8 DRXD_InitEQB1[] = {
0493     WR16(B_EQ_REG_COMM_EXEC__A, 0x0001),
0494     END_OF_TABLE
0495 };
0496 
0497 u8 DRXD_ResetECRAM[] = {
0498     /* Reset packet sync bytes in EC_VD ram */
0499     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
0500     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
0501     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
0502     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
0503     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
0504     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
0505     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
0506     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
0507     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
0508     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
0509     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
0510 
0511     /* Reset packet sync bytes in EC_RS ram */
0512     WR16(EC_RS_EC_RAM__A, 0x0000),
0513     WR16(EC_RS_EC_RAM__A + 204, 0x0000),
0514     END_OF_TABLE
0515 };
0516 
0517 u8 DRXD_InitECA2[] = {
0518     WRBLOCK(EC_SB_REG_CSI_HI__A, 6),
0519     0x1F, 0x00,     /* EC_SB_REG_CSI_HI__A            */
0520     0x1E, 0x00,     /* EC_SB_REG_CSI_LO__A            */
0521     0x01, 0x00,     /* EC_SB_REG_SMB_TGL__A           */
0522     0x7F, 0x00,     /* EC_SB_REG_SNR_HI__A            */
0523     0x7F, 0x00,     /* EC_SB_REG_SNR_MID__A           */
0524     0x7F, 0x00,     /* EC_SB_REG_SNR_LO__A            */
0525 
0526     WRBLOCK(EC_RS_REG_REQ_PCK_CNT__A, 2),
0527     0x00, 0x10,     /* EC_RS_REG_REQ_PCK_CNT__A       */
0528     DATA16(EC_RS_REG_VAL_PCK),  /* EC_RS_REG_VAL__A               */
0529 
0530     WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
0531     0x03, 0x00,     /* EC_OC_REG_TMD_TOP_MODE__A      */
0532     0xF4, 0x01,     /* EC_OC_REG_TMD_TOP_CNT__A       */
0533     0xC0, 0x03,     /* EC_OC_REG_TMD_HIL_MAR__A       */
0534     0x40, 0x00,     /* EC_OC_REG_TMD_LOL_MAR__A       */
0535     0x03, 0x00,     /* EC_OC_REG_TMD_CUR_CNT__A       */
0536 
0537     WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
0538     0x06, 0x00,     /* EC_OC_REG_AVR_ASH_CNT__A       */
0539     0x02, 0x00,     /* EC_OC_REG_AVR_BSH_CNT__A       */
0540 
0541     WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
0542     0x07, 0x00,     /* EC_OC_REG_RCN_MODE__A          */
0543     0x00, 0x00,     /* EC_OC_REG_RCN_CRA_LOP__A       */
0544     0xc0, 0x00,     /* EC_OC_REG_RCN_CRA_HIP__A       */
0545     0x00, 0x10,     /* EC_OC_REG_RCN_CST_LOP__A       */
0546     0x00, 0x00,     /* EC_OC_REG_RCN_CST_HIP__A       */
0547     0xFF, 0x01,     /* EC_OC_REG_RCN_SET_LVL__A       */
0548     0x0D, 0x00,     /* EC_OC_REG_RCN_GAI_LVL__A       */
0549 
0550     WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
0551     0x00, 0x00,     /* EC_OC_REG_RCN_CLP_LOP__A       */
0552     0xC0, 0x00,     /* EC_OC_REG_RCN_CLP_HIP__A       */
0553 
0554     WR16(EC_SB_REG_CSI_OFS__A, 0x0001),
0555     WR16(EC_VD_REG_FORCE__A, 0x0002),
0556     WR16(EC_VD_REG_REQ_SMB_CNT__A, 0x0001),
0557     WR16(EC_VD_REG_RLK_ENA__A, 0x0001),
0558     WR16(EC_OD_REG_SYNC__A, 0x0664),
0559     WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
0560     WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
0561     /* Output zero on monitorbus pads, power saving */
0562     WR16(EC_OC_REG_OCR_MON_UOS__A,
0563          (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
0564           EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
0565           EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
0566           EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
0567           EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
0568           EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
0569           EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
0570           EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
0571           EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
0572           EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
0573           EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
0574           EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
0575     WR16(EC_OC_REG_OCR_MON_WRI__A,
0576          EC_OC_REG_OCR_MON_WRI_INIT),
0577 
0578 /*   CHK_ERROR(ResetECRAM(demod)); */
0579     /* Reset packet sync bytes in EC_VD ram */
0580     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
0581     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
0582     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
0583     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
0584     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
0585     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
0586     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
0587     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
0588     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
0589     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
0590     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
0591 
0592     /* Reset packet sync bytes in EC_RS ram */
0593     WR16(EC_RS_EC_RAM__A, 0x0000),
0594     WR16(EC_RS_EC_RAM__A + 204, 0x0000),
0595 
0596     WR16(EC_SB_REG_COMM_EXEC__A, 0x0001),
0597     WR16(EC_VD_REG_COMM_EXEC__A, 0x0001),
0598     WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
0599     WR16(EC_RS_REG_COMM_EXEC__A, 0x0001),
0600     END_OF_TABLE
0601 };
0602 
0603 u8 DRXD_InitECB1[] = {
0604     WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001),
0605     WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001),
0606     WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001),
0607     WR16(B_EC_SB_REG_CSI_LO__A, 0x000c),
0608     WR16(B_EC_SB_REG_CSI_HI__A, 0x0018),
0609     WR16(B_EC_SB_REG_SNR_HI__A, 0x007f),
0610     WR16(B_EC_SB_REG_SNR_MID__A, 0x007f),
0611     WR16(B_EC_SB_REG_SNR_LO__A, 0x007f),
0612 
0613     WR16(B_EC_OC_REG_DTO_CLKMODE__A, 0x0002),
0614     WR16(B_EC_OC_REG_DTO_PER__A, 0x0006),
0615     WR16(B_EC_OC_REG_DTO_BUR__A, 0x0001),
0616     WR16(B_EC_OC_REG_RCR_CLKMODE__A, 0x0000),
0617     WR16(B_EC_OC_REG_RCN_GAI_LVL__A, 0x000D),
0618     WR16(B_EC_OC_REG_OC_MPG_SIO__A, 0x0000),
0619 
0620     /* Needed because shadow registers do not have correct default value */
0621     WR16(B_EC_OC_REG_RCN_CST_LOP__A, 0x1000),
0622     WR16(B_EC_OC_REG_RCN_CST_HIP__A, 0x0000),
0623     WR16(B_EC_OC_REG_RCN_CRA_LOP__A, 0x0000),
0624     WR16(B_EC_OC_REG_RCN_CRA_HIP__A, 0x00C0),
0625     WR16(B_EC_OC_REG_RCN_CLP_LOP__A, 0x0000),
0626     WR16(B_EC_OC_REG_RCN_CLP_HIP__A, 0x00C0),
0627     WR16(B_EC_OC_REG_DTO_INC_LOP__A, 0x0000),
0628     WR16(B_EC_OC_REG_DTO_INC_HIP__A, 0x00C0),
0629 
0630     WR16(B_EC_OD_REG_SYNC__A, 0x0664),
0631     WR16(B_EC_RS_REG_REQ_PCK_CNT__A, 0x1000),
0632 
0633 /*   CHK_ERROR(ResetECRAM(demod)); */
0634     /* Reset packet sync bytes in EC_VD ram */
0635     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
0636     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
0637     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
0638     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
0639     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
0640     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
0641     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
0642     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
0643     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
0644     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
0645     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
0646 
0647     /* Reset packet sync bytes in EC_RS ram */
0648     WR16(EC_RS_EC_RAM__A, 0x0000),
0649     WR16(EC_RS_EC_RAM__A + 204, 0x0000),
0650 
0651     WR16(B_EC_SB_REG_COMM_EXEC__A, 0x0001),
0652     WR16(B_EC_VD_REG_COMM_EXEC__A, 0x0001),
0653     WR16(B_EC_OD_REG_COMM_EXEC__A, 0x0001),
0654     WR16(B_EC_RS_REG_COMM_EXEC__A, 0x0001),
0655     END_OF_TABLE
0656 };
0657 
0658 u8 DRXD_ResetECA2[] = {
0659 
0660     WR16(EC_OC_REG_COMM_EXEC__A, 0x0000),
0661     WR16(EC_OD_REG_COMM_EXEC__A, 0x0000),
0662 
0663     WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
0664     0x03, 0x00,     /* EC_OC_REG_TMD_TOP_MODE__A      */
0665     0xF4, 0x01,     /* EC_OC_REG_TMD_TOP_CNT__A       */
0666     0xC0, 0x03,     /* EC_OC_REG_TMD_HIL_MAR__A       */
0667     0x40, 0x00,     /* EC_OC_REG_TMD_LOL_MAR__A       */
0668     0x03, 0x00,     /* EC_OC_REG_TMD_CUR_CNT__A       */
0669 
0670     WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
0671     0x06, 0x00,     /* EC_OC_REG_AVR_ASH_CNT__A       */
0672     0x02, 0x00,     /* EC_OC_REG_AVR_BSH_CNT__A       */
0673 
0674     WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
0675     0x07, 0x00,     /* EC_OC_REG_RCN_MODE__A          */
0676     0x00, 0x00,     /* EC_OC_REG_RCN_CRA_LOP__A       */
0677     0xc0, 0x00,     /* EC_OC_REG_RCN_CRA_HIP__A       */
0678     0x00, 0x10,     /* EC_OC_REG_RCN_CST_LOP__A       */
0679     0x00, 0x00,     /* EC_OC_REG_RCN_CST_HIP__A       */
0680     0xFF, 0x01,     /* EC_OC_REG_RCN_SET_LVL__A       */
0681     0x0D, 0x00,     /* EC_OC_REG_RCN_GAI_LVL__A       */
0682 
0683     WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
0684     0x00, 0x00,     /* EC_OC_REG_RCN_CLP_LOP__A       */
0685     0xC0, 0x00,     /* EC_OC_REG_RCN_CLP_HIP__A       */
0686 
0687     WR16(EC_OD_REG_SYNC__A, 0x0664),
0688     WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
0689     WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
0690     /* Output zero on monitorbus pads, power saving */
0691     WR16(EC_OC_REG_OCR_MON_UOS__A,
0692          (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
0693           EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
0694           EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
0695           EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
0696           EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
0697           EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
0698           EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
0699           EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
0700           EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
0701           EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
0702           EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
0703           EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
0704     WR16(EC_OC_REG_OCR_MON_WRI__A,
0705          EC_OC_REG_OCR_MON_WRI_INIT),
0706 
0707 /*   CHK_ERROR(ResetECRAM(demod)); */
0708     /* Reset packet sync bytes in EC_VD ram */
0709     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
0710     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
0711     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
0712     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
0713     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
0714     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
0715     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
0716     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
0717     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
0718     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
0719     WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
0720 
0721     /* Reset packet sync bytes in EC_RS ram */
0722     WR16(EC_RS_EC_RAM__A, 0x0000),
0723     WR16(EC_RS_EC_RAM__A + 204, 0x0000),
0724 
0725     WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
0726     END_OF_TABLE
0727 };
0728 
0729 u8 DRXD_InitSC[] = {
0730     WR16(SC_COMM_EXEC__A, 0),
0731     WR16(SC_COMM_STATE__A, 0),
0732 
0733 #ifdef COMPILE_FOR_QT
0734     WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100),
0735 #endif
0736 
0737     /* SC is not started, this is done in SetChannels() */
0738     END_OF_TABLE
0739 };
0740 
0741 /* Diversity settings */
0742 
0743 u8 DRXD_InitDiversityFront[] = {
0744     /* Start demod ********* RF in , diversity out **************************** */
0745     WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
0746          B_SC_RA_RAM_CONFIG_FREQSCAN__M),
0747 
0748     WR16(B_SC_RA_RAM_LC_ABS_2K__A, 0x7),
0749     WR16(B_SC_RA_RAM_LC_ABS_8K__A, 0x7),
0750     WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
0751     WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
0752     WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
0753     WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
0754     WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
0755     WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
0756 
0757     WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
0758     WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
0759     WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
0760     WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
0761     WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
0762     WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
0763 
0764     WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
0765     WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
0766     WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
0767     WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
0768     WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
0769 
0770     WR16(B_CC_REG_DIVERSITY__A, 0x0001),
0771     WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010),
0772     WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |
0773          B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
0774 
0775     /*    0x2a ), *//* CE to PASS mux */
0776 
0777     END_OF_TABLE
0778 };
0779 
0780 u8 DRXD_InitDiversityEnd[] = {
0781     /* End demod *********** combining RF in and diversity in, MPEG TS out **** */
0782     /* disable near/far; switch on timing slave mode */
0783     WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
0784          B_SC_RA_RAM_CONFIG_FREQSCAN__M |
0785          B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M |
0786          B_SC_RA_RAM_CONFIG_SLAVE__M |
0787          B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M
0788 /* MV from CtrlDiversity */
0789         ),
0790 #ifdef DRXDDIV_SRMM_SLAVING
0791     WR16(SC_RA_RAM_LC_ABS_2K__A, 0x3c7),
0792     WR16(SC_RA_RAM_LC_ABS_8K__A, 0x3c7),
0793 #else
0794     WR16(SC_RA_RAM_LC_ABS_2K__A, 0x7),
0795     WR16(SC_RA_RAM_LC_ABS_8K__A, 0x7),
0796 #endif
0797 
0798     WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
0799     WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
0800     WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
0801     WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
0802     WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
0803     WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
0804 
0805     WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
0806     WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
0807     WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
0808     WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
0809     WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
0810     WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
0811 
0812     WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
0813     WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
0814     WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
0815     WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
0816     WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
0817 
0818     WR16(B_CC_REG_DIVERSITY__A, 0x0001),
0819     END_OF_TABLE
0820 };
0821 
0822 u8 DRXD_DisableDiversity[] = {
0823     WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE),
0824     WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE),
0825     WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A,
0826          B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE),
0827     WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A,
0828          B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE),
0829     WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A,
0830          B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE),
0831     WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A,
0832          B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE),
0833     WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A,
0834          B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE),
0835     WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A,
0836          B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE),
0837 
0838     WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A,
0839          B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE),
0840     WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A,
0841          B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE),
0842     WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A,
0843          B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE),
0844     WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A,
0845          B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE),
0846     WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A,
0847          B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE),
0848     WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A,
0849          B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE),
0850 
0851     WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE),
0852     WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE),
0853     WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE),
0854     WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE),
0855     WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE),
0856 
0857     WR16(B_CC_REG_DIVERSITY__A, 0x0000),
0858     WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT), /* combining disabled */
0859 
0860     END_OF_TABLE
0861 };
0862 
0863 u8 DRXD_StartDiversityFront[] = {
0864     /* Start demod, RF in and diversity out, no combining */
0865     WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),
0866     WR16(B_FE_AD_REG_FDB_IN__A, 0x0),
0867     WR16(B_FE_AD_REG_INVEXT__A, 0x0),
0868     WR16(B_EQ_REG_COMM_MB__A, 0x12),    /* EQ to MB out */
0869     WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |    /* CE to PASS mux */
0870          B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
0871 
0872     WR16(SC_RA_RAM_ECHO_SHIFT_LIM__A, 2),
0873 
0874     END_OF_TABLE
0875 };
0876 
0877 u8 DRXD_StartDiversityEnd[] = {
0878     /* End demod, combining RF in and diversity in, MPEG TS out */
0879     WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),  /* disable impulse noise cruncher */
0880     WR16(B_FE_AD_REG_INVEXT__A, 0x0),   /* clock inversion (for sohard board) */
0881     WR16(B_CP_REG_BR_STR_DEL__A, 10),   /* apparently no mb delay matching is best */
0882 
0883     WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON |   /* org = 0x81 combining enabled */
0884          B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
0885          B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC),
0886 
0887     END_OF_TABLE
0888 };
0889 
0890 u8 DRXD_DiversityDelay8MHZ[] = {
0891     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50),
0892     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50),
0893     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50),
0894     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 800 - 50),
0895     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50),
0896     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50),
0897     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4800 - 50),
0898     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 4000 - 50),
0899     END_OF_TABLE
0900 };
0901 
0902 u8 DRXD_DiversityDelay6MHZ[] =  /* also used ok for 7 MHz */
0903 {
0904     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50),
0905     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50),
0906     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 900 - 50),
0907     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 600 - 50),
0908     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50),
0909     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50),
0910     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4500 - 50),
0911     WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 3500 - 50),
0912     END_OF_TABLE
0913 };
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