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0001 0002 /* 0003 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. 0004 All rights reserved. 0005 0006 Redistribution and use in source and binary forms, with or without 0007 modification, are permitted provided that the following conditions are met: 0008 0009 * Redistributions of source code must retain the above copyright notice, 0010 this list of conditions and the following disclaimer. 0011 * Redistributions in binary form must reproduce the above copyright notice, 0012 this list of conditions and the following disclaimer in the documentation 0013 and/or other materials provided with the distribution. 0014 * Neither the name of Trident Microsystems nor Hauppauge Computer Works 0015 nor the names of its contributors may be used to endorse or promote 0016 products derived from this software without specific prior written 0017 permission. 0018 0019 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 0020 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 0021 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 0022 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 0023 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 0024 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 0025 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 0026 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 0027 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 0028 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 0029 POSSIBILITY OF SUCH DAMAGE. 0030 0031 DRXJ specific header file 0032 0033 Authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen 0034 */ 0035 0036 #ifndef __DRXJ_H__ 0037 #define __DRXJ_H__ 0038 /*------------------------------------------------------------------------- 0039 INCLUDES 0040 -------------------------------------------------------------------------*/ 0041 0042 #include "drx_driver.h" 0043 #include "drx_dap_fasi.h" 0044 0045 /* Check DRX-J specific dap condition */ 0046 /* Multi master mode and short addr format only will not work. 0047 RMW, CRC reset, broadcast and switching back to single master mode 0048 cannot be done with short addr only in multi master mode. */ 0049 #if ((DRXDAP_SINGLE_MASTER == 0) && (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)) 0050 #error "Multi master mode and short addressing only is an illegal combination" 0051 *; /* Generate a fatal compiler error to make sure it stops here, 0052 this is necessary because not all compilers stop after a #error. */ 0053 #endif 0054 0055 /*------------------------------------------------------------------------- 0056 TYPEDEFS 0057 -------------------------------------------------------------------------*/ 0058 /*============================================================================*/ 0059 /*============================================================================*/ 0060 /*== code support ============================================================*/ 0061 /*============================================================================*/ 0062 /*============================================================================*/ 0063 0064 /*============================================================================*/ 0065 /*============================================================================*/ 0066 /*== SCU cmd if =============================================================*/ 0067 /*============================================================================*/ 0068 /*============================================================================*/ 0069 0070 struct drxjscu_cmd { 0071 u16 command; 0072 /*< Command number */ 0073 u16 parameter_len; 0074 /*< Data length in byte */ 0075 u16 result_len; 0076 /*< result length in byte */ 0077 u16 *parameter; 0078 /*< General purpose param */ 0079 u16 *result; 0080 /*< General purpose param */}; 0081 0082 /*============================================================================*/ 0083 /*============================================================================*/ 0084 /*== CTRL CFG related data structures ========================================*/ 0085 /*============================================================================*/ 0086 /*============================================================================*/ 0087 0088 /* extra intermediate lock state for VSB,QAM,NTSC */ 0089 #define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1) 0090 0091 /* OOB lock states */ 0092 #define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */ 0093 #define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */ 0094 0095 /* Intermediate powermodes for DRXJ */ 0096 #define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8 0097 #define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9 0098 #define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10 0099 0100 /* supstition for GPIO FNC mux */ 0101 #define APP_O (0x0000) 0102 0103 /*#define DRX_CTRL_BASE (0x0000)*/ 0104 0105 #define DRXJ_CTRL_CFG_BASE (0x1000) 0106 enum drxj_cfg_type { 0107 DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE, 0108 DRXJ_CFG_AGC_IF, 0109 DRXJ_CFG_AGC_INTERNAL, 0110 DRXJ_CFG_PRE_SAW, 0111 DRXJ_CFG_AFE_GAIN, 0112 DRXJ_CFG_SYMBOL_CLK_OFFSET, 0113 DRXJ_CFG_ACCUM_CR_RS_CW_ERR, 0114 DRXJ_CFG_FEC_MERS_SEQ_COUNT, 0115 DRXJ_CFG_OOB_MISC, 0116 DRXJ_CFG_SMART_ANT, 0117 DRXJ_CFG_OOB_PRE_SAW, 0118 DRXJ_CFG_VSB_MISC, 0119 DRXJ_CFG_RESET_PACKET_ERR, 0120 0121 /* ATV (FM) */ 0122 DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */ 0123 DRXJ_CFG_ATV_MISC, 0124 DRXJ_CFG_ATV_EQU_COEF, 0125 DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */ 0126 0127 DRXJ_CFG_MPEG_OUTPUT_MISC, 0128 DRXJ_CFG_HW_CFG, 0129 DRXJ_CFG_OOB_LO_POW, 0130 0131 DRXJ_CFG_MAX /* dummy, never to be used */}; 0132 0133 /* 0134 * /enum drxj_cfg_smart_ant_io * smart antenna i/o. 0135 */ 0136 enum drxj_cfg_smart_ant_io { 0137 DRXJ_SMT_ANT_OUTPUT = 0, 0138 DRXJ_SMT_ANT_INPUT 0139 }; 0140 0141 /* 0142 * /struct drxj_cfg_smart_ant * Set smart antenna. 0143 */ 0144 struct drxj_cfg_smart_ant { 0145 enum drxj_cfg_smart_ant_io io; 0146 u16 ctrl_data; 0147 }; 0148 0149 /* 0150 * /struct DRXJAGCSTATUS_t 0151 * AGC status information from the DRXJ-IQM-AF. 0152 */ 0153 struct drxj_agc_status { 0154 u16 IFAGC; 0155 u16 RFAGC; 0156 u16 digital_agc; 0157 }; 0158 0159 /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ 0160 0161 /* 0162 * /enum drxj_agc_ctrl_mode * Available AGCs modes in the DRXJ. 0163 */ 0164 enum drxj_agc_ctrl_mode { 0165 DRX_AGC_CTRL_AUTO = 0, 0166 DRX_AGC_CTRL_USER, 0167 DRX_AGC_CTRL_OFF}; 0168 0169 /* 0170 * /struct drxj_cfg_agc * Generic interface for all AGCs present on the DRXJ. 0171 */ 0172 struct drxj_cfg_agc { 0173 enum drx_standard standard; /* standard for which these settings apply */ 0174 enum drxj_agc_ctrl_mode ctrl_mode; /* off, user, auto */ 0175 u16 output_level; /* range dependent on AGC */ 0176 u16 min_output_level; /* range dependent on AGC */ 0177 u16 max_output_level; /* range dependent on AGC */ 0178 u16 speed; /* range dependent on AGC */ 0179 u16 top; /* rf-agc take over point */ 0180 u16 cut_off_current; /* rf-agc is accelerated if output current 0181 is below cut-off current */}; 0182 0183 /* DRXJ_CFG_PRE_SAW */ 0184 0185 /* 0186 * /struct drxj_cfg_pre_saw * Interface to configure pre SAW sense. 0187 */ 0188 struct drxj_cfg_pre_saw { 0189 enum drx_standard standard; /* standard to which these settings apply */ 0190 u16 reference; /* pre SAW reference value, range 0 .. 31 */ 0191 bool use_pre_saw; /* true algorithms must use pre SAW sense */}; 0192 0193 /* DRXJ_CFG_AFE_GAIN */ 0194 0195 /* 0196 * /struct drxj_cfg_afe_gain * Interface to configure gain of AFE (LNA + PGA). 0197 */ 0198 struct drxj_cfg_afe_gain { 0199 enum drx_standard standard; /* standard to which these settings apply */ 0200 u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */}; 0201 0202 /* 0203 * /struct drxjrs_errors 0204 * Available failure information in DRXJ_FEC_RS. 0205 * 0206 * Container for errors that are received in the most recently finished measurement period 0207 * 0208 */ 0209 struct drxjrs_errors { 0210 u16 nr_bit_errors; 0211 /*< no of pre RS bit errors */ 0212 u16 nr_symbol_errors; 0213 /*< no of pre RS symbol errors */ 0214 u16 nr_packet_errors; 0215 /*< no of pre RS packet errors */ 0216 u16 nr_failures; 0217 /*< no of post RS failures to decode */ 0218 u16 nr_snc_par_fail_count; 0219 /*< no of post RS bit erros */ 0220 }; 0221 0222 /* 0223 * /struct drxj_cfg_vsb_misc * symbol error rate 0224 */ 0225 struct drxj_cfg_vsb_misc { 0226 u32 symb_error; 0227 /*< symbol error rate sps */}; 0228 0229 /* 0230 * /enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. 0231 * 0232 */ 0233 enum drxj_mpeg_start_width { 0234 DRXJ_MPEG_START_WIDTH_1CLKCYC, 0235 DRXJ_MPEG_START_WIDTH_8CLKCYC}; 0236 0237 /* 0238 * /enum drxj_mpeg_output_clock_rate * Mpeg output clock rate. 0239 * 0240 */ 0241 enum drxj_mpeg_output_clock_rate { 0242 DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, 0243 DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K, 0244 DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K, 0245 DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K, 0246 DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, 0247 DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, 0248 DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K}; 0249 0250 /* 0251 * /struct DRXJCfgMisc_t 0252 * Change TEI bit of MPEG output 0253 * reverse MPEG output bit order 0254 * set MPEG output clock rate 0255 */ 0256 struct drxj_cfg_mpeg_output_misc { 0257 bool disable_tei_handling; /*< if true pass (not change) TEI bit */ 0258 bool bit_reverse_mpeg_outout; /*< if true, parallel: msb on MD0; serial: lsb out first */ 0259 enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; 0260 /*< set MPEG output clock rate that overwirtes the derived one from symbol rate */ 0261 enum drxj_mpeg_start_width mpeg_start_width; /*< set MPEG output start width */}; 0262 0263 /* 0264 * /enum drxj_xtal_freq * Supported external crystal reference frequency. 0265 */ 0266 enum drxj_xtal_freq { 0267 DRXJ_XTAL_FREQ_RSVD, 0268 DRXJ_XTAL_FREQ_27MHZ, 0269 DRXJ_XTAL_FREQ_20P25MHZ, 0270 DRXJ_XTAL_FREQ_4MHZ}; 0271 0272 /* 0273 * /enum drxj_xtal_freq * Supported external crystal reference frequency. 0274 */ 0275 enum drxji2c_speed { 0276 DRXJ_I2C_SPEED_400KBPS, 0277 DRXJ_I2C_SPEED_100KBPS}; 0278 0279 /* 0280 * /struct drxj_cfg_hw_cfg * Get hw configuration, such as crystal 0281 * reference frequency, I2C speed, etc... 0282 */ 0283 struct drxj_cfg_hw_cfg { 0284 enum drxj_xtal_freq xtal_freq; 0285 /*< crystal reference frequency */ 0286 enum drxji2c_speed i2c_speed; 0287 /*< 100 or 400 kbps */}; 0288 0289 /* 0290 * DRXJ_CFG_ATV_MISC 0291 */ 0292 struct drxj_cfg_atv_misc { 0293 s16 peak_filter; /* -8 .. 15 */ 0294 u16 noise_filter; /* 0 .. 15 */}; 0295 0296 /* 0297 * struct drxj_cfg_oob_misc */ 0298 #define DRXJ_OOB_STATE_RESET 0x0 0299 #define DRXJ_OOB_STATE_AGN_HUNT 0x1 0300 #define DRXJ_OOB_STATE_DGN_HUNT 0x2 0301 #define DRXJ_OOB_STATE_AGC_HUNT 0x3 0302 #define DRXJ_OOB_STATE_FRQ_HUNT 0x4 0303 #define DRXJ_OOB_STATE_PHA_HUNT 0x8 0304 #define DRXJ_OOB_STATE_TIM_HUNT 0x10 0305 #define DRXJ_OOB_STATE_EQU_HUNT 0x20 0306 #define DRXJ_OOB_STATE_EQT_HUNT 0x30 0307 #define DRXJ_OOB_STATE_SYNC 0x40 0308 0309 struct drxj_cfg_oob_misc { 0310 struct drxj_agc_status agc; 0311 bool eq_lock; 0312 bool sym_timing_lock; 0313 bool phase_lock; 0314 bool freq_lock; 0315 bool dig_gain_lock; 0316 bool ana_gain_lock; 0317 u8 state; 0318 }; 0319 0320 /* 0321 * Index of in array of coef 0322 */ 0323 enum drxj_cfg_oob_lo_power { 0324 DRXJ_OOB_LO_POW_MINUS0DB = 0, 0325 DRXJ_OOB_LO_POW_MINUS5DB, 0326 DRXJ_OOB_LO_POW_MINUS10DB, 0327 DRXJ_OOB_LO_POW_MINUS15DB, 0328 DRXJ_OOB_LO_POW_MAX}; 0329 0330 /* 0331 * DRXJ_CFG_ATV_EQU_COEF 0332 */ 0333 struct drxj_cfg_atv_equ_coef { 0334 s16 coef0; /* -256 .. 255 */ 0335 s16 coef1; /* -256 .. 255 */ 0336 s16 coef2; /* -256 .. 255 */ 0337 s16 coef3; /* -256 .. 255 */}; 0338 0339 /* 0340 * Index of in array of coef 0341 */ 0342 enum drxj_coef_array_index { 0343 DRXJ_COEF_IDX_MN = 0, 0344 DRXJ_COEF_IDX_FM, 0345 DRXJ_COEF_IDX_L, 0346 DRXJ_COEF_IDX_LP, 0347 DRXJ_COEF_IDX_BG, 0348 DRXJ_COEF_IDX_DK, 0349 DRXJ_COEF_IDX_I, 0350 DRXJ_COEF_IDX_MAX}; 0351 0352 /* 0353 * DRXJ_CFG_ATV_OUTPUT 0354 */ 0355 0356 /* 0357 * /enum DRXJAttenuation_t 0358 * Attenuation setting for SIF AGC. 0359 * 0360 */ 0361 enum drxjsif_attenuation { 0362 DRXJ_SIF_ATTENUATION_0DB, 0363 DRXJ_SIF_ATTENUATION_3DB, 0364 DRXJ_SIF_ATTENUATION_6DB, 0365 DRXJ_SIF_ATTENUATION_9DB}; 0366 0367 /* 0368 * /struct drxj_cfg_atv_output * SIF attenuation setting. 0369 * 0370 */ 0371 struct drxj_cfg_atv_output { 0372 bool enable_cvbs_output; /* true= enabled */ 0373 bool enable_sif_output; /* true= enabled */ 0374 enum drxjsif_attenuation sif_attenuation; 0375 }; 0376 0377 /* 0378 DRXJ_CFG_ATV_AGC_STATUS (get only) 0379 */ 0380 /* TODO : AFE interface not yet finished, subject to change */ 0381 struct drxj_cfg_atv_agc_status { 0382 u16 rf_agc_gain; /* 0 .. 877 uA */ 0383 u16 if_agc_gain; /* 0 .. 877 uA */ 0384 s16 video_agc_gain; /* -75 .. 1972 in 0.1 dB steps */ 0385 s16 audio_agc_gain; /* -4 .. 1020 in 0.1 dB steps */ 0386 u16 rf_agc_loop_gain; /* 0 .. 7 */ 0387 u16 if_agc_loop_gain; /* 0 .. 7 */ 0388 u16 video_agc_loop_gain; /* 0 .. 7 */}; 0389 0390 /*============================================================================*/ 0391 /*============================================================================*/ 0392 /*== CTRL related data structures ============================================*/ 0393 /*============================================================================*/ 0394 /*============================================================================*/ 0395 0396 /* NONE */ 0397 0398 /*============================================================================*/ 0399 /*============================================================================*/ 0400 0401 /*========================================*/ 0402 /* 0403 * /struct struct drxj_data * DRXJ specific attributes. 0404 * 0405 * Global data container for DRXJ specific data. 0406 * 0407 */ 0408 struct drxj_data { 0409 /* device capabilities (determined during drx_open()) */ 0410 bool has_lna; /*< true if LNA (aka PGA) present */ 0411 bool has_oob; /*< true if OOB supported */ 0412 bool has_ntsc; /*< true if NTSC supported */ 0413 bool has_btsc; /*< true if BTSC supported */ 0414 bool has_smatx; /*< true if mat_tx is available */ 0415 bool has_smarx; /*< true if mat_rx is available */ 0416 bool has_gpio; /*< true if GPIO is available */ 0417 bool has_irqn; /*< true if IRQN is available */ 0418 /* A1/A2/A... */ 0419 u8 mfx; /*< metal fix */ 0420 0421 /* tuner settings */ 0422 bool mirror_freq_spect_oob;/*< tuner inversion (true = tuner mirrors the signal */ 0423 0424 /* standard/channel settings */ 0425 enum drx_standard standard; /*< current standard information */ 0426 enum drx_modulation constellation; 0427 /*< current constellation */ 0428 s32 frequency; /*< center signal frequency in KHz */ 0429 enum drx_bandwidth curr_bandwidth; 0430 /*< current channel bandwidth */ 0431 enum drx_mirror mirror; /*< current channel mirror */ 0432 0433 /* signal quality information */ 0434 u32 fec_bits_desired; /*< BER accounting period */ 0435 u16 fec_vd_plen; /*< no of trellis symbols: VD SER measurement period */ 0436 u16 qam_vd_prescale; /*< Viterbi Measurement Prescale */ 0437 u16 qam_vd_period; /*< Viterbi Measurement period */ 0438 u16 fec_rs_plen; /*< defines RS BER measurement period */ 0439 u16 fec_rs_prescale; /*< ReedSolomon Measurement Prescale */ 0440 u16 fec_rs_period; /*< ReedSolomon Measurement period */ 0441 bool reset_pkt_err_acc; /*< Set a flag to reset accumulated packet error */ 0442 u16 pkt_err_acc_start; /*< Set a flag to reset accumulated packet error */ 0443 0444 /* HI configuration */ 0445 u16 hi_cfg_timing_div; /*< HI Configure() parameter 2 */ 0446 u16 hi_cfg_bridge_delay; /*< HI Configure() parameter 3 */ 0447 u16 hi_cfg_wake_up_key; /*< HI Configure() parameter 4 */ 0448 u16 hi_cfg_ctrl; /*< HI Configure() parameter 5 */ 0449 u16 hi_cfg_transmit; /*< HI Configure() parameter 6 */ 0450 0451 /* UIO configuration */ 0452 enum drxuio_mode uio_sma_rx_mode;/*< current mode of SmaRx pin */ 0453 enum drxuio_mode uio_sma_tx_mode;/*< current mode of SmaTx pin */ 0454 enum drxuio_mode uio_gpio_mode; /*< current mode of ASEL pin */ 0455 enum drxuio_mode uio_irqn_mode; /*< current mode of IRQN pin */ 0456 0457 /* IQM fs frequency shift and inversion */ 0458 u32 iqm_fs_rate_ofs; /*< frequency shifter setting after setchannel */ 0459 bool pos_image; /*< True: positive image */ 0460 /* IQM RC frequency shift */ 0461 u32 iqm_rc_rate_ofs; /*< frequency shifter setting after setchannel */ 0462 0463 /* ATV configuration */ 0464 u32 atv_cfg_changed_flags; /*< flag: flags cfg changes */ 0465 s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU0__A */ 0466 s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU1__A */ 0467 s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU2__A */ 0468 s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU3__A */ 0469 bool phase_correction_bypass;/*< flag: true=bypass */ 0470 s16 atv_top_vid_peak; /*< shadow of ATV_TOP_VID_PEAK__A */ 0471 u16 atv_top_noise_th; /*< shadow of ATV_TOP_NOISE_TH__A */ 0472 bool enable_cvbs_output; /*< flag CVBS output enable */ 0473 bool enable_sif_output; /*< flag SIF output enable */ 0474 enum drxjsif_attenuation sif_attenuation; 0475 /*< current SIF att setting */ 0476 /* Agc configuration for QAM and VSB */ 0477 struct drxj_cfg_agc qam_rf_agc_cfg; /*< qam RF AGC config */ 0478 struct drxj_cfg_agc qam_if_agc_cfg; /*< qam IF AGC config */ 0479 struct drxj_cfg_agc vsb_rf_agc_cfg; /*< vsb RF AGC config */ 0480 struct drxj_cfg_agc vsb_if_agc_cfg; /*< vsb IF AGC config */ 0481 0482 /* PGA gain configuration for QAM and VSB */ 0483 u16 qam_pga_cfg; /*< qam PGA config */ 0484 u16 vsb_pga_cfg; /*< vsb PGA config */ 0485 0486 /* Pre SAW configuration for QAM and VSB */ 0487 struct drxj_cfg_pre_saw qam_pre_saw_cfg; 0488 /*< qam pre SAW config */ 0489 struct drxj_cfg_pre_saw vsb_pre_saw_cfg; 0490 /*< qam pre SAW config */ 0491 0492 /* Version information */ 0493 char v_text[2][12]; /*< allocated text versions */ 0494 struct drx_version v_version[2]; /*< allocated versions structs */ 0495 struct drx_version_list v_list_elements[2]; 0496 /*< allocated version list */ 0497 0498 /* smart antenna configuration */ 0499 bool smart_ant_inverted; 0500 0501 /* Tracking filter setting for OOB */ 0502 u16 oob_trk_filter_cfg[8]; 0503 bool oob_power_on; 0504 0505 /* MPEG static bitrate setting */ 0506 u32 mpeg_ts_static_bitrate; /*< bitrate static MPEG output */ 0507 bool disable_te_ihandling; /*< MPEG TS TEI handling */ 0508 bool bit_reverse_mpeg_outout;/*< MPEG output bit order */ 0509 enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate; 0510 /*< MPEG output clock rate */ 0511 enum drxj_mpeg_start_width mpeg_start_width; 0512 /*< MPEG Start width */ 0513 0514 /* Pre SAW & Agc configuration for ATV */ 0515 struct drxj_cfg_pre_saw atv_pre_saw_cfg; 0516 /*< atv pre SAW config */ 0517 struct drxj_cfg_agc atv_rf_agc_cfg; /*< atv RF AGC config */ 0518 struct drxj_cfg_agc atv_if_agc_cfg; /*< atv IF AGC config */ 0519 u16 atv_pga_cfg; /*< atv pga config */ 0520 0521 u32 curr_symbol_rate; 0522 0523 /* pin-safe mode */ 0524 bool pdr_safe_mode; /*< PDR safe mode activated */ 0525 u16 pdr_safe_restore_val_gpio; 0526 u16 pdr_safe_restore_val_v_sync; 0527 u16 pdr_safe_restore_val_sma_rx; 0528 u16 pdr_safe_restore_val_sma_tx; 0529 0530 /* OOB pre-saw value */ 0531 u16 oob_pre_saw; 0532 enum drxj_cfg_oob_lo_power oob_lo_pow; 0533 0534 struct drx_aud_data aud_data; 0535 /*< audio storage */}; 0536 0537 /*------------------------------------------------------------------------- 0538 Access MACROS 0539 -------------------------------------------------------------------------*/ 0540 /* 0541 * \brief Compilable references to attributes 0542 * \param d pointer to demod instance 0543 * 0544 * Used as main reference to an attribute field. 0545 * Can be used by both macro implementation and function implementation. 0546 * These macros are defined to avoid duplication of code in macro and function 0547 * definitions that handle access of demod common or extended attributes. 0548 * 0549 */ 0550 0551 #define DRXJ_ATTR_BTSC_DETECT(d) \ 0552 (((struct drxj_data *)(d)->my_ext_attr)->aud_data.btsc_detect) 0553 0554 /*------------------------------------------------------------------------- 0555 DEFINES 0556 -------------------------------------------------------------------------*/ 0557 0558 /* 0559 * \def DRXJ_NTSC_CARRIER_FREQ_OFFSET 0560 * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 0561 * 0562 * For NTSC standard. 0563 * NTSC channels are listed by their picture carrier frequency (Fpc). 0564 * The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input. 0565 * In case the tuner module is not used the DRX-J requires that the tuner is 0566 * tuned to the centre frequency of the channel: 0567 * 0568 * Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET 0569 * 0570 */ 0571 #define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((s32)(1750)) 0572 0573 /* 0574 * \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET 0575 * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 0576 * 0577 * For PAL/SECAM - BG standard. This define is needed in case the tuner module 0578 * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). 0579 * The DRX-J requires that the tuner is tuned to: 0580 * Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET 0581 * 0582 * In case the tuner module is used the drxdriver takes care of this. 0583 * In case the tuner module is NOT used the application programmer must take 0584 * care of this. 0585 * 0586 */ 0587 #define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((s32)(2375)) 0588 0589 /* 0590 * \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET 0591 * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 0592 * 0593 * For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module 0594 * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). 0595 * The DRX-J requires that the tuner is tuned to: 0596 * Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET 0597 * 0598 * In case the tuner module is used the drxdriver takes care of this. 0599 * In case the tuner module is NOT used the application programmer must take 0600 * care of this. 0601 * 0602 */ 0603 #define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((s32)(2775)) 0604 0605 /* 0606 * \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET 0607 * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 0608 * 0609 * For PAL/SECAM - LP standard. This define is needed in case the tuner module 0610 * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). 0611 * The DRX-J requires that the tuner is tuned to: 0612 * Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET 0613 * 0614 * In case the tuner module is used the drxdriver takes care of this. 0615 * In case the tuner module is NOT used the application programmer must take 0616 * care of this. 0617 */ 0618 #define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((s32)(-3255)) 0619 0620 /* 0621 * \def DRXJ_FM_CARRIER_FREQ_OFFSET 0622 * \brief Offset from sound carrier to centre frequency in kHz, in RF domain 0623 * 0624 * For FM standard. 0625 * FM channels are listed by their sound carrier frequency (Fsc). 0626 * The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as 0627 * input. 0628 * In case the tuner module is not used the DRX-J requires that the tuner is 0629 * tuned to the Ffm frequency of the channel. 0630 * 0631 * Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET 0632 * 0633 */ 0634 #define DRXJ_FM_CARRIER_FREQ_OFFSET ((s32)(-3000)) 0635 0636 /* Revision types -------------------------------------------------------*/ 0637 0638 #define DRXJ_TYPE_ID (0x3946000DUL) 0639 0640 /* Macros ---------------------------------------------------------------*/ 0641 0642 /* Convert OOB lock status to string */ 0643 #define DRXJ_STR_OOB_LOCKSTATUS(x) ( \ 0644 (x == DRX_NEVER_LOCK) ? "Never" : \ 0645 (x == DRX_NOT_LOCKED) ? "No" : \ 0646 (x == DRX_LOCKED) ? "Locked" : \ 0647 (x == DRX_LOCK_STATE_1) ? "AGC lock" : \ 0648 (x == DRX_LOCK_STATE_2) ? "sync lock" : \ 0649 "(Invalid)") 0650 0651 #endif /* __DRXJ_H__ */
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