media/dvb-frontends/dibx000_common.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef DIBX000_COMMON_H
0003 #define DIBX000_COMMON_H
0004
0005 enum dibx000_i2c_interface {
0006     DIBX000_I2C_INTERFACE_TUNER = 0,
0007     DIBX000_I2C_INTERFACE_GPIO_1_2 = 1,
0008     DIBX000_I2C_INTERFACE_GPIO_3_4 = 2,
0009     DIBX000_I2C_INTERFACE_GPIO_6_7 = 3
0010 };
0011
0012 struct dibx000_i2c_master {
0013 #define DIB3000MC 1
0014 #define DIB7000   2
0015 #define DIB7000P  11
0016 #define DIB7000MC 12
0017 #define DIB8000   13
0018     u16 device_rev;
0019
0020     enum dibx000_i2c_interface selected_interface;
0021
0022 /*  struct i2c_adapter  tuner_i2c_adap; */
0023     struct i2c_adapter gated_tuner_i2c_adap;
0024     struct i2c_adapter master_i2c_adap_gpio12;
0025     struct i2c_adapter master_i2c_adap_gpio34;
0026     struct i2c_adapter master_i2c_adap_gpio67;
0027
0028     struct i2c_adapter *i2c_adap;
0029     u8 i2c_addr;
0030
0031     u16 base_reg;
0032
0033     /* for the I2C transfer */
0034     struct i2c_msg msg[34];
0035     u8 i2c_write_buffer[8];
0036     u8 i2c_read_buffer[2];
0037     struct mutex i2c_buffer_lock;
0038 };
0039
0040 extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst,
0041                     u16 device_rev, struct i2c_adapter *i2c_adap,
0042                     u8 i2c_addr);
0043 extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master
0044                             *mst,
0045                             enum dibx000_i2c_interface
0046                             intf, int gating);
0047 extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
0048 extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst);
0049 extern int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed);
0050
0051 #define BAND_LBAND 0x01
0052 #define BAND_UHF   0x02
0053 #define BAND_VHF   0x04
0054 #define BAND_SBAND 0x08
0055 #define BAND_FM    0x10
0056 #define BAND_CBAND 0x20
0057
0058 #define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \
0059                                     (freq_kHz) <= 115000 ? BAND_FM : \
0060                                     (freq_kHz) <= 250000 ? BAND_VHF : \
0061                                     (freq_kHz) <= 863000 ? BAND_UHF : \
0062                                     (freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND )
0063
0064 struct dibx000_agc_config {
0065     /* defines the capabilities of this AGC-setting - using the BAND_-defines */
0066     u8 band_caps;
0067
0068     u16 setup;
0069
0070     u16 inv_gain;
0071     u16 time_stabiliz;
0072
0073     u8 alpha_level;
0074     u16 thlock;
0075
0076     u8 wbd_inv;
0077     u16 wbd_ref;
0078     u8 wbd_sel;
0079     u8 wbd_alpha;
0080
0081     u16 agc1_max;
0082     u16 agc1_min;
0083     u16 agc2_max;
0084     u16 agc2_min;
0085
0086     u8 agc1_pt1;
0087     u8 agc1_pt2;
0088     u8 agc1_pt3;
0089
0090     u8 agc1_slope1;
0091     u8 agc1_slope2;
0092
0093     u8 agc2_pt1;
0094     u8 agc2_pt2;
0095
0096     u8 agc2_slope1;
0097     u8 agc2_slope2;
0098
0099     u8 alpha_mant;
0100     u8 alpha_exp;
0101
0102     u8 beta_mant;
0103     u8 beta_exp;
0104
0105     u8 perform_agc_softsplit;
0106
0107     struct {
0108         u16 min;
0109         u16 max;
0110         u16 min_thres;
0111         u16 max_thres;
0112     } split;
0113 };
0114
0115 struct dibx000_bandwidth_config {
0116     u32 internal;
0117     u32 sampling;
0118
0119     u8 pll_prediv;
0120     u8 pll_ratio;
0121     u8 pll_range;
0122     u8 pll_reset;
0123     u8 pll_bypass;
0124
0125     u8 enable_refdiv;
0126     u8 bypclk_div;
0127     u8 IO_CLK_en_core;
0128     u8 ADClkSrc;
0129     u8 modulo;
0130
0131     u16 sad_cfg;
0132
0133     u32 ifreq;
0134     u32 timf;
0135
0136     u32 xtal_hz;
0137 };
0138
0139 enum dibx000_adc_states {
0140     DIBX000_SLOW_ADC_ON = 0,
0141     DIBX000_SLOW_ADC_OFF,
0142     DIBX000_ADC_ON,
0143     DIBX000_ADC_OFF,
0144     DIBX000_VBG_ENABLE,
0145     DIBX000_VBG_DISABLE,
0146 };
0147
0148 #define BANDWIDTH_TO_KHZ(v) ((v) / 1000)
0149 #define BANDWIDTH_TO_HZ(v)  ((v) * 1000)
0150
0151 /* Chip output mode. */
0152 #define OUTMODE_HIGH_Z              0
0153 #define OUTMODE_MPEG2_PAR_GATED_CLK 1
0154 #define OUTMODE_MPEG2_PAR_CONT_CLK  2
0155 #define OUTMODE_MPEG2_SERIAL        7
0156 #define OUTMODE_DIVERSITY           4
0157 #define OUTMODE_MPEG2_FIFO          5
0158 #define OUTMODE_ANALOG_ADC          6
0159
0160 #define INPUT_MODE_OFF                0x11
0161 #define INPUT_MODE_DIVERSITY          0x12
0162 #define INPUT_MODE_MPEG               0x13
0163
0164 enum frontend_tune_state {
0165     CT_TUNER_START = 10,
0166     CT_TUNER_STEP_0,
0167     CT_TUNER_STEP_1,
0168     CT_TUNER_STEP_2,
0169     CT_TUNER_STEP_3,
0170     CT_TUNER_STEP_4,
0171     CT_TUNER_STEP_5,
0172     CT_TUNER_STEP_6,
0173     CT_TUNER_STEP_7,
0174     CT_TUNER_STOP,
0175
0176     CT_AGC_START = 20,
0177     CT_AGC_STEP_0,
0178     CT_AGC_STEP_1,
0179     CT_AGC_STEP_2,
0180     CT_AGC_STEP_3,
0181     CT_AGC_STEP_4,
0182     CT_AGC_STOP,
0183
0184     CT_DEMOD_START = 30,
0185     CT_DEMOD_STEP_1,
0186     CT_DEMOD_STEP_2,
0187     CT_DEMOD_STEP_3,
0188     CT_DEMOD_STEP_4,
0189     CT_DEMOD_STEP_5,
0190     CT_DEMOD_STEP_6,
0191     CT_DEMOD_STEP_7,
0192     CT_DEMOD_STEP_8,
0193     CT_DEMOD_STEP_9,
0194     CT_DEMOD_STEP_10,
0195     CT_DEMOD_STEP_11,
0196     CT_DEMOD_SEARCH_NEXT = 51,
0197     CT_DEMOD_STEP_LOCKED,
0198     CT_DEMOD_STOP,
0199
0200     CT_DONE = 100,
0201     CT_SHUTDOWN,
0202
0203 };
0204
0205 struct dvb_frontend_parametersContext {
0206 #define CHANNEL_STATUS_PARAMETERS_UNKNOWN   0x01
0207 #define CHANNEL_STATUS_PARAMETERS_SET       0x02
0208     u8 status;
0209     u32 tune_time_estimation[2];
0210     s32 tps_available;
0211     u16 tps[9];
0212 };
0213
0214 #define FE_STATUS_TUNE_FAILED          0
0215 #define FE_STATUS_TUNE_TIMED_OUT      -1
0216 #define FE_STATUS_TUNE_TIME_TOO_SHORT -2
0217 #define FE_STATUS_TUNE_PENDING        -3
0218 #define FE_STATUS_STD_SUCCESS         -4
0219 #define FE_STATUS_FFT_SUCCESS         -5
0220 #define FE_STATUS_DEMOD_SUCCESS       -6
0221 #define FE_STATUS_LOCKED              -7
0222 #define FE_STATUS_DATA_LOCKED         -8
0223
0224 #define FE_CALLBACK_TIME_NEVER 0xffffffff
0225
0226 #define DATA_BUS_ACCESS_MODE_8BIT                 0x01
0227 #define DATA_BUS_ACCESS_MODE_16BIT                0x02
0228 #define DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT 0x10
0229
0230 struct dibGPIOFunction {
0231 #define BOARD_GPIO_COMPONENT_BUS_ADAPTER 1
0232 #define BOARD_GPIO_COMPONENT_DEMOD       2
0233     u8 component;
0234
0235 #define BOARD_GPIO_FUNCTION_BOARD_ON      1
0236 #define BOARD_GPIO_FUNCTION_BOARD_OFF     2
0237 #define BOARD_GPIO_FUNCTION_COMPONENT_ON  3
0238 #define BOARD_GPIO_FUNCTION_COMPONENT_OFF 4
0239 #define BOARD_GPIO_FUNCTION_SUBBAND_PWM   5
0240 #define BOARD_GPIO_FUNCTION_SUBBAND_GPIO   6
0241     u8 function;
0242
0243 /* mask, direction and value are used specify which GPIO to change GPIO0
0244  * is LSB and possible GPIO31 is MSB.  The same bit-position as in the
0245  * mask is used for the direction and the value. Direction == 1 is OUT,
0246  * 0 == IN. For direction "OUT" value is either 1 or 0, for direction IN
0247  * value has no meaning.
0248  *
0249  * In case of BOARD_GPIO_FUNCTION_PWM mask is giving the GPIO to be
0250  * used to do the PWM. Direction gives the PWModulator to be used.
0251  * Value gives the PWM value in device-dependent scale.
0252  */
0253     u32 mask;
0254     u32 direction;
0255     u32 value;
0256 };
0257
0258 #define MAX_NB_SUBBANDS   8
0259 struct dibSubbandSelection {
0260     u8  size; /* Actual number of subbands. */
0261     struct {
0262         u16 f_mhz;
0263         struct dibGPIOFunction gpio;
0264     } subband[MAX_NB_SUBBANDS];
0265 };
0266
0267 #define DEMOD_TIMF_SET    0x00
0268 #define DEMOD_TIMF_GET    0x01
0269 #define DEMOD_TIMF_UPDATE 0x02
0270
0271 #define MPEG_ON_DIBTX       1
0272 #define DIV_ON_DIBTX        2
0273 #define ADC_ON_DIBTX        3
0274 #define DEMOUT_ON_HOSTBUS   4
0275 #define DIBTX_ON_HOSTBUS    5
0276 #define MPEG_ON_HOSTBUS     6
0277
0278 #endif