media/dvb-frontends/dib3000mb.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Frontend driver for mobile DVB-T demodulator DiBcom 3000M-B
0004  * DiBcom (http://www.dibcom.fr/)
0005  *
0006  * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@posteo.de)
0007  *
0008  * based on GPL code from DibCom, which has
0009  *
0010  * Copyright (C) 2004 Amaury Demol for DiBcom
0011  *
0012  * Acknowledgements
0013  *
0014  *  Amaury Demol from DiBcom for providing specs and driver
0015  *  sources, on which this driver (and the dvb-dibusb) are based.
0016  *
0017  * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
0018  */
0019
0020 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0021
0022 #include <linux/kernel.h>
0023 #include <linux/module.h>
0024 #include <linux/init.h>
0025 #include <linux/delay.h>
0026 #include <linux/string.h>
0027 #include <linux/slab.h>
0028
0029 #include <media/dvb_frontend.h>
0030
0031 #include "dib3000.h"
0032 #include "dib3000mb_priv.h"
0033
0034 /* Version information */
0035 #define DRIVER_VERSION "0.1"
0036 #define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator"
0037 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@posteo.de"
0038
0039 static int debug;
0040 module_param(debug, int, 0644);
0041 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
0042
0043 #define deb_info(args...) dprintk(0x01, args)
0044 #define deb_i2c(args...)  dprintk(0x02, args)
0045 #define deb_srch(args...) dprintk(0x04, args)
0046 #define deb_info(args...) dprintk(0x01, args)
0047 #define deb_xfer(args...) dprintk(0x02, args)
0048 #define deb_setf(args...) dprintk(0x04, args)
0049 #define deb_getf(args...) dprintk(0x08, args)
0050
0051 static int dib3000_read_reg(struct dib3000_state *state, u16 reg)
0052 {
0053     u8 wb[] = { ((reg >> 8) | 0x80) & 0xff, reg & 0xff };
0054     u8 rb[2];
0055     struct i2c_msg msg[] = {
0056         { .addr = state->config.demod_address, .flags = 0,        .buf = wb, .len = 2 },
0057         { .addr = state->config.demod_address, .flags = I2C_M_RD, .buf = rb, .len = 2 },
0058     };
0059
0060     if (i2c_transfer(state->i2c, msg, 2) != 2)
0061         deb_i2c("i2c read error\n");
0062
0063     deb_i2c("reading i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,
0064             (rb[0] << 8) | rb[1],(rb[0] << 8) | rb[1]);
0065
0066     return (rb[0] << 8) | rb[1];
0067 }
0068
0069 static int dib3000_write_reg(struct dib3000_state *state, u16 reg, u16 val)
0070 {
0071     u8 b[] = {
0072         (reg >> 8) & 0xff, reg & 0xff,
0073         (val >> 8) & 0xff, val & 0xff,
0074     };
0075     struct i2c_msg msg[] = {
0076         { .addr = state->config.demod_address, .flags = 0, .buf = b, .len = 4 }
0077     };
0078     deb_i2c("writing i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,val,val);
0079
0080     return i2c_transfer(state->i2c,msg, 1) != 1 ? -EREMOTEIO : 0;
0081 }
0082
0083 static int dib3000_search_status(u16 irq,u16 lock)
0084 {
0085     if (irq & 0x02) {
0086         if (lock & 0x01) {
0087             deb_srch("auto search succeeded\n");
0088             return 1; // auto search succeeded
0089         } else {
0090             deb_srch("auto search not successful\n");
0091             return 0; // auto search failed
0092         }
0093     } else if (irq & 0x01)  {
0094         deb_srch("auto search failed\n");
0095         return 0; // auto search failed
0096     }
0097     return -1; // try again
0098 }
0099
0100 /* for auto search */
0101 static u16 dib3000_seq[2][2][2] =     /* fft,gua,   inv   */
0102     { /* fft */
0103         { /* gua */
0104             { 0, 1 },                   /*  0   0   { 0,1 } */
0105             { 3, 9 },                   /*  0   1   { 0,1 } */
0106         },
0107         {
0108             { 2, 5 },                   /*  1   0   { 0,1 } */
0109             { 6, 11 },                  /*  1   1   { 0,1 } */
0110         }
0111     };
0112
0113 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
0114                   struct dtv_frontend_properties *c);
0115
0116 static int dib3000mb_set_frontend(struct dvb_frontend *fe, int tuner)
0117 {
0118     struct dib3000_state* state = fe->demodulator_priv;
0119     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0120     enum fe_code_rate fe_cr = FEC_NONE;
0121     int search_state, seq;
0122
0123     if (tuner && fe->ops.tuner_ops.set_params) {
0124         fe->ops.tuner_ops.set_params(fe);
0125         if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
0126
0127         switch (c->bandwidth_hz) {
0128             case 8000000:
0129                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
0130                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
0131                 break;
0132             case 7000000:
0133                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]);
0134                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz);
0135                 break;
0136             case 6000000:
0137                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]);
0138                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz);
0139                 break;
0140             case 0:
0141                 return -EOPNOTSUPP;
0142             default:
0143                 pr_err("unknown bandwidth value.\n");
0144                 return -EINVAL;
0145         }
0146         deb_setf("bandwidth: %d MHZ\n", c->bandwidth_hz / 1000000);
0147     }
0148     wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
0149
0150     switch (c->transmission_mode) {
0151         case TRANSMISSION_MODE_2K:
0152             deb_setf("transmission mode: 2k\n");
0153             wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
0154             break;
0155         case TRANSMISSION_MODE_8K:
0156             deb_setf("transmission mode: 8k\n");
0157             wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
0158             break;
0159         case TRANSMISSION_MODE_AUTO:
0160             deb_setf("transmission mode: auto\n");
0161             break;
0162         default:
0163             return -EINVAL;
0164     }
0165
0166     switch (c->guard_interval) {
0167         case GUARD_INTERVAL_1_32:
0168             deb_setf("guard 1_32\n");
0169             wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
0170             break;
0171         case GUARD_INTERVAL_1_16:
0172             deb_setf("guard 1_16\n");
0173             wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
0174             break;
0175         case GUARD_INTERVAL_1_8:
0176             deb_setf("guard 1_8\n");
0177             wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
0178             break;
0179         case GUARD_INTERVAL_1_4:
0180             deb_setf("guard 1_4\n");
0181             wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
0182             break;
0183         case GUARD_INTERVAL_AUTO:
0184             deb_setf("guard auto\n");
0185             break;
0186         default:
0187             return -EINVAL;
0188     }
0189
0190     switch (c->inversion) {
0191         case INVERSION_OFF:
0192             deb_setf("inversion off\n");
0193             wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
0194             break;
0195         case INVERSION_AUTO:
0196             deb_setf("inversion auto\n");
0197             break;
0198         case INVERSION_ON:
0199             deb_setf("inversion on\n");
0200             wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
0201             break;
0202         default:
0203             return -EINVAL;
0204     }
0205
0206     switch (c->modulation) {
0207         case QPSK:
0208             deb_setf("modulation: qpsk\n");
0209             wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
0210             break;
0211         case QAM_16:
0212             deb_setf("modulation: qam16\n");
0213             wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
0214             break;
0215         case QAM_64:
0216             deb_setf("modulation: qam64\n");
0217             wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
0218             break;
0219         case QAM_AUTO:
0220             break;
0221         default:
0222             return -EINVAL;
0223     }
0224     switch (c->hierarchy) {
0225         case HIERARCHY_NONE:
0226             deb_setf("hierarchy: none\n");
0227             fallthrough;
0228         case HIERARCHY_1:
0229             deb_setf("hierarchy: alpha=1\n");
0230             wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
0231             break;
0232         case HIERARCHY_2:
0233             deb_setf("hierarchy: alpha=2\n");
0234             wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
0235             break;
0236         case HIERARCHY_4:
0237             deb_setf("hierarchy: alpha=4\n");
0238             wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
0239             break;
0240         case HIERARCHY_AUTO:
0241             deb_setf("hierarchy: alpha=auto\n");
0242             break;
0243         default:
0244             return -EINVAL;
0245     }
0246
0247     if (c->hierarchy == HIERARCHY_NONE) {
0248         wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
0249         wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
0250         fe_cr = c->code_rate_HP;
0251     } else if (c->hierarchy != HIERARCHY_AUTO) {
0252         wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
0253         wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
0254         fe_cr = c->code_rate_LP;
0255     }
0256     switch (fe_cr) {
0257         case FEC_1_2:
0258             deb_setf("fec: 1_2\n");
0259             wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
0260             break;
0261         case FEC_2_3:
0262             deb_setf("fec: 2_3\n");
0263             wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
0264             break;
0265         case FEC_3_4:
0266             deb_setf("fec: 3_4\n");
0267             wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
0268             break;
0269         case FEC_5_6:
0270             deb_setf("fec: 5_6\n");
0271             wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
0272             break;
0273         case FEC_7_8:
0274             deb_setf("fec: 7_8\n");
0275             wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
0276             break;
0277         case FEC_NONE:
0278             deb_setf("fec: none\n");
0279             break;
0280         case FEC_AUTO:
0281             deb_setf("fec: auto\n");
0282             break;
0283         default:
0284             return -EINVAL;
0285     }
0286
0287     seq = dib3000_seq
0288         [c->transmission_mode == TRANSMISSION_MODE_AUTO]
0289         [c->guard_interval == GUARD_INTERVAL_AUTO]
0290         [c->inversion == INVERSION_AUTO];
0291
0292     deb_setf("seq? %d\n", seq);
0293
0294     wr(DIB3000MB_REG_SEQ, seq);
0295
0296     wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
0297
0298     if (c->transmission_mode == TRANSMISSION_MODE_2K) {
0299         if (c->guard_interval == GUARD_INTERVAL_1_8) {
0300             wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8);
0301         } else {
0302             wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT);
0303         }
0304
0305         wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K);
0306     } else {
0307         wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT);
0308     }
0309
0310     wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF);
0311     wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
0312     wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF);
0313
0314     wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high);
0315
0316     wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE);
0317
0318     wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL);
0319     wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
0320
0321     /* wait for AGC lock */
0322     msleep(70);
0323
0324     wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
0325
0326     /* something has to be auto searched */
0327     if (c->modulation == QAM_AUTO ||
0328         c->hierarchy == HIERARCHY_AUTO ||
0329         fe_cr == FEC_AUTO ||
0330         c->inversion == INVERSION_AUTO) {
0331         int as_count=0;
0332
0333         deb_setf("autosearch enabled.\n");
0334
0335         wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
0336
0337         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH);
0338         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
0339
0340         while ((search_state =
0341                 dib3000_search_status(
0342                     rd(DIB3000MB_REG_AS_IRQ_PENDING),
0343                     rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
0344             msleep(1);
0345
0346         deb_setf("search_state after autosearch %d after %d checks\n",
0347              search_state, as_count);
0348
0349         if (search_state == 1) {
0350             if (dib3000mb_get_frontend(fe, c) == 0) {
0351                 deb_setf("reading tuning data from frontend succeeded.\n");
0352                 return dib3000mb_set_frontend(fe, 0);
0353             }
0354         }
0355
0356     } else {
0357         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL);
0358         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
0359     }
0360
0361     return 0;
0362 }
0363
0364 static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
0365 {
0366     struct dib3000_state* state = fe->demodulator_priv;
0367
0368     deb_info("dib3000mb is getting up.\n");
0369     wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP);
0370
0371     wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
0372
0373     wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE);
0374     wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST);
0375
0376     wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT);
0377
0378     wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON);
0379
0380     wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB);
0381     wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB);
0382
0383     wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
0384
0385     wr_foreach(dib3000mb_reg_impulse_noise,
0386             dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
0387
0388     wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain);
0389
0390     wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT);
0391
0392     wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
0393
0394     wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration);
0395
0396     wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
0397
0398     wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT);
0399     wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
0400     wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT);
0401     wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
0402
0403     wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
0404
0405     wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68);
0406     wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69);
0407     wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71);
0408     wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77);
0409     wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78);
0410     wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
0411     wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92);
0412     wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96);
0413     wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97);
0414     wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106);
0415     wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107);
0416     wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108);
0417     wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122);
0418     wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
0419     wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT);
0420
0421     wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs);
0422
0423     wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON);
0424     wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB);
0425     wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB);
0426
0427     wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE);
0428
0429     wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142);
0430     wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188);
0431     wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
0432     wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
0433     wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146);
0434     wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147);
0435
0436     wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF);
0437
0438     return 0;
0439 }
0440
0441 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
0442                   struct dtv_frontend_properties *c)
0443 {
0444     struct dib3000_state* state = fe->demodulator_priv;
0445     enum fe_code_rate *cr;
0446     u16 tps_val;
0447     int inv_test1,inv_test2;
0448     u32 dds_val, threshold = 0x800000;
0449
0450     if (!rd(DIB3000MB_REG_TPS_LOCK))
0451         return 0;
0452
0453     dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
0454     deb_getf("DDS_VAL: %x %x %x\n", dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB));
0455     if (dds_val < threshold)
0456         inv_test1 = 0;
0457     else if (dds_val == threshold)
0458         inv_test1 = 1;
0459     else
0460         inv_test1 = 2;
0461
0462     dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
0463     deb_getf("DDS_FREQ: %x %x %x\n", dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB));
0464     if (dds_val < threshold)
0465         inv_test2 = 0;
0466     else if (dds_val == threshold)
0467         inv_test2 = 1;
0468     else
0469         inv_test2 = 2;
0470
0471     c->inversion =
0472         ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
0473         ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
0474         INVERSION_ON : INVERSION_OFF;
0475
0476     deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, c->inversion);
0477
0478     switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
0479         case DIB3000_CONSTELLATION_QPSK:
0480             deb_getf("QPSK\n");
0481             c->modulation = QPSK;
0482             break;
0483         case DIB3000_CONSTELLATION_16QAM:
0484             deb_getf("QAM16\n");
0485             c->modulation = QAM_16;
0486             break;
0487         case DIB3000_CONSTELLATION_64QAM:
0488             deb_getf("QAM64\n");
0489             c->modulation = QAM_64;
0490             break;
0491         default:
0492             pr_err("Unexpected constellation returned by TPS (%d)\n", tps_val);
0493             break;
0494     }
0495     deb_getf("TPS: %d\n", tps_val);
0496
0497     if (rd(DIB3000MB_REG_TPS_HRCH)) {
0498         deb_getf("HRCH ON\n");
0499         cr = &c->code_rate_LP;
0500         c->code_rate_HP = FEC_NONE;
0501         switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
0502             case DIB3000_ALPHA_0:
0503                 deb_getf("HIERARCHY_NONE\n");
0504                 c->hierarchy = HIERARCHY_NONE;
0505                 break;
0506             case DIB3000_ALPHA_1:
0507                 deb_getf("HIERARCHY_1\n");
0508                 c->hierarchy = HIERARCHY_1;
0509                 break;
0510             case DIB3000_ALPHA_2:
0511                 deb_getf("HIERARCHY_2\n");
0512                 c->hierarchy = HIERARCHY_2;
0513                 break;
0514             case DIB3000_ALPHA_4:
0515                 deb_getf("HIERARCHY_4\n");
0516                 c->hierarchy = HIERARCHY_4;
0517                 break;
0518             default:
0519                 pr_err("Unexpected ALPHA value returned by TPS (%d)\n", tps_val);
0520                 break;
0521         }
0522         deb_getf("TPS: %d\n", tps_val);
0523
0524         tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
0525     } else {
0526         deb_getf("HRCH OFF\n");
0527         cr = &c->code_rate_HP;
0528         c->code_rate_LP = FEC_NONE;
0529         c->hierarchy = HIERARCHY_NONE;
0530
0531         tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
0532     }
0533
0534     switch (tps_val) {
0535         case DIB3000_FEC_1_2:
0536             deb_getf("FEC_1_2\n");
0537             *cr = FEC_1_2;
0538             break;
0539         case DIB3000_FEC_2_3:
0540             deb_getf("FEC_2_3\n");
0541             *cr = FEC_2_3;
0542             break;
0543         case DIB3000_FEC_3_4:
0544             deb_getf("FEC_3_4\n");
0545             *cr = FEC_3_4;
0546             break;
0547         case DIB3000_FEC_5_6:
0548             deb_getf("FEC_5_6\n");
0549             *cr = FEC_4_5;
0550             break;
0551         case DIB3000_FEC_7_8:
0552             deb_getf("FEC_7_8\n");
0553             *cr = FEC_7_8;
0554             break;
0555         default:
0556             pr_err("Unexpected FEC returned by TPS (%d)\n", tps_val);
0557             break;
0558     }
0559     deb_getf("TPS: %d\n",tps_val);
0560
0561     switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
0562         case DIB3000_GUARD_TIME_1_32:
0563             deb_getf("GUARD_INTERVAL_1_32\n");
0564             c->guard_interval = GUARD_INTERVAL_1_32;
0565             break;
0566         case DIB3000_GUARD_TIME_1_16:
0567             deb_getf("GUARD_INTERVAL_1_16\n");
0568             c->guard_interval = GUARD_INTERVAL_1_16;
0569             break;
0570         case DIB3000_GUARD_TIME_1_8:
0571             deb_getf("GUARD_INTERVAL_1_8\n");
0572             c->guard_interval = GUARD_INTERVAL_1_8;
0573             break;
0574         case DIB3000_GUARD_TIME_1_4:
0575             deb_getf("GUARD_INTERVAL_1_4\n");
0576             c->guard_interval = GUARD_INTERVAL_1_4;
0577             break;
0578         default:
0579             pr_err("Unexpected Guard Time returned by TPS (%d)\n", tps_val);
0580             break;
0581     }
0582     deb_getf("TPS: %d\n", tps_val);
0583
0584     switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
0585         case DIB3000_TRANSMISSION_MODE_2K:
0586             deb_getf("TRANSMISSION_MODE_2K\n");
0587             c->transmission_mode = TRANSMISSION_MODE_2K;
0588             break;
0589         case DIB3000_TRANSMISSION_MODE_8K:
0590             deb_getf("TRANSMISSION_MODE_8K\n");
0591             c->transmission_mode = TRANSMISSION_MODE_8K;
0592             break;
0593         default:
0594             pr_err("unexpected transmission mode return by TPS (%d)\n", tps_val);
0595             break;
0596     }
0597     deb_getf("TPS: %d\n", tps_val);
0598
0599     return 0;
0600 }
0601
0602 static int dib3000mb_read_status(struct dvb_frontend *fe,
0603                  enum fe_status *stat)
0604 {
0605     struct dib3000_state* state = fe->demodulator_priv;
0606
0607     *stat = 0;
0608
0609     if (rd(DIB3000MB_REG_AGC_LOCK))
0610         *stat |= FE_HAS_SIGNAL;
0611     if (rd(DIB3000MB_REG_CARRIER_LOCK))
0612         *stat |= FE_HAS_CARRIER;
0613     if (rd(DIB3000MB_REG_VIT_LCK))
0614         *stat |= FE_HAS_VITERBI;
0615     if (rd(DIB3000MB_REG_TS_SYNC_LOCK))
0616         *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
0617
0618     deb_getf("actual status is %2x\n",*stat);
0619
0620     deb_getf("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
0621             rd(DIB3000MB_REG_TPS_LOCK),
0622             rd(DIB3000MB_REG_TPS_QAM),
0623             rd(DIB3000MB_REG_TPS_HRCH),
0624             rd(DIB3000MB_REG_TPS_VIT_ALPHA),
0625             rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
0626             rd(DIB3000MB_REG_TPS_CODE_RATE_LP),
0627             rd(DIB3000MB_REG_TPS_GUARD_TIME),
0628             rd(DIB3000MB_REG_TPS_FFT),
0629             rd(DIB3000MB_REG_TPS_CELL_ID));
0630
0631     //*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
0632     return 0;
0633 }
0634
0635 static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber)
0636 {
0637     struct dib3000_state* state = fe->demodulator_priv;
0638
0639     *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB));
0640     return 0;
0641 }
0642
0643 /* see dib3000-watch dvb-apps for exact calcuations of signal_strength and snr */
0644 static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
0645 {
0646     struct dib3000_state* state = fe->demodulator_priv;
0647
0648     *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170;
0649     return 0;
0650 }
0651
0652 static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr)
0653 {
0654     struct dib3000_state* state = fe->demodulator_priv;
0655     short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER);
0656     int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) |
0657         rd(DIB3000MB_REG_NOISE_POWER_LSB);
0658     *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1);
0659     return 0;
0660 }
0661
0662 static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
0663 {
0664     struct dib3000_state* state = fe->demodulator_priv;
0665
0666     *unc = rd(DIB3000MB_REG_PACKET_ERROR_RATE);
0667     return 0;
0668 }
0669
0670 static int dib3000mb_sleep(struct dvb_frontend* fe)
0671 {
0672     struct dib3000_state* state = fe->demodulator_priv;
0673     deb_info("dib3000mb is going to bed.\n");
0674     wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN);
0675     return 0;
0676 }
0677
0678 static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
0679 {
0680     tune->min_delay_ms = 800;
0681     return 0;
0682 }
0683
0684 static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
0685 {
0686     return dib3000mb_fe_init(fe, 0);
0687 }
0688
0689 static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend *fe)
0690 {
0691     return dib3000mb_set_frontend(fe, 1);
0692 }
0693
0694 static void dib3000mb_release(struct dvb_frontend* fe)
0695 {
0696     struct dib3000_state *state = fe->demodulator_priv;
0697     kfree(state);
0698 }
0699
0700 /* pid filter and transfer stuff */
0701 static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
0702 {
0703     struct dib3000_state *state = fe->demodulator_priv;
0704     pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
0705     wr(index+DIB3000MB_REG_FIRST_PID,pid);
0706     return 0;
0707 }
0708
0709 static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff)
0710 {
0711     struct dib3000_state *state = fe->demodulator_priv;
0712
0713     deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
0714     if (onoff) {
0715         wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
0716     } else {
0717         wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
0718     }
0719     return 0;
0720 }
0721
0722 static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff)
0723 {
0724     struct dib3000_state *state = fe->demodulator_priv;
0725     deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
0726     wr(DIB3000MB_REG_PID_PARSE,onoff);
0727     return 0;
0728 }
0729
0730 static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
0731 {
0732     struct dib3000_state *state = fe->demodulator_priv;
0733     if (onoff) {
0734         wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
0735     } else {
0736         wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
0737     }
0738     return 0;
0739 }
0740
0741 static const struct dvb_frontend_ops dib3000mb_ops;
0742
0743 struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
0744                       struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
0745 {
0746     struct dib3000_state* state = NULL;
0747
0748     /* allocate memory for the internal state */
0749     state = kzalloc(sizeof(struct dib3000_state), GFP_KERNEL);
0750     if (state == NULL)
0751         goto error;
0752
0753     /* setup the state */
0754     state->i2c = i2c;
0755     memcpy(&state->config,config,sizeof(struct dib3000_config));
0756
0757     /* check for the correct demod */
0758     if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
0759         goto error;
0760
0761     if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID)
0762         goto error;
0763
0764     /* create dvb_frontend */
0765     memcpy(&state->frontend.ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops));
0766     state->frontend.demodulator_priv = state;
0767
0768     /* set the xfer operations */
0769     xfer_ops->pid_parse = dib3000mb_pid_parse;
0770     xfer_ops->fifo_ctrl = dib3000mb_fifo_control;
0771     xfer_ops->pid_ctrl = dib3000mb_pid_control;
0772     xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl;
0773
0774     return &state->frontend;
0775
0776 error:
0777     kfree(state);
0778     return NULL;
0779 }
0780
0781 static const struct dvb_frontend_ops dib3000mb_ops = {
0782     .delsys = { SYS_DVBT },
0783     .info = {
0784         .name           = "DiBcom 3000M-B DVB-T",
0785         .frequency_min_hz   =  44250 * kHz,
0786         .frequency_max_hz   = 867250 * kHz,
0787         .frequency_stepsize_hz  = 62500,
0788         .caps = FE_CAN_INVERSION_AUTO |
0789                 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
0790                 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
0791                 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
0792                 FE_CAN_TRANSMISSION_MODE_AUTO |
0793                 FE_CAN_GUARD_INTERVAL_AUTO |
0794                 FE_CAN_RECOVER |
0795                 FE_CAN_HIERARCHY_AUTO,
0796     },
0797
0798     .release = dib3000mb_release,
0799
0800     .init = dib3000mb_fe_init_nonmobile,
0801     .sleep = dib3000mb_sleep,
0802
0803     .set_frontend = dib3000mb_set_frontend_and_tuner,
0804     .get_frontend = dib3000mb_get_frontend,
0805     .get_tune_settings = dib3000mb_fe_get_tune_settings,
0806
0807     .read_status = dib3000mb_read_status,
0808     .read_ber = dib3000mb_read_ber,
0809     .read_signal_strength = dib3000mb_read_signal_strength,
0810     .read_snr = dib3000mb_read_snr,
0811     .read_ucblocks = dib3000mb_read_unc_blocks,
0812 };
0813
0814 MODULE_AUTHOR(DRIVER_AUTHOR);
0815 MODULE_DESCRIPTION(DRIVER_DESC);
0816 MODULE_LICENSE("GPL");
0817
0818 EXPORT_SYMBOL(dib3000mb_attach);