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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * cxd2880_tnrdmd.h
0004  * Sony CXD2880 DVB-T2/T tuner + demodulator driver
0005  * common control interface
0006  *
0007  * Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
0008  */
0009 
0010 #ifndef CXD2880_TNRDMD_H
0011 #define CXD2880_TNRDMD_H
0012 
0013 #include <linux/atomic.h>
0014 
0015 #include "cxd2880_common.h"
0016 #include "cxd2880_io.h"
0017 #include "cxd2880_dtv.h"
0018 #include "cxd2880_dvbt.h"
0019 #include "cxd2880_dvbt2.h"
0020 
0021 #define CXD2880_TNRDMD_MAX_CFG_MEM_COUNT 100
0022 
0023 #define slvt_unfreeze_reg(tnr_dmd) ((void)((tnr_dmd)->io->write_reg\
0024 ((tnr_dmd)->io, CXD2880_IO_TGT_DMD, 0x01, 0x00)))
0025 
0026 #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_UNDERFLOW     0x0001
0027 #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_OVERFLOW      0x0002
0028 #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_ALMOST_EMPTY  0x0004
0029 #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_ALMOST_FULL   0x0008
0030 #define CXD2880_TNRDMD_INTERRUPT_TYPE_BUF_RRDY    0x0010
0031 #define CXD2880_TNRDMD_INTERRUPT_TYPE_ILLEGAL_COMMAND      0x0020
0032 #define CXD2880_TNRDMD_INTERRUPT_TYPE_ILLEGAL_ACCESS       0x0040
0033 #define CXD2880_TNRDMD_INTERRUPT_TYPE_CPU_ERROR     0x0100
0034 #define CXD2880_TNRDMD_INTERRUPT_TYPE_LOCK       0x0200
0035 #define CXD2880_TNRDMD_INTERRUPT_TYPE_INV_LOCK       0x0400
0036 #define CXD2880_TNRDMD_INTERRUPT_TYPE_NOOFDM           0x0800
0037 #define CXD2880_TNRDMD_INTERRUPT_TYPE_EWS         0x1000
0038 #define CXD2880_TNRDMD_INTERRUPT_TYPE_EEW         0x2000
0039 #define CXD2880_TNRDMD_INTERRUPT_TYPE_FEC_FAIL       0x4000
0040 
0041 #define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_L1POST_OK 0x01
0042 #define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_DMD_LOCK   0x02
0043 #define CXD2880_TNRDMD_INTERRUPT_LOCK_SEL_TS_LOCK     0x04
0044 
0045 enum cxd2880_tnrdmd_chip_id {
0046     CXD2880_TNRDMD_CHIP_ID_UNKNOWN = 0x00,
0047     CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X = 0x62,
0048     CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11 = 0x6a
0049 };
0050 
0051 #define CXD2880_TNRDMD_CHIP_ID_VALID(chip_id) \
0052     (((chip_id) == CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X) || \
0053      ((chip_id) == CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11))
0054 
0055 enum cxd2880_tnrdmd_state {
0056     CXD2880_TNRDMD_STATE_UNKNOWN,
0057     CXD2880_TNRDMD_STATE_SLEEP,
0058     CXD2880_TNRDMD_STATE_ACTIVE,
0059     CXD2880_TNRDMD_STATE_INVALID
0060 };
0061 
0062 enum cxd2880_tnrdmd_divermode {
0063     CXD2880_TNRDMD_DIVERMODE_SINGLE,
0064     CXD2880_TNRDMD_DIVERMODE_MAIN,
0065     CXD2880_TNRDMD_DIVERMODE_SUB
0066 };
0067 
0068 enum cxd2880_tnrdmd_clockmode {
0069     CXD2880_TNRDMD_CLOCKMODE_UNKNOWN,
0070     CXD2880_TNRDMD_CLOCKMODE_A,
0071     CXD2880_TNRDMD_CLOCKMODE_B,
0072     CXD2880_TNRDMD_CLOCKMODE_C
0073 };
0074 
0075 enum cxd2880_tnrdmd_tsout_if {
0076     CXD2880_TNRDMD_TSOUT_IF_TS,
0077     CXD2880_TNRDMD_TSOUT_IF_SPI,
0078     CXD2880_TNRDMD_TSOUT_IF_SDIO
0079 };
0080 
0081 enum cxd2880_tnrdmd_xtal_share {
0082     CXD2880_TNRDMD_XTAL_SHARE_NONE,
0083     CXD2880_TNRDMD_XTAL_SHARE_EXTREF,
0084     CXD2880_TNRDMD_XTAL_SHARE_MASTER,
0085     CXD2880_TNRDMD_XTAL_SHARE_SLAVE
0086 };
0087 
0088 enum cxd2880_tnrdmd_spectrum_sense {
0089     CXD2880_TNRDMD_SPECTRUM_NORMAL,
0090     CXD2880_TNRDMD_SPECTRUM_INV
0091 };
0092 
0093 enum cxd2880_tnrdmd_cfg_id {
0094     CXD2880_TNRDMD_CFG_OUTPUT_SEL_MSB,
0095     CXD2880_TNRDMD_CFG_TSVALID_ACTIVE_HI,
0096     CXD2880_TNRDMD_CFG_TSSYNC_ACTIVE_HI,
0097     CXD2880_TNRDMD_CFG_TSERR_ACTIVE_HI,
0098     CXD2880_TNRDMD_CFG_LATCH_ON_POSEDGE,
0099     CXD2880_TNRDMD_CFG_TSCLK_CONT,
0100     CXD2880_TNRDMD_CFG_TSCLK_MASK,
0101     CXD2880_TNRDMD_CFG_TSVALID_MASK,
0102     CXD2880_TNRDMD_CFG_TSERR_MASK,
0103     CXD2880_TNRDMD_CFG_TSERR_VALID_DIS,
0104     CXD2880_TNRDMD_CFG_TSPIN_CURRENT,
0105     CXD2880_TNRDMD_CFG_TSPIN_PULLUP_MANUAL,
0106     CXD2880_TNRDMD_CFG_TSPIN_PULLUP,
0107     CXD2880_TNRDMD_CFG_TSCLK_FREQ,
0108     CXD2880_TNRDMD_CFG_TSBYTECLK_MANUAL,
0109     CXD2880_TNRDMD_CFG_TS_PACKET_GAP,
0110     CXD2880_TNRDMD_CFG_TS_BACKWARDS_COMPATIBLE,
0111     CXD2880_TNRDMD_CFG_PWM_VALUE,
0112     CXD2880_TNRDMD_CFG_INTERRUPT,
0113     CXD2880_TNRDMD_CFG_INTERRUPT_LOCK_SEL,
0114     CXD2880_TNRDMD_CFG_INTERRUPT_INV_LOCK_SEL,
0115     CXD2880_TNRDMD_CFG_TS_BUF_ALMOST_EMPTY_THRS,
0116     CXD2880_TNRDMD_CFG_TS_BUF_ALMOST_FULL_THRS,
0117     CXD2880_TNRDMD_CFG_TS_BUF_RRDY_THRS,
0118     CXD2880_TNRDMD_CFG_FIXED_CLOCKMODE,
0119     CXD2880_TNRDMD_CFG_CABLE_INPUT,
0120     CXD2880_TNRDMD_CFG_DVBT2_FEF_INTERMITTENT_BASE,
0121     CXD2880_TNRDMD_CFG_DVBT2_FEF_INTERMITTENT_LITE,
0122     CXD2880_TNRDMD_CFG_BLINDTUNE_DVBT2_FIRST,
0123     CXD2880_TNRDMD_CFG_DVBT_BERN_PERIOD,
0124     CXD2880_TNRDMD_CFG_DVBT_VBER_PERIOD,
0125     CXD2880_TNRDMD_CFG_DVBT_PER_MES,
0126     CXD2880_TNRDMD_CFG_DVBT2_BBER_MES,
0127     CXD2880_TNRDMD_CFG_DVBT2_LBER_MES,
0128     CXD2880_TNRDMD_CFG_DVBT2_PER_MES,
0129 };
0130 
0131 enum cxd2880_tnrdmd_lock_result {
0132     CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT,
0133     CXD2880_TNRDMD_LOCK_RESULT_LOCKED,
0134     CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED
0135 };
0136 
0137 enum cxd2880_tnrdmd_gpio_mode {
0138     CXD2880_TNRDMD_GPIO_MODE_OUTPUT = 0x00,
0139     CXD2880_TNRDMD_GPIO_MODE_INPUT = 0x01,
0140     CXD2880_TNRDMD_GPIO_MODE_INT = 0x02,
0141     CXD2880_TNRDMD_GPIO_MODE_FEC_FAIL = 0x03,
0142     CXD2880_TNRDMD_GPIO_MODE_PWM = 0x04,
0143     CXD2880_TNRDMD_GPIO_MODE_EWS = 0x05,
0144     CXD2880_TNRDMD_GPIO_MODE_EEW = 0x06
0145 };
0146 
0147 enum cxd2880_tnrdmd_serial_ts_clk {
0148     CXD2880_TNRDMD_SERIAL_TS_CLK_FULL,
0149     CXD2880_TNRDMD_SERIAL_TS_CLK_HALF
0150 };
0151 
0152 struct cxd2880_tnrdmd_cfg_mem {
0153     enum cxd2880_io_tgt tgt;
0154     u8 bank;
0155     u8 address;
0156     u8 value;
0157     u8 bit_mask;
0158 };
0159 
0160 struct cxd2880_tnrdmd_pid_cfg {
0161     u8 is_en;
0162     u16 pid;
0163 };
0164 
0165 struct cxd2880_tnrdmd_pid_ftr_cfg {
0166     u8 is_negative;
0167     struct cxd2880_tnrdmd_pid_cfg pid_cfg[32];
0168 };
0169 
0170 struct cxd2880_tnrdmd_lna_thrs {
0171     u8 off_on;
0172     u8 on_off;
0173 };
0174 
0175 struct cxd2880_tnrdmd_lna_thrs_tbl_air {
0176     struct cxd2880_tnrdmd_lna_thrs thrs[24];
0177 };
0178 
0179 struct cxd2880_tnrdmd_lna_thrs_tbl_cable {
0180     struct cxd2880_tnrdmd_lna_thrs thrs[32];
0181 };
0182 
0183 struct cxd2880_tnrdmd_create_param {
0184     enum cxd2880_tnrdmd_tsout_if ts_output_if;
0185     u8 en_internal_ldo;
0186     enum cxd2880_tnrdmd_xtal_share xtal_share_type;
0187     u8 xosc_cap;
0188     u8 xosc_i;
0189     u8 is_cxd2881gg;
0190     u8 stationary_use;
0191 };
0192 
0193 struct cxd2880_tnrdmd_diver_create_param {
0194     enum cxd2880_tnrdmd_tsout_if ts_output_if;
0195     u8 en_internal_ldo;
0196     u8 xosc_cap_main;
0197     u8 xosc_i_main;
0198     u8 xosc_i_sub;
0199     u8 is_cxd2881gg;
0200     u8 stationary_use;
0201 };
0202 
0203 struct cxd2880_tnrdmd {
0204     struct cxd2880_tnrdmd *diver_sub;
0205     struct cxd2880_io *io;
0206     struct cxd2880_tnrdmd_create_param create_param;
0207     enum cxd2880_tnrdmd_divermode diver_mode;
0208     enum cxd2880_tnrdmd_clockmode fixed_clk_mode;
0209     u8 is_cable_input;
0210     u8 en_fef_intmtnt_base;
0211     u8 en_fef_intmtnt_lite;
0212     u8 blind_tune_dvbt2_first;
0213     int (*rf_lvl_cmpstn)(struct cxd2880_tnrdmd *tnr_dmd,
0214                  int *rf_lvl_db);
0215     struct cxd2880_tnrdmd_lna_thrs_tbl_air *lna_thrs_tbl_air;
0216     struct cxd2880_tnrdmd_lna_thrs_tbl_cable *lna_thrs_tbl_cable;
0217     u8 srl_ts_clk_mod_cnts;
0218     enum cxd2880_tnrdmd_serial_ts_clk srl_ts_clk_frq;
0219     u8 ts_byte_clk_manual_setting;
0220     u8 is_ts_backwards_compatible_mode;
0221     struct cxd2880_tnrdmd_cfg_mem cfg_mem[CXD2880_TNRDMD_MAX_CFG_MEM_COUNT];
0222     u8 cfg_mem_last_entry;
0223     struct cxd2880_tnrdmd_pid_ftr_cfg pid_ftr_cfg;
0224     u8 pid_ftr_cfg_en;
0225     void *user;
0226     enum cxd2880_tnrdmd_chip_id chip_id;
0227     enum cxd2880_tnrdmd_state state;
0228     enum cxd2880_tnrdmd_clockmode clk_mode;
0229     u32 frequency_khz;
0230     enum cxd2880_dtv_sys sys;
0231     enum cxd2880_dtv_bandwidth bandwidth;
0232     u8 scan_mode;
0233     atomic_t cancel;
0234 };
0235 
0236 int cxd2880_tnrdmd_create(struct cxd2880_tnrdmd *tnr_dmd,
0237               struct cxd2880_io *io,
0238               struct cxd2880_tnrdmd_create_param
0239               *create_param);
0240 
0241 int cxd2880_tnrdmd_diver_create(struct cxd2880_tnrdmd
0242                 *tnr_dmd_main,
0243                 struct cxd2880_io *io_main,
0244                 struct cxd2880_tnrdmd *tnr_dmd_sub,
0245                 struct cxd2880_io *io_sub,
0246                 struct
0247                 cxd2880_tnrdmd_diver_create_param
0248                 *create_param);
0249 
0250 int cxd2880_tnrdmd_init1(struct cxd2880_tnrdmd *tnr_dmd);
0251 
0252 int cxd2880_tnrdmd_init2(struct cxd2880_tnrdmd *tnr_dmd);
0253 
0254 int cxd2880_tnrdmd_check_internal_cpu_status(struct cxd2880_tnrdmd
0255                          *tnr_dmd,
0256                          u8 *task_completed);
0257 
0258 int cxd2880_tnrdmd_common_tune_setting1(struct cxd2880_tnrdmd
0259                     *tnr_dmd,
0260                     enum cxd2880_dtv_sys sys,
0261                     u32 frequency_khz,
0262                     enum cxd2880_dtv_bandwidth
0263                     bandwidth, u8 one_seg_opt,
0264                     u8 one_seg_opt_shft_dir);
0265 
0266 int cxd2880_tnrdmd_common_tune_setting2(struct cxd2880_tnrdmd
0267                     *tnr_dmd,
0268                     enum cxd2880_dtv_sys sys,
0269                     u8 en_fef_intmtnt_ctrl);
0270 
0271 int cxd2880_tnrdmd_sleep(struct cxd2880_tnrdmd *tnr_dmd);
0272 
0273 int cxd2880_tnrdmd_set_cfg(struct cxd2880_tnrdmd *tnr_dmd,
0274                enum cxd2880_tnrdmd_cfg_id id,
0275                int value);
0276 
0277 int cxd2880_tnrdmd_gpio_set_cfg(struct cxd2880_tnrdmd *tnr_dmd,
0278                 u8 id,
0279                 u8 en,
0280                 enum cxd2880_tnrdmd_gpio_mode mode,
0281                 u8 open_drain, u8 invert);
0282 
0283 int cxd2880_tnrdmd_gpio_set_cfg_sub(struct cxd2880_tnrdmd *tnr_dmd,
0284                     u8 id,
0285                     u8 en,
0286                     enum cxd2880_tnrdmd_gpio_mode
0287                     mode, u8 open_drain,
0288                     u8 invert);
0289 
0290 int cxd2880_tnrdmd_gpio_read(struct cxd2880_tnrdmd *tnr_dmd,
0291                  u8 id, u8 *value);
0292 
0293 int cxd2880_tnrdmd_gpio_read_sub(struct cxd2880_tnrdmd *tnr_dmd,
0294                  u8 id, u8 *value);
0295 
0296 int cxd2880_tnrdmd_gpio_write(struct cxd2880_tnrdmd *tnr_dmd,
0297                   u8 id, u8 value);
0298 
0299 int cxd2880_tnrdmd_gpio_write_sub(struct cxd2880_tnrdmd *tnr_dmd,
0300                   u8 id, u8 value);
0301 
0302 int cxd2880_tnrdmd_interrupt_read(struct cxd2880_tnrdmd *tnr_dmd,
0303                   u16 *value);
0304 
0305 int cxd2880_tnrdmd_interrupt_clear(struct cxd2880_tnrdmd *tnr_dmd,
0306                    u16 value);
0307 
0308 int cxd2880_tnrdmd_ts_buf_clear(struct cxd2880_tnrdmd *tnr_dmd,
0309                 u8 clear_overflow_flag,
0310                 u8 clear_underflow_flag,
0311                 u8 clear_buf);
0312 
0313 int cxd2880_tnrdmd_chip_id(struct cxd2880_tnrdmd *tnr_dmd,
0314                enum cxd2880_tnrdmd_chip_id *chip_id);
0315 
0316 int cxd2880_tnrdmd_set_and_save_reg_bits(struct cxd2880_tnrdmd
0317                      *tnr_dmd,
0318                      enum cxd2880_io_tgt tgt,
0319                      u8 bank, u8 address,
0320                      u8 value, u8 bit_mask);
0321 
0322 int cxd2880_tnrdmd_set_scan_mode(struct cxd2880_tnrdmd *tnr_dmd,
0323                  enum cxd2880_dtv_sys sys,
0324                  u8 scan_mode_end);
0325 
0326 int cxd2880_tnrdmd_set_pid_ftr(struct cxd2880_tnrdmd *tnr_dmd,
0327                    struct cxd2880_tnrdmd_pid_ftr_cfg
0328                    *pid_ftr_cfg);
0329 
0330 int cxd2880_tnrdmd_set_rf_lvl_cmpstn(struct cxd2880_tnrdmd
0331                      *tnr_dmd,
0332                      int (*rf_lvl_cmpstn)
0333                      (struct cxd2880_tnrdmd *,
0334                      int *));
0335 
0336 int cxd2880_tnrdmd_set_rf_lvl_cmpstn_sub(struct cxd2880_tnrdmd *tnr_dmd,
0337                      int (*rf_lvl_cmpstn)
0338                      (struct cxd2880_tnrdmd *,
0339                      int *));
0340 
0341 int cxd2880_tnrdmd_set_lna_thrs(struct cxd2880_tnrdmd *tnr_dmd,
0342                 struct
0343                 cxd2880_tnrdmd_lna_thrs_tbl_air
0344                 *tbl_air,
0345                 struct
0346                 cxd2880_tnrdmd_lna_thrs_tbl_cable
0347                 *tbl_cable);
0348 
0349 int cxd2880_tnrdmd_set_lna_thrs_sub(struct cxd2880_tnrdmd *tnr_dmd,
0350                     struct
0351                     cxd2880_tnrdmd_lna_thrs_tbl_air
0352                     *tbl_air,
0353                     struct
0354                     cxd2880_tnrdmd_lna_thrs_tbl_cable
0355                     *tbl_cable);
0356 
0357 int cxd2880_tnrdmd_set_ts_pin_high_low(struct cxd2880_tnrdmd
0358                        *tnr_dmd, u8 en, u8 value);
0359 
0360 int cxd2880_tnrdmd_set_ts_output(struct cxd2880_tnrdmd *tnr_dmd,
0361                  u8 en);
0362 
0363 int slvt_freeze_reg(struct cxd2880_tnrdmd *tnr_dmd);
0364 
0365 #endif
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