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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * cxd2880_dvbt2.h
0004  * Sony CXD2880 DVB-T2/T tuner + demodulator driver
0005  * DVB-T2 related definitions
0006  *
0007  * Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
0008  */
0009 
0010 #ifndef CXD2880_DVBT2_H
0011 #define CXD2880_DVBT2_H
0012 
0013 #include "cxd2880_common.h"
0014 
0015 enum cxd2880_dvbt2_profile {
0016     CXD2880_DVBT2_PROFILE_BASE,
0017     CXD2880_DVBT2_PROFILE_LITE,
0018     CXD2880_DVBT2_PROFILE_ANY
0019 };
0020 
0021 enum cxd2880_dvbt2_version {
0022     CXD2880_DVBT2_V111,
0023     CXD2880_DVBT2_V121,
0024     CXD2880_DVBT2_V131
0025 };
0026 
0027 enum cxd2880_dvbt2_s1 {
0028     CXD2880_DVBT2_S1_BASE_SISO = 0x00,
0029     CXD2880_DVBT2_S1_BASE_MISO = 0x01,
0030     CXD2880_DVBT2_S1_NON_DVBT2 = 0x02,
0031     CXD2880_DVBT2_S1_LITE_SISO = 0x03,
0032     CXD2880_DVBT2_S1_LITE_MISO = 0x04,
0033     CXD2880_DVBT2_S1_RSVD3 = 0x05,
0034     CXD2880_DVBT2_S1_RSVD4 = 0x06,
0035     CXD2880_DVBT2_S1_RSVD5 = 0x07,
0036     CXD2880_DVBT2_S1_UNKNOWN = 0xff
0037 };
0038 
0039 enum cxd2880_dvbt2_base_s2 {
0040     CXD2880_DVBT2_BASE_S2_M2K_G_ANY = 0x00,
0041     CXD2880_DVBT2_BASE_S2_M8K_G_DVBT = 0x01,
0042     CXD2880_DVBT2_BASE_S2_M4K_G_ANY = 0x02,
0043     CXD2880_DVBT2_BASE_S2_M1K_G_ANY = 0x03,
0044     CXD2880_DVBT2_BASE_S2_M16K_G_ANY = 0x04,
0045     CXD2880_DVBT2_BASE_S2_M32K_G_DVBT = 0x05,
0046     CXD2880_DVBT2_BASE_S2_M8K_G_DVBT2 = 0x06,
0047     CXD2880_DVBT2_BASE_S2_M32K_G_DVBT2 = 0x07,
0048     CXD2880_DVBT2_BASE_S2_UNKNOWN = 0xff
0049 };
0050 
0051 enum cxd2880_dvbt2_lite_s2 {
0052     CXD2880_DVBT2_LITE_S2_M2K_G_ANY = 0x00,
0053     CXD2880_DVBT2_LITE_S2_M8K_G_DVBT = 0x01,
0054     CXD2880_DVBT2_LITE_S2_M4K_G_ANY = 0x02,
0055     CXD2880_DVBT2_LITE_S2_M16K_G_DVBT2 = 0x03,
0056     CXD2880_DVBT2_LITE_S2_M16K_G_DVBT = 0x04,
0057     CXD2880_DVBT2_LITE_S2_RSVD1 = 0x05,
0058     CXD2880_DVBT2_LITE_S2_M8K_G_DVBT2 = 0x06,
0059     CXD2880_DVBT2_LITE_S2_RSVD2 = 0x07,
0060     CXD2880_DVBT2_LITE_S2_UNKNOWN = 0xff
0061 };
0062 
0063 enum cxd2880_dvbt2_guard {
0064     CXD2880_DVBT2_G1_32 = 0x00,
0065     CXD2880_DVBT2_G1_16 = 0x01,
0066     CXD2880_DVBT2_G1_8 = 0x02,
0067     CXD2880_DVBT2_G1_4 = 0x03,
0068     CXD2880_DVBT2_G1_128 = 0x04,
0069     CXD2880_DVBT2_G19_128 = 0x05,
0070     CXD2880_DVBT2_G19_256 = 0x06,
0071     CXD2880_DVBT2_G_RSVD1 = 0x07,
0072     CXD2880_DVBT2_G_UNKNOWN = 0xff
0073 };
0074 
0075 enum cxd2880_dvbt2_mode {
0076     CXD2880_DVBT2_M2K = 0x00,
0077     CXD2880_DVBT2_M8K = 0x01,
0078     CXD2880_DVBT2_M4K = 0x02,
0079     CXD2880_DVBT2_M1K = 0x03,
0080     CXD2880_DVBT2_M16K = 0x04,
0081     CXD2880_DVBT2_M32K = 0x05,
0082     CXD2880_DVBT2_M_RSVD1 = 0x06,
0083     CXD2880_DVBT2_M_RSVD2 = 0x07
0084 };
0085 
0086 enum cxd2880_dvbt2_bw {
0087     CXD2880_DVBT2_BW_8 = 0x00,
0088     CXD2880_DVBT2_BW_7 = 0x01,
0089     CXD2880_DVBT2_BW_6 = 0x02,
0090     CXD2880_DVBT2_BW_5 = 0x03,
0091     CXD2880_DVBT2_BW_10 = 0x04,
0092     CXD2880_DVBT2_BW_1_7 = 0x05,
0093     CXD2880_DVBT2_BW_RSVD1 = 0x06,
0094     CXD2880_DVBT2_BW_RSVD2 = 0x07,
0095     CXD2880_DVBT2_BW_RSVD3 = 0x08,
0096     CXD2880_DVBT2_BW_RSVD4 = 0x09,
0097     CXD2880_DVBT2_BW_RSVD5 = 0x0a,
0098     CXD2880_DVBT2_BW_RSVD6 = 0x0b,
0099     CXD2880_DVBT2_BW_RSVD7 = 0x0c,
0100     CXD2880_DVBT2_BW_RSVD8 = 0x0d,
0101     CXD2880_DVBT2_BW_RSVD9 = 0x0e,
0102     CXD2880_DVBT2_BW_RSVD10 = 0x0f,
0103     CXD2880_DVBT2_BW_UNKNOWN = 0xff
0104 };
0105 
0106 enum cxd2880_dvbt2_l1pre_type {
0107     CXD2880_DVBT2_L1PRE_TYPE_TS = 0x00,
0108     CXD2880_DVBT2_L1PRE_TYPE_GS = 0x01,
0109     CXD2880_DVBT2_L1PRE_TYPE_TS_GS = 0x02,
0110     CXD2880_DVBT2_L1PRE_TYPE_RESERVED = 0x03,
0111     CXD2880_DVBT2_L1PRE_TYPE_UNKNOWN = 0xff
0112 };
0113 
0114 enum cxd2880_dvbt2_papr {
0115     CXD2880_DVBT2_PAPR_0 = 0x00,
0116     CXD2880_DVBT2_PAPR_1 = 0x01,
0117     CXD2880_DVBT2_PAPR_2 = 0x02,
0118     CXD2880_DVBT2_PAPR_3 = 0x03,
0119     CXD2880_DVBT2_PAPR_RSVD1 = 0x04,
0120     CXD2880_DVBT2_PAPR_RSVD2 = 0x05,
0121     CXD2880_DVBT2_PAPR_RSVD3 = 0x06,
0122     CXD2880_DVBT2_PAPR_RSVD4 = 0x07,
0123     CXD2880_DVBT2_PAPR_RSVD5 = 0x08,
0124     CXD2880_DVBT2_PAPR_RSVD6 = 0x09,
0125     CXD2880_DVBT2_PAPR_RSVD7 = 0x0a,
0126     CXD2880_DVBT2_PAPR_RSVD8 = 0x0b,
0127     CXD2880_DVBT2_PAPR_RSVD9 = 0x0c,
0128     CXD2880_DVBT2_PAPR_RSVD10 = 0x0d,
0129     CXD2880_DVBT2_PAPR_RSVD11 = 0x0e,
0130     CXD2880_DVBT2_PAPR_RSVD12 = 0x0f,
0131     CXD2880_DVBT2_PAPR_UNKNOWN = 0xff
0132 };
0133 
0134 enum cxd2880_dvbt2_l1post_constell {
0135     CXD2880_DVBT2_L1POST_BPSK = 0x00,
0136     CXD2880_DVBT2_L1POST_QPSK = 0x01,
0137     CXD2880_DVBT2_L1POST_QAM16 = 0x02,
0138     CXD2880_DVBT2_L1POST_QAM64 = 0x03,
0139     CXD2880_DVBT2_L1POST_C_RSVD1 = 0x04,
0140     CXD2880_DVBT2_L1POST_C_RSVD2 = 0x05,
0141     CXD2880_DVBT2_L1POST_C_RSVD3 = 0x06,
0142     CXD2880_DVBT2_L1POST_C_RSVD4 = 0x07,
0143     CXD2880_DVBT2_L1POST_C_RSVD5 = 0x08,
0144     CXD2880_DVBT2_L1POST_C_RSVD6 = 0x09,
0145     CXD2880_DVBT2_L1POST_C_RSVD7 = 0x0a,
0146     CXD2880_DVBT2_L1POST_C_RSVD8 = 0x0b,
0147     CXD2880_DVBT2_L1POST_C_RSVD9 = 0x0c,
0148     CXD2880_DVBT2_L1POST_C_RSVD10 = 0x0d,
0149     CXD2880_DVBT2_L1POST_C_RSVD11 = 0x0e,
0150     CXD2880_DVBT2_L1POST_C_RSVD12 = 0x0f,
0151     CXD2880_DVBT2_L1POST_CONSTELL_UNKNOWN = 0xff
0152 };
0153 
0154 enum cxd2880_dvbt2_l1post_cr {
0155     CXD2880_DVBT2_L1POST_R1_2 = 0x00,
0156     CXD2880_DVBT2_L1POST_R_RSVD1 = 0x01,
0157     CXD2880_DVBT2_L1POST_R_RSVD2 = 0x02,
0158     CXD2880_DVBT2_L1POST_R_RSVD3 = 0x03,
0159     CXD2880_DVBT2_L1POST_R_UNKNOWN = 0xff
0160 };
0161 
0162 enum cxd2880_dvbt2_l1post_fec_type {
0163     CXD2880_DVBT2_L1POST_FEC_LDPC16K = 0x00,
0164     CXD2880_DVBT2_L1POST_FEC_RSVD1 = 0x01,
0165     CXD2880_DVBT2_L1POST_FEC_RSVD2 = 0x02,
0166     CXD2880_DVBT2_L1POST_FEC_RSVD3 = 0x03,
0167     CXD2880_DVBT2_L1POST_FEC_UNKNOWN = 0xff
0168 };
0169 
0170 enum cxd2880_dvbt2_pp {
0171     CXD2880_DVBT2_PP1 = 0x00,
0172     CXD2880_DVBT2_PP2 = 0x01,
0173     CXD2880_DVBT2_PP3 = 0x02,
0174     CXD2880_DVBT2_PP4 = 0x03,
0175     CXD2880_DVBT2_PP5 = 0x04,
0176     CXD2880_DVBT2_PP6 = 0x05,
0177     CXD2880_DVBT2_PP7 = 0x06,
0178     CXD2880_DVBT2_PP8 = 0x07,
0179     CXD2880_DVBT2_PP_RSVD1 = 0x08,
0180     CXD2880_DVBT2_PP_RSVD2 = 0x09,
0181     CXD2880_DVBT2_PP_RSVD3 = 0x0a,
0182     CXD2880_DVBT2_PP_RSVD4 = 0x0b,
0183     CXD2880_DVBT2_PP_RSVD5 = 0x0c,
0184     CXD2880_DVBT2_PP_RSVD6 = 0x0d,
0185     CXD2880_DVBT2_PP_RSVD7 = 0x0e,
0186     CXD2880_DVBT2_PP_RSVD8 = 0x0f,
0187     CXD2880_DVBT2_PP_UNKNOWN = 0xff
0188 };
0189 
0190 enum cxd2880_dvbt2_plp_code_rate {
0191     CXD2880_DVBT2_R1_2 = 0x00,
0192     CXD2880_DVBT2_R3_5 = 0x01,
0193     CXD2880_DVBT2_R2_3 = 0x02,
0194     CXD2880_DVBT2_R3_4 = 0x03,
0195     CXD2880_DVBT2_R4_5 = 0x04,
0196     CXD2880_DVBT2_R5_6 = 0x05,
0197     CXD2880_DVBT2_R1_3 = 0x06,
0198     CXD2880_DVBT2_R2_5 = 0x07,
0199     CXD2880_DVBT2_PLP_CR_UNKNOWN = 0xff
0200 };
0201 
0202 enum cxd2880_dvbt2_plp_constell {
0203     CXD2880_DVBT2_QPSK = 0x00,
0204     CXD2880_DVBT2_QAM16 = 0x01,
0205     CXD2880_DVBT2_QAM64 = 0x02,
0206     CXD2880_DVBT2_QAM256 = 0x03,
0207     CXD2880_DVBT2_CON_RSVD1 = 0x04,
0208     CXD2880_DVBT2_CON_RSVD2 = 0x05,
0209     CXD2880_DVBT2_CON_RSVD3 = 0x06,
0210     CXD2880_DVBT2_CON_RSVD4 = 0x07,
0211     CXD2880_DVBT2_CONSTELL_UNKNOWN = 0xff
0212 };
0213 
0214 enum cxd2880_dvbt2_plp_type {
0215     CXD2880_DVBT2_PLP_TYPE_COMMON = 0x00,
0216     CXD2880_DVBT2_PLP_TYPE_DATA1 = 0x01,
0217     CXD2880_DVBT2_PLP_TYPE_DATA2 = 0x02,
0218     CXD2880_DVBT2_PLP_TYPE_RSVD1 = 0x03,
0219     CXD2880_DVBT2_PLP_TYPE_RSVD2 = 0x04,
0220     CXD2880_DVBT2_PLP_TYPE_RSVD3 = 0x05,
0221     CXD2880_DVBT2_PLP_TYPE_RSVD4 = 0x06,
0222     CXD2880_DVBT2_PLP_TYPE_RSVD5 = 0x07,
0223     CXD2880_DVBT2_PLP_TYPE_UNKNOWN = 0xff
0224 };
0225 
0226 enum cxd2880_dvbt2_plp_payload {
0227     CXD2880_DVBT2_PLP_PAYLOAD_GFPS = 0x00,
0228     CXD2880_DVBT2_PLP_PAYLOAD_GCS = 0x01,
0229     CXD2880_DVBT2_PLP_PAYLOAD_GSE = 0x02,
0230     CXD2880_DVBT2_PLP_PAYLOAD_TS = 0x03,
0231     CXD2880_DVBT2_PLP_PAYLOAD_RSVD1 = 0x04,
0232     CXD2880_DVBT2_PLP_PAYLOAD_RSVD2 = 0x05,
0233     CXD2880_DVBT2_PLP_PAYLOAD_RSVD3 = 0x06,
0234     CXD2880_DVBT2_PLP_PAYLOAD_RSVD4 = 0x07,
0235     CXD2880_DVBT2_PLP_PAYLOAD_RSVD5 = 0x08,
0236     CXD2880_DVBT2_PLP_PAYLOAD_RSVD6 = 0x09,
0237     CXD2880_DVBT2_PLP_PAYLOAD_RSVD7 = 0x0a,
0238     CXD2880_DVBT2_PLP_PAYLOAD_RSVD8 = 0x0b,
0239     CXD2880_DVBT2_PLP_PAYLOAD_RSVD9 = 0x0c,
0240     CXD2880_DVBT2_PLP_PAYLOAD_RSVD10 = 0x0d,
0241     CXD2880_DVBT2_PLP_PAYLOAD_RSVD11 = 0x0e,
0242     CXD2880_DVBT2_PLP_PAYLOAD_RSVD12 = 0x0f,
0243     CXD2880_DVBT2_PLP_PAYLOAD_RSVD13 = 0x10,
0244     CXD2880_DVBT2_PLP_PAYLOAD_RSVD14 = 0x11,
0245     CXD2880_DVBT2_PLP_PAYLOAD_RSVD15 = 0x12,
0246     CXD2880_DVBT2_PLP_PAYLOAD_RSVD16 = 0x13,
0247     CXD2880_DVBT2_PLP_PAYLOAD_RSVD17 = 0x14,
0248     CXD2880_DVBT2_PLP_PAYLOAD_RSVD18 = 0x15,
0249     CXD2880_DVBT2_PLP_PAYLOAD_RSVD19 = 0x16,
0250     CXD2880_DVBT2_PLP_PAYLOAD_RSVD20 = 0x17,
0251     CXD2880_DVBT2_PLP_PAYLOAD_RSVD21 = 0x18,
0252     CXD2880_DVBT2_PLP_PAYLOAD_RSVD22 = 0x19,
0253     CXD2880_DVBT2_PLP_PAYLOAD_RSVD23 = 0x1a,
0254     CXD2880_DVBT2_PLP_PAYLOAD_RSVD24 = 0x1b,
0255     CXD2880_DVBT2_PLP_PAYLOAD_RSVD25 = 0x1c,
0256     CXD2880_DVBT2_PLP_PAYLOAD_RSVD26 = 0x1d,
0257     CXD2880_DVBT2_PLP_PAYLOAD_RSVD27 = 0x1e,
0258     CXD2880_DVBT2_PLP_PAYLOAD_RSVD28 = 0x1f,
0259     CXD2880_DVBT2_PLP_PAYLOAD_UNKNOWN = 0xff
0260 };
0261 
0262 enum cxd2880_dvbt2_plp_fec {
0263     CXD2880_DVBT2_FEC_LDPC_16K = 0x00,
0264     CXD2880_DVBT2_FEC_LDPC_64K = 0x01,
0265     CXD2880_DVBT2_FEC_RSVD1 = 0x02,
0266     CXD2880_DVBT2_FEC_RSVD2 = 0x03,
0267     CXD2880_DVBT2_FEC_UNKNOWN = 0xff
0268 };
0269 
0270 enum cxd2880_dvbt2_plp_mode {
0271     CXD2880_DVBT2_PLP_MODE_NOTSPECIFIED = 0x00,
0272     CXD2880_DVBT2_PLP_MODE_NM = 0x01,
0273     CXD2880_DVBT2_PLP_MODE_HEM = 0x02,
0274     CXD2880_DVBT2_PLP_MODE_RESERVED = 0x03,
0275     CXD2880_DVBT2_PLP_MODE_UNKNOWN = 0xff
0276 };
0277 
0278 enum cxd2880_dvbt2_plp_btype {
0279     CXD2880_DVBT2_PLP_COMMON,
0280     CXD2880_DVBT2_PLP_DATA
0281 };
0282 
0283 enum cxd2880_dvbt2_stream {
0284     CXD2880_DVBT2_STREAM_GENERIC_PACKETIZED = 0x00,
0285     CXD2880_DVBT2_STREAM_GENERIC_CONTINUOUS = 0x01,
0286     CXD2880_DVBT2_STREAM_GENERIC_ENCAPSULATED = 0x02,
0287     CXD2880_DVBT2_STREAM_TRANSPORT = 0x03,
0288     CXD2880_DVBT2_STREAM_UNKNOWN = 0xff
0289 };
0290 
0291 struct cxd2880_dvbt2_l1pre {
0292     enum cxd2880_dvbt2_l1pre_type type;
0293     u8 bw_ext;
0294     enum cxd2880_dvbt2_s1 s1;
0295     u8 s2;
0296     u8 mixed;
0297     enum cxd2880_dvbt2_mode fft_mode;
0298     u8 l1_rep;
0299     enum cxd2880_dvbt2_guard gi;
0300     enum cxd2880_dvbt2_papr papr;
0301     enum cxd2880_dvbt2_l1post_constell mod;
0302     enum cxd2880_dvbt2_l1post_cr cr;
0303     enum cxd2880_dvbt2_l1post_fec_type fec;
0304     u32 l1_post_size;
0305     u32 l1_post_info_size;
0306     enum cxd2880_dvbt2_pp pp;
0307     u8 tx_id_availability;
0308     u16 cell_id;
0309     u16 network_id;
0310     u16 sys_id;
0311     u8 num_frames;
0312     u16 num_symbols;
0313     u8 regen;
0314     u8 post_ext;
0315     u8 num_rf_freqs;
0316     u8 rf_idx;
0317     enum cxd2880_dvbt2_version t2_version;
0318     u8 l1_post_scrambled;
0319     u8 t2_base_lite;
0320     u32 crc32;
0321 };
0322 
0323 struct cxd2880_dvbt2_plp {
0324     u8 id;
0325     enum cxd2880_dvbt2_plp_type type;
0326     enum cxd2880_dvbt2_plp_payload payload;
0327     u8 ff;
0328     u8 first_rf_idx;
0329     u8 first_frm_idx;
0330     u8 group_id;
0331     enum cxd2880_dvbt2_plp_constell constell;
0332     enum cxd2880_dvbt2_plp_code_rate plp_cr;
0333     u8 rot;
0334     enum cxd2880_dvbt2_plp_fec fec;
0335     u16 num_blocks_max;
0336     u8 frm_int;
0337     u8 til_len;
0338     u8 til_type;
0339     u8 in_band_a_flag;
0340     u8 in_band_b_flag;
0341     u16 rsvd;
0342     enum cxd2880_dvbt2_plp_mode plp_mode;
0343     u8 static_flag;
0344     u8 static_padding_flag;
0345 };
0346 
0347 struct cxd2880_dvbt2_l1post {
0348     u16 sub_slices_per_frame;
0349     u8 num_plps;
0350     u8 num_aux;
0351     u8 aux_cfg_rfu;
0352     u8 rf_idx;
0353     u32 freq;
0354     u8 fef_type;
0355     u32 fef_length;
0356     u8 fef_intvl;
0357 };
0358 
0359 struct cxd2880_dvbt2_ofdm {
0360     u8 mixed;
0361     u8 is_miso;
0362     enum cxd2880_dvbt2_mode mode;
0363     enum cxd2880_dvbt2_guard gi;
0364     enum cxd2880_dvbt2_pp pp;
0365     u8 bw_ext;
0366     enum cxd2880_dvbt2_papr papr;
0367     u16 num_symbols;
0368 };
0369 
0370 struct cxd2880_dvbt2_bbheader {
0371     enum cxd2880_dvbt2_stream stream_input;
0372     u8 is_single_input_stream;
0373     u8 is_constant_coding_modulation;
0374     u8 issy_indicator;
0375     u8 null_packet_deletion;
0376     u8 ext;
0377     u8 input_stream_identifier;
0378     u16 user_packet_length;
0379     u16 data_field_length;
0380     u8 sync_byte;
0381     u32 issy;
0382     enum cxd2880_dvbt2_plp_mode plp_mode;
0383 };
0384 
0385 #endif
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