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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Sony CXD2820R demodulator driver
0004  *
0005  * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
0006  */
0007 
0008 
0009 #include "cxd2820r_priv.h"
0010 
0011 int cxd2820r_set_frontend_t2(struct dvb_frontend *fe)
0012 {
0013     struct cxd2820r_priv *priv = fe->demodulator_priv;
0014     struct i2c_client *client = priv->client[0];
0015     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0016     int ret, bw_i;
0017     unsigned int utmp;
0018     u32 if_frequency;
0019     u8 buf[3], bw_param;
0020     u8 bw_params1[][5] = {
0021         { 0x1c, 0xb3, 0x33, 0x33, 0x33 }, /* 5 MHz */
0022         { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
0023         { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
0024         { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
0025     };
0026     struct reg_val_mask tab[] = {
0027         { 0x00080, 0x02, 0xff },
0028         { 0x00081, 0x20, 0xff },
0029         { 0x00085, 0x07, 0xff },
0030         { 0x00088, 0x01, 0xff },
0031         { 0x02069, 0x01, 0xff },
0032 
0033         { 0x0207f, 0x2a, 0xff },
0034         { 0x02082, 0x0a, 0xff },
0035         { 0x02083, 0x0a, 0xff },
0036         { 0x020cb, priv->if_agc_polarity << 6, 0x40 },
0037         { 0x02070, priv->ts_mode, 0xff },
0038         { 0x02071, !priv->ts_clk_inv << 6, 0x40 },
0039         { 0x020b5, priv->spec_inv << 4, 0x10 },
0040         { 0x02567, 0x07, 0x0f },
0041         { 0x02569, 0x03, 0x03 },
0042         { 0x02595, 0x1a, 0xff },
0043         { 0x02596, 0x50, 0xff },
0044         { 0x02a8c, 0x00, 0xff },
0045         { 0x02a8d, 0x34, 0xff },
0046         { 0x02a45, 0x06, 0x07 },
0047         { 0x03f10, 0x0d, 0xff },
0048         { 0x03f11, 0x02, 0xff },
0049         { 0x03f12, 0x01, 0xff },
0050         { 0x03f23, 0x2c, 0xff },
0051         { 0x03f51, 0x13, 0xff },
0052         { 0x03f52, 0x01, 0xff },
0053         { 0x03f53, 0x00, 0xff },
0054         { 0x027e6, 0x14, 0xff },
0055         { 0x02786, 0x02, 0x07 },
0056         { 0x02787, 0x40, 0xe0 },
0057         { 0x027ef, 0x10, 0x18 },
0058     };
0059 
0060     dev_dbg(&client->dev,
0061         "delivery_system=%d modulation=%d frequency=%u bandwidth_hz=%u inversion=%d stream_id=%u\n",
0062         c->delivery_system, c->modulation, c->frequency,
0063         c->bandwidth_hz, c->inversion, c->stream_id);
0064 
0065     switch (c->bandwidth_hz) {
0066     case 5000000:
0067         bw_i = 0;
0068         bw_param = 3;
0069         break;
0070     case 6000000:
0071         bw_i = 1;
0072         bw_param = 2;
0073         break;
0074     case 7000000:
0075         bw_i = 2;
0076         bw_param = 1;
0077         break;
0078     case 8000000:
0079         bw_i = 3;
0080         bw_param = 0;
0081         break;
0082     default:
0083         return -EINVAL;
0084     }
0085 
0086     /* program tuner */
0087     if (fe->ops.tuner_ops.set_params)
0088         fe->ops.tuner_ops.set_params(fe);
0089 
0090     if (priv->delivery_system != SYS_DVBT2) {
0091         ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
0092         if (ret)
0093             goto error;
0094     }
0095 
0096     priv->delivery_system = SYS_DVBT2;
0097 
0098     /* program IF frequency */
0099     if (fe->ops.tuner_ops.get_if_frequency) {
0100         ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
0101         if (ret)
0102             goto error;
0103         dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
0104     } else {
0105         ret = -EINVAL;
0106         goto error;
0107     }
0108 
0109     utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, CXD2820R_CLK);
0110     buf[0] = (utmp >> 16) & 0xff;
0111     buf[1] = (utmp >>  8) & 0xff;
0112     buf[2] = (utmp >>  0) & 0xff;
0113     ret = regmap_bulk_write(priv->regmap[0], 0x20b6, buf, 3);
0114     if (ret)
0115         goto error;
0116 
0117     /* PLP filtering */
0118     if (c->stream_id > 255) {
0119         dev_dbg(&client->dev, "disable PLP filtering\n");
0120         ret = regmap_write(priv->regmap[0], 0x23ad, 0x00);
0121         if (ret)
0122             goto error;
0123     } else {
0124         dev_dbg(&client->dev, "enable PLP filtering\n");
0125         ret = regmap_write(priv->regmap[0], 0x23af, c->stream_id & 0xff);
0126         if (ret)
0127             goto error;
0128         ret = regmap_write(priv->regmap[0], 0x23ad, 0x01);
0129         if (ret)
0130             goto error;
0131     }
0132 
0133     ret = regmap_bulk_write(priv->regmap[0], 0x209f, bw_params1[bw_i], 5);
0134     if (ret)
0135         goto error;
0136 
0137     ret = regmap_update_bits(priv->regmap[0], 0x20d7, 0xc0, bw_param << 6);
0138     if (ret)
0139         goto error;
0140 
0141     ret = regmap_write(priv->regmap[0], 0x00ff, 0x08);
0142     if (ret)
0143         goto error;
0144 
0145     ret = regmap_write(priv->regmap[0], 0x00fe, 0x01);
0146     if (ret)
0147         goto error;
0148 
0149     return ret;
0150 error:
0151     dev_dbg(&client->dev, "failed=%d\n", ret);
0152     return ret;
0153 
0154 }
0155 
0156 int cxd2820r_get_frontend_t2(struct dvb_frontend *fe,
0157                  struct dtv_frontend_properties *c)
0158 {
0159     struct cxd2820r_priv *priv = fe->demodulator_priv;
0160     struct i2c_client *client = priv->client[0];
0161     int ret;
0162     unsigned int utmp;
0163     u8 buf[2];
0164 
0165     dev_dbg(&client->dev, "\n");
0166 
0167     ret = regmap_bulk_read(priv->regmap[0], 0x205c, buf, 2);
0168     if (ret)
0169         goto error;
0170 
0171     switch ((buf[0] >> 0) & 0x07) {
0172     case 0:
0173         c->transmission_mode = TRANSMISSION_MODE_2K;
0174         break;
0175     case 1:
0176         c->transmission_mode = TRANSMISSION_MODE_8K;
0177         break;
0178     case 2:
0179         c->transmission_mode = TRANSMISSION_MODE_4K;
0180         break;
0181     case 3:
0182         c->transmission_mode = TRANSMISSION_MODE_1K;
0183         break;
0184     case 4:
0185         c->transmission_mode = TRANSMISSION_MODE_16K;
0186         break;
0187     case 5:
0188         c->transmission_mode = TRANSMISSION_MODE_32K;
0189         break;
0190     }
0191 
0192     switch ((buf[1] >> 4) & 0x07) {
0193     case 0:
0194         c->guard_interval = GUARD_INTERVAL_1_32;
0195         break;
0196     case 1:
0197         c->guard_interval = GUARD_INTERVAL_1_16;
0198         break;
0199     case 2:
0200         c->guard_interval = GUARD_INTERVAL_1_8;
0201         break;
0202     case 3:
0203         c->guard_interval = GUARD_INTERVAL_1_4;
0204         break;
0205     case 4:
0206         c->guard_interval = GUARD_INTERVAL_1_128;
0207         break;
0208     case 5:
0209         c->guard_interval = GUARD_INTERVAL_19_128;
0210         break;
0211     case 6:
0212         c->guard_interval = GUARD_INTERVAL_19_256;
0213         break;
0214     }
0215 
0216     ret = regmap_bulk_read(priv->regmap[0], 0x225b, buf, 2);
0217     if (ret)
0218         goto error;
0219 
0220     switch ((buf[0] >> 0) & 0x07) {
0221     case 0:
0222         c->fec_inner = FEC_1_2;
0223         break;
0224     case 1:
0225         c->fec_inner = FEC_3_5;
0226         break;
0227     case 2:
0228         c->fec_inner = FEC_2_3;
0229         break;
0230     case 3:
0231         c->fec_inner = FEC_3_4;
0232         break;
0233     case 4:
0234         c->fec_inner = FEC_4_5;
0235         break;
0236     case 5:
0237         c->fec_inner = FEC_5_6;
0238         break;
0239     }
0240 
0241     switch ((buf[1] >> 0) & 0x07) {
0242     case 0:
0243         c->modulation = QPSK;
0244         break;
0245     case 1:
0246         c->modulation = QAM_16;
0247         break;
0248     case 2:
0249         c->modulation = QAM_64;
0250         break;
0251     case 3:
0252         c->modulation = QAM_256;
0253         break;
0254     }
0255 
0256     ret = regmap_read(priv->regmap[0], 0x20b5, &utmp);
0257     if (ret)
0258         goto error;
0259 
0260     switch ((utmp >> 4) & 0x01) {
0261     case 0:
0262         c->inversion = INVERSION_OFF;
0263         break;
0264     case 1:
0265         c->inversion = INVERSION_ON;
0266         break;
0267     }
0268 
0269     return ret;
0270 error:
0271     dev_dbg(&client->dev, "failed=%d\n", ret);
0272     return ret;
0273 }
0274 
0275 int cxd2820r_read_status_t2(struct dvb_frontend *fe, enum fe_status *status)
0276 {
0277     struct cxd2820r_priv *priv = fe->demodulator_priv;
0278     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0279     struct i2c_client *client = priv->client[0];
0280     int ret;
0281     unsigned int utmp, utmp1, utmp2;
0282     u8 buf[4];
0283 
0284     /* Lock detection */
0285     ret = regmap_bulk_read(priv->regmap[0], 0x2010, &buf[0], 1);
0286     if (ret)
0287         goto error;
0288 
0289     utmp1 = (buf[0] >> 0) & 0x07;
0290     utmp2 = (buf[0] >> 5) & 0x01;
0291 
0292     if (utmp1 == 6 && utmp2 == 1) {
0293         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
0294               FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
0295     } else if (utmp1 == 6 || utmp2 == 1) {
0296         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
0297               FE_HAS_VITERBI | FE_HAS_SYNC;
0298     } else {
0299         *status = 0;
0300     }
0301 
0302     dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
0303         *status, 1, buf, utmp1, utmp2);
0304 
0305     /* Signal strength */
0306     if (*status & FE_HAS_SIGNAL) {
0307         unsigned int strength;
0308 
0309         ret = regmap_bulk_read(priv->regmap[0], 0x2026, buf, 2);
0310         if (ret)
0311             goto error;
0312 
0313         utmp = buf[0] << 8 | buf[1] << 0;
0314         utmp = ~utmp & 0x0fff;
0315         /* Scale value to 0x0000-0xffff */
0316         strength = utmp << 4 | utmp >> 8;
0317 
0318         c->strength.len = 1;
0319         c->strength.stat[0].scale = FE_SCALE_RELATIVE;
0320         c->strength.stat[0].uvalue = strength;
0321     } else {
0322         c->strength.len = 1;
0323         c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0324     }
0325 
0326     /* CNR */
0327     if (*status & FE_HAS_VITERBI) {
0328         unsigned int cnr;
0329 
0330         ret = regmap_bulk_read(priv->regmap[0], 0x2028, buf, 2);
0331         if (ret)
0332             goto error;
0333 
0334         utmp = buf[0] << 8 | buf[1] << 0;
0335         utmp = utmp & 0x0fff;
0336         #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
0337         if (utmp)
0338             cnr = div_u64((u64)(intlog10(utmp)
0339                       - CXD2820R_LOG10_8_24) * 10000,
0340                       (1 << 24));
0341         else
0342             cnr = 0;
0343 
0344         c->cnr.len = 1;
0345         c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
0346         c->cnr.stat[0].svalue = cnr;
0347     } else {
0348         c->cnr.len = 1;
0349         c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0350     }
0351 
0352     /* BER */
0353     if (*status & FE_HAS_SYNC) {
0354         unsigned int post_bit_error;
0355 
0356         ret = regmap_bulk_read(priv->regmap[0], 0x2039, buf, 4);
0357         if (ret)
0358             goto error;
0359 
0360         if ((buf[0] >> 4) & 0x01) {
0361             post_bit_error = buf[0] << 24 | buf[1] << 16 |
0362                      buf[2] << 8 | buf[3] << 0;
0363             post_bit_error &= 0x0fffffff;
0364         } else {
0365             post_bit_error = 0;
0366         }
0367 
0368         priv->post_bit_error += post_bit_error;
0369 
0370         c->post_bit_error.len = 1;
0371         c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
0372         c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
0373     } else {
0374         c->post_bit_error.len = 1;
0375         c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0376     }
0377 
0378     return ret;
0379 error:
0380     dev_dbg(&client->dev, "failed=%d\n", ret);
0381     return ret;
0382 }
0383 
0384 int cxd2820r_sleep_t2(struct dvb_frontend *fe)
0385 {
0386     struct cxd2820r_priv *priv = fe->demodulator_priv;
0387     struct i2c_client *client = priv->client[0];
0388     int ret;
0389     static const struct reg_val_mask tab[] = {
0390         { 0x000ff, 0x1f, 0xff },
0391         { 0x00085, 0x00, 0xff },
0392         { 0x00088, 0x01, 0xff },
0393         { 0x02069, 0x00, 0xff },
0394         { 0x00081, 0x00, 0xff },
0395         { 0x00080, 0x00, 0xff },
0396     };
0397 
0398     dev_dbg(&client->dev, "\n");
0399 
0400     ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
0401     if (ret)
0402         goto error;
0403 
0404     priv->delivery_system = SYS_UNDEFINED;
0405 
0406     return ret;
0407 error:
0408     dev_dbg(&client->dev, "failed=%d\n", ret);
0409     return ret;
0410 }
0411 
0412 int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe,
0413     struct dvb_frontend_tune_settings *s)
0414 {
0415     s->min_delay_ms = 1500;
0416     s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
0417     s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;
0418 
0419     return 0;
0420 }
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