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0008 #include <linux/slab.h>
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/i2c.h>
0012 #include <linux/regmap.h>
0013 #include <linux/wait.h>
0014 #include <linux/delay.h>
0015 #include <linux/mutex.h>
0016 #include <linux/io.h>
0017
0018 #include "cxd2099.h"
0019
0020 static int buffermode;
0021 module_param(buffermode, int, 0444);
0022 MODULE_PARM_DESC(buffermode, "Enable CXD2099AR buffer mode (default: disabled)");
0023
0024 static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount);
0025
0026 struct cxd {
0027 struct dvb_ca_en50221 en;
0028
0029 struct cxd2099_cfg cfg;
0030 struct i2c_client *client;
0031 struct regmap *regmap;
0032
0033 u8 regs[0x23];
0034 u8 lastaddress;
0035 u8 clk_reg_f;
0036 u8 clk_reg_b;
0037 int mode;
0038 int ready;
0039 int dr;
0040 int write_busy;
0041 int slot_stat;
0042
0043 u8 amem[1024];
0044 int amem_read;
0045
0046 int cammode;
0047 struct mutex lock;
0048
0049 u8 rbuf[1028];
0050 u8 wbuf[1028];
0051 };
0052
0053 static int read_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
0054 {
0055 int status = 0;
0056
0057 if (ci->lastaddress != adr)
0058 status = regmap_write(ci->regmap, 0, adr);
0059 if (!status) {
0060 ci->lastaddress = adr;
0061
0062 while (n) {
0063 int len = n;
0064
0065 if (ci->cfg.max_i2c && len > ci->cfg.max_i2c)
0066 len = ci->cfg.max_i2c;
0067 status = regmap_raw_read(ci->regmap, 1, data, len);
0068 if (status)
0069 return status;
0070 data += len;
0071 n -= len;
0072 }
0073 }
0074 return status;
0075 }
0076
0077 static int read_reg(struct cxd *ci, u8 reg, u8 *val)
0078 {
0079 return read_block(ci, reg, val, 1);
0080 }
0081
0082 static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
0083 {
0084 int status;
0085 u8 addr[2] = {address & 0xff, address >> 8};
0086
0087 status = regmap_raw_write(ci->regmap, 2, addr, 2);
0088 if (!status)
0089 status = regmap_raw_read(ci->regmap, 3, data, n);
0090 return status;
0091 }
0092
0093 static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
0094 {
0095 int status;
0096 u8 addr[2] = {address & 0xff, address >> 8};
0097
0098 status = regmap_raw_write(ci->regmap, 2, addr, 2);
0099 if (!status) {
0100 u8 buf[256];
0101
0102 memcpy(buf, data, n);
0103 status = regmap_raw_write(ci->regmap, 3, buf, n);
0104 }
0105 return status;
0106 }
0107
0108 static int read_io(struct cxd *ci, u16 address, unsigned int *val)
0109 {
0110 int status;
0111 u8 addr[2] = {address & 0xff, address >> 8};
0112
0113 status = regmap_raw_write(ci->regmap, 2, addr, 2);
0114 if (!status)
0115 status = regmap_read(ci->regmap, 3, val);
0116 return status;
0117 }
0118
0119 static int write_io(struct cxd *ci, u16 address, u8 val)
0120 {
0121 int status;
0122 u8 addr[2] = {address & 0xff, address >> 8};
0123
0124 status = regmap_raw_write(ci->regmap, 2, addr, 2);
0125 if (!status)
0126 status = regmap_write(ci->regmap, 3, val);
0127 return status;
0128 }
0129
0130 static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
0131 {
0132 int status = 0;
0133 unsigned int regval;
0134
0135 if (ci->lastaddress != reg)
0136 status = regmap_write(ci->regmap, 0, reg);
0137 if (!status && reg >= 6 && reg <= 8 && mask != 0xff) {
0138 status = regmap_read(ci->regmap, 1, ®val);
0139 ci->regs[reg] = regval;
0140 }
0141 ci->lastaddress = reg;
0142 ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
0143 if (!status)
0144 status = regmap_write(ci->regmap, 1, ci->regs[reg]);
0145 if (reg == 0x20)
0146 ci->regs[reg] &= 0x7f;
0147 return status;
0148 }
0149
0150 static int write_reg(struct cxd *ci, u8 reg, u8 val)
0151 {
0152 return write_regm(ci, reg, val, 0xff);
0153 }
0154
0155 static int write_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
0156 {
0157 int status = 0;
0158 u8 *buf = ci->wbuf;
0159
0160 if (ci->lastaddress != adr)
0161 status = regmap_write(ci->regmap, 0, adr);
0162 if (status)
0163 return status;
0164
0165 ci->lastaddress = adr;
0166 while (n) {
0167 int len = n;
0168
0169 if (ci->cfg.max_i2c && (len + 1 > ci->cfg.max_i2c))
0170 len = ci->cfg.max_i2c - 1;
0171 memcpy(buf, data, len);
0172 status = regmap_raw_write(ci->regmap, 1, buf, len);
0173 if (status)
0174 return status;
0175 n -= len;
0176 data += len;
0177 }
0178 return status;
0179 }
0180
0181 static void set_mode(struct cxd *ci, int mode)
0182 {
0183 if (mode == ci->mode)
0184 return;
0185
0186 switch (mode) {
0187 case 0x00:
0188 write_regm(ci, 0x06, 0x00, 0x07);
0189 break;
0190 case 0x01:
0191 write_regm(ci, 0x06, 0x02, 0x07);
0192 break;
0193 default:
0194 break;
0195 }
0196 ci->mode = mode;
0197 }
0198
0199 static void cam_mode(struct cxd *ci, int mode)
0200 {
0201 u8 dummy;
0202
0203 if (mode == ci->cammode)
0204 return;
0205
0206 switch (mode) {
0207 case 0x00:
0208 write_regm(ci, 0x20, 0x80, 0x80);
0209 break;
0210 case 0x01:
0211 if (!ci->en.read_data)
0212 return;
0213 ci->write_busy = 0;
0214 dev_info(&ci->client->dev, "enable cam buffer mode\n");
0215 write_reg(ci, 0x0d, 0x00);
0216 write_reg(ci, 0x0e, 0x01);
0217 write_regm(ci, 0x08, 0x40, 0x40);
0218 read_reg(ci, 0x12, &dummy);
0219 write_regm(ci, 0x08, 0x80, 0x80);
0220 break;
0221 default:
0222 break;
0223 }
0224 ci->cammode = mode;
0225 }
0226
0227 static int init(struct cxd *ci)
0228 {
0229 int status;
0230
0231 mutex_lock(&ci->lock);
0232 ci->mode = -1;
0233 do {
0234 status = write_reg(ci, 0x00, 0x00);
0235 if (status < 0)
0236 break;
0237 status = write_reg(ci, 0x01, 0x00);
0238 if (status < 0)
0239 break;
0240 status = write_reg(ci, 0x02, 0x10);
0241 if (status < 0)
0242 break;
0243 status = write_reg(ci, 0x03, 0x00);
0244 if (status < 0)
0245 break;
0246 status = write_reg(ci, 0x05, 0xFF);
0247 if (status < 0)
0248 break;
0249 status = write_reg(ci, 0x06, 0x1F);
0250 if (status < 0)
0251 break;
0252 status = write_reg(ci, 0x07, 0x1F);
0253 if (status < 0)
0254 break;
0255 status = write_reg(ci, 0x08, 0x28);
0256 if (status < 0)
0257 break;
0258 status = write_reg(ci, 0x14, 0x20);
0259 if (status < 0)
0260 break;
0261
0262
0263
0264
0265 status = write_reg(ci, 0x0A, 0xA7);
0266 if (status < 0)
0267 break;
0268
0269 status = write_reg(ci, 0x0B, 0x33);
0270 if (status < 0)
0271 break;
0272 status = write_reg(ci, 0x0C, 0x33);
0273 if (status < 0)
0274 break;
0275
0276 status = write_regm(ci, 0x14, 0x00, 0x0F);
0277 if (status < 0)
0278 break;
0279 status = write_reg(ci, 0x15, ci->clk_reg_b);
0280 if (status < 0)
0281 break;
0282 status = write_regm(ci, 0x16, 0x00, 0x0F);
0283 if (status < 0)
0284 break;
0285 status = write_reg(ci, 0x17, ci->clk_reg_f);
0286 if (status < 0)
0287 break;
0288
0289 if (ci->cfg.clock_mode == 2) {
0290
0291 u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000;
0292
0293 if (ci->cfg.polarity) {
0294 status = write_reg(ci, 0x09, 0x6f);
0295 if (status < 0)
0296 break;
0297 } else {
0298 status = write_reg(ci, 0x09, 0x6d);
0299 if (status < 0)
0300 break;
0301 }
0302 status = write_reg(ci, 0x20, 0x08);
0303 if (status < 0)
0304 break;
0305 status = write_reg(ci, 0x21, (reg >> 8) & 0xff);
0306 if (status < 0)
0307 break;
0308 status = write_reg(ci, 0x22, reg & 0xff);
0309 if (status < 0)
0310 break;
0311 } else if (ci->cfg.clock_mode == 1) {
0312 if (ci->cfg.polarity) {
0313 status = write_reg(ci, 0x09, 0x6f);
0314 if (status < 0)
0315 break;
0316 } else {
0317 status = write_reg(ci, 0x09, 0x6d);
0318 if (status < 0)
0319 break;
0320 }
0321 status = write_reg(ci, 0x20, 0x68);
0322 if (status < 0)
0323 break;
0324 status = write_reg(ci, 0x21, 0x00);
0325 if (status < 0)
0326 break;
0327 status = write_reg(ci, 0x22, 0x02);
0328 if (status < 0)
0329 break;
0330 } else {
0331 if (ci->cfg.polarity) {
0332 status = write_reg(ci, 0x09, 0x4f);
0333 if (status < 0)
0334 break;
0335 } else {
0336 status = write_reg(ci, 0x09, 0x4d);
0337 if (status < 0)
0338 break;
0339 }
0340 status = write_reg(ci, 0x20, 0x28);
0341 if (status < 0)
0342 break;
0343 status = write_reg(ci, 0x21, 0x00);
0344 if (status < 0)
0345 break;
0346 status = write_reg(ci, 0x22, 0x07);
0347 if (status < 0)
0348 break;
0349 }
0350
0351 status = write_regm(ci, 0x20, 0x80, 0x80);
0352 if (status < 0)
0353 break;
0354 status = write_regm(ci, 0x03, 0x02, 0x02);
0355 if (status < 0)
0356 break;
0357 status = write_reg(ci, 0x01, 0x04);
0358 if (status < 0)
0359 break;
0360 status = write_reg(ci, 0x00, 0x31);
0361 if (status < 0)
0362 break;
0363
0364
0365 status = write_regm(ci, 0x09, 0x08, 0x08);
0366 if (status < 0)
0367 break;
0368 ci->cammode = -1;
0369 cam_mode(ci, 0);
0370 } while (0);
0371 mutex_unlock(&ci->lock);
0372
0373 return 0;
0374 }
0375
0376 static int read_attribute_mem(struct dvb_ca_en50221 *ca,
0377 int slot, int address)
0378 {
0379 struct cxd *ci = ca->data;
0380 u8 val;
0381
0382 mutex_lock(&ci->lock);
0383 set_mode(ci, 1);
0384 read_pccard(ci, address, &val, 1);
0385 mutex_unlock(&ci->lock);
0386 return val;
0387 }
0388
0389 static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
0390 int address, u8 value)
0391 {
0392 struct cxd *ci = ca->data;
0393
0394 mutex_lock(&ci->lock);
0395 set_mode(ci, 1);
0396 write_pccard(ci, address, &value, 1);
0397 mutex_unlock(&ci->lock);
0398 return 0;
0399 }
0400
0401 static int read_cam_control(struct dvb_ca_en50221 *ca,
0402 int slot, u8 address)
0403 {
0404 struct cxd *ci = ca->data;
0405 unsigned int val;
0406
0407 mutex_lock(&ci->lock);
0408 set_mode(ci, 0);
0409 read_io(ci, address, &val);
0410 mutex_unlock(&ci->lock);
0411 return val;
0412 }
0413
0414 static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
0415 u8 address, u8 value)
0416 {
0417 struct cxd *ci = ca->data;
0418
0419 mutex_lock(&ci->lock);
0420 set_mode(ci, 0);
0421 write_io(ci, address, value);
0422 mutex_unlock(&ci->lock);
0423 return 0;
0424 }
0425
0426 static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
0427 {
0428 struct cxd *ci = ca->data;
0429
0430 if (ci->cammode)
0431 read_data(ca, slot, ci->rbuf, 0);
0432
0433 mutex_lock(&ci->lock);
0434 cam_mode(ci, 0);
0435 write_reg(ci, 0x00, 0x21);
0436 write_reg(ci, 0x06, 0x1F);
0437 write_reg(ci, 0x00, 0x31);
0438 write_regm(ci, 0x20, 0x80, 0x80);
0439 write_reg(ci, 0x03, 0x02);
0440 ci->ready = 0;
0441 ci->mode = -1;
0442 {
0443 int i;
0444
0445 for (i = 0; i < 100; i++) {
0446 usleep_range(10000, 11000);
0447 if (ci->ready)
0448 break;
0449 }
0450 }
0451 mutex_unlock(&ci->lock);
0452 return 0;
0453 }
0454
0455 static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
0456 {
0457 struct cxd *ci = ca->data;
0458
0459 dev_dbg(&ci->client->dev, "%s\n", __func__);
0460 if (ci->cammode)
0461 read_data(ca, slot, ci->rbuf, 0);
0462 mutex_lock(&ci->lock);
0463 write_reg(ci, 0x00, 0x21);
0464 write_reg(ci, 0x06, 0x1F);
0465 msleep(300);
0466
0467 write_regm(ci, 0x09, 0x08, 0x08);
0468 write_regm(ci, 0x20, 0x80, 0x80);
0469 write_regm(ci, 0x06, 0x07, 0x07);
0470
0471 ci->mode = -1;
0472 ci->write_busy = 0;
0473 mutex_unlock(&ci->lock);
0474 return 0;
0475 }
0476
0477 static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
0478 {
0479 struct cxd *ci = ca->data;
0480
0481 mutex_lock(&ci->lock);
0482 write_regm(ci, 0x09, 0x00, 0x08);
0483 set_mode(ci, 0);
0484 cam_mode(ci, 1);
0485 mutex_unlock(&ci->lock);
0486 return 0;
0487 }
0488
0489 static int campoll(struct cxd *ci)
0490 {
0491 u8 istat;
0492
0493 read_reg(ci, 0x04, &istat);
0494 if (!istat)
0495 return 0;
0496 write_reg(ci, 0x05, istat);
0497
0498 if (istat & 0x40)
0499 ci->dr = 1;
0500 if (istat & 0x20)
0501 ci->write_busy = 0;
0502
0503 if (istat & 2) {
0504 u8 slotstat;
0505
0506 read_reg(ci, 0x01, &slotstat);
0507 if (!(2 & slotstat)) {
0508 if (!ci->slot_stat) {
0509 ci->slot_stat |=
0510 DVB_CA_EN50221_POLL_CAM_PRESENT;
0511 write_regm(ci, 0x03, 0x08, 0x08);
0512 }
0513
0514 } else {
0515 if (ci->slot_stat) {
0516 ci->slot_stat = 0;
0517 write_regm(ci, 0x03, 0x00, 0x08);
0518 dev_info(&ci->client->dev, "NO CAM\n");
0519 ci->ready = 0;
0520 }
0521 }
0522 if ((istat & 8) &&
0523 ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) {
0524 ci->ready = 1;
0525 ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
0526 }
0527 }
0528 return 0;
0529 }
0530
0531 static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
0532 {
0533 struct cxd *ci = ca->data;
0534 u8 slotstat;
0535
0536 mutex_lock(&ci->lock);
0537 campoll(ci);
0538 read_reg(ci, 0x01, &slotstat);
0539 mutex_unlock(&ci->lock);
0540
0541 return ci->slot_stat;
0542 }
0543
0544 static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
0545 {
0546 struct cxd *ci = ca->data;
0547 u8 msb, lsb;
0548 u16 len;
0549
0550 mutex_lock(&ci->lock);
0551 campoll(ci);
0552 mutex_unlock(&ci->lock);
0553
0554 if (!ci->dr)
0555 return 0;
0556
0557 mutex_lock(&ci->lock);
0558 read_reg(ci, 0x0f, &msb);
0559 read_reg(ci, 0x10, &lsb);
0560 len = ((u16)msb << 8) | lsb;
0561 if (len > ecount || len < 2) {
0562
0563 read_block(ci, 0x12, ci->rbuf, len);
0564 mutex_unlock(&ci->lock);
0565 return -EIO;
0566 }
0567 read_block(ci, 0x12, ebuf, len);
0568 ci->dr = 0;
0569 mutex_unlock(&ci->lock);
0570 return len;
0571 }
0572
0573 static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
0574 {
0575 struct cxd *ci = ca->data;
0576
0577 if (ci->write_busy)
0578 return -EAGAIN;
0579 mutex_lock(&ci->lock);
0580 write_reg(ci, 0x0d, ecount >> 8);
0581 write_reg(ci, 0x0e, ecount & 0xff);
0582 write_block(ci, 0x11, ebuf, ecount);
0583 ci->write_busy = 1;
0584 mutex_unlock(&ci->lock);
0585 return ecount;
0586 }
0587
0588 static const struct dvb_ca_en50221 en_templ = {
0589 .read_attribute_mem = read_attribute_mem,
0590 .write_attribute_mem = write_attribute_mem,
0591 .read_cam_control = read_cam_control,
0592 .write_cam_control = write_cam_control,
0593 .slot_reset = slot_reset,
0594 .slot_shutdown = slot_shutdown,
0595 .slot_ts_enable = slot_ts_enable,
0596 .poll_slot_status = poll_slot_status,
0597 .read_data = read_data,
0598 .write_data = write_data,
0599 };
0600
0601 static int cxd2099_probe(struct i2c_client *client,
0602 const struct i2c_device_id *id)
0603 {
0604 struct cxd *ci;
0605 struct cxd2099_cfg *cfg = client->dev.platform_data;
0606 static const struct regmap_config rm_cfg = {
0607 .reg_bits = 8,
0608 .val_bits = 8,
0609 };
0610 unsigned int val;
0611 int ret;
0612
0613 ci = kzalloc(sizeof(*ci), GFP_KERNEL);
0614 if (!ci) {
0615 ret = -ENOMEM;
0616 goto err;
0617 }
0618
0619 ci->client = client;
0620 memcpy(&ci->cfg, cfg, sizeof(ci->cfg));
0621
0622 ci->regmap = regmap_init_i2c(client, &rm_cfg);
0623 if (IS_ERR(ci->regmap)) {
0624 ret = PTR_ERR(ci->regmap);
0625 goto err_kfree;
0626 }
0627
0628 ret = regmap_read(ci->regmap, 0x00, &val);
0629 if (ret < 0) {
0630 dev_info(&client->dev, "No CXD2099AR detected at 0x%02x\n",
0631 client->addr);
0632 goto err_rmexit;
0633 }
0634
0635 mutex_init(&ci->lock);
0636 ci->lastaddress = 0xff;
0637 ci->clk_reg_b = 0x4a;
0638 ci->clk_reg_f = 0x1b;
0639
0640 ci->en = en_templ;
0641 ci->en.data = ci;
0642 init(ci);
0643 dev_info(&client->dev, "Attached CXD2099AR at 0x%02x\n", client->addr);
0644
0645 *cfg->en = &ci->en;
0646
0647 if (!buffermode) {
0648 ci->en.read_data = NULL;
0649 ci->en.write_data = NULL;
0650 } else {
0651 dev_info(&client->dev, "Using CXD2099AR buffer mode");
0652 }
0653
0654 i2c_set_clientdata(client, ci);
0655
0656 return 0;
0657
0658 err_rmexit:
0659 regmap_exit(ci->regmap);
0660 err_kfree:
0661 kfree(ci);
0662 err:
0663
0664 return ret;
0665 }
0666
0667 static int cxd2099_remove(struct i2c_client *client)
0668 {
0669 struct cxd *ci = i2c_get_clientdata(client);
0670
0671 regmap_exit(ci->regmap);
0672 kfree(ci);
0673
0674 return 0;
0675 }
0676
0677 static const struct i2c_device_id cxd2099_id[] = {
0678 {"cxd2099", 0},
0679 {}
0680 };
0681 MODULE_DEVICE_TABLE(i2c, cxd2099_id);
0682
0683 static struct i2c_driver cxd2099_driver = {
0684 .driver = {
0685 .name = "cxd2099",
0686 },
0687 .probe = cxd2099_probe,
0688 .remove = cxd2099_remove,
0689 .id_table = cxd2099_id,
0690 };
0691
0692 module_i2c_driver(cxd2099_driver);
0693
0694 MODULE_DESCRIPTION("Sony CXD2099AR Common Interface controller driver");
0695 MODULE_AUTHOR("Ralph Metzler");
0696 MODULE_LICENSE("GPL v2");
