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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *   Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver
0004  *
0005  *   Copyright (C) 2005 Steven Toth <stoth@linuxtv.org>
0006  *
0007  *   Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc>
0008  *
0009  *   Support for CX24123/CX24113-NIM by Patrick Boettcher <pb@linuxtv.org>
0010  */
0011 
0012 #include <linux/slab.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/init.h>
0016 #include <asm/div64.h>
0017 
0018 #include <media/dvb_frontend.h>
0019 #include "cx24123.h"
0020 
0021 #define XTAL 10111000
0022 
0023 static int force_band;
0024 module_param(force_band, int, 0644);
0025 MODULE_PARM_DESC(force_band, "Force a specific band select "\
0026     "(1-9, default:off).");
0027 
0028 static int debug;
0029 module_param(debug, int, 0644);
0030 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
0031 
0032 #define info(args...) do { printk(KERN_INFO "CX24123: " args); } while (0)
0033 #define err(args...)  do { printk(KERN_ERR  "CX24123: " args); } while (0)
0034 
0035 #define dprintk(args...) \
0036     do { \
0037         if (debug) { \
0038             printk(KERN_DEBUG "CX24123: %s: ", __func__); \
0039             printk(args); \
0040         } \
0041     } while (0)
0042 
0043 struct cx24123_state {
0044     struct i2c_adapter *i2c;
0045     const struct cx24123_config *config;
0046 
0047     struct dvb_frontend frontend;
0048 
0049     /* Some PLL specifics for tuning */
0050     u32 VCAarg;
0051     u32 VGAarg;
0052     u32 bandselectarg;
0053     u32 pllarg;
0054     u32 FILTune;
0055 
0056     struct i2c_adapter tuner_i2c_adapter;
0057 
0058     u8 demod_rev;
0059 
0060     /* The Demod/Tuner can't easily provide these, we cache them */
0061     u32 currentfreq;
0062     u32 currentsymbolrate;
0063 };
0064 
0065 /* Various tuner defaults need to be established for a given symbol rate Sps */
0066 static struct cx24123_AGC_val {
0067     u32 symbolrate_low;
0068     u32 symbolrate_high;
0069     u32 VCAprogdata;
0070     u32 VGAprogdata;
0071     u32 FILTune;
0072 } cx24123_AGC_vals[] =
0073 {
0074     {
0075         .symbolrate_low     = 1000000,
0076         .symbolrate_high    = 4999999,
0077         /* the specs recommend other values for VGA offsets,
0078            but tests show they are wrong */
0079         .VGAprogdata        = (1 << 19) | (0x180 << 9) | 0x1e0,
0080         .VCAprogdata        = (2 << 19) | (0x07 << 9) | 0x07,
0081         .FILTune        = 0x27f /* 0.41 V */
0082     },
0083     {
0084         .symbolrate_low     =  5000000,
0085         .symbolrate_high    = 14999999,
0086         .VGAprogdata        = (1 << 19) | (0x180 << 9) | 0x1e0,
0087         .VCAprogdata        = (2 << 19) | (0x07 << 9) | 0x1f,
0088         .FILTune        = 0x317 /* 0.90 V */
0089     },
0090     {
0091         .symbolrate_low     = 15000000,
0092         .symbolrate_high    = 45000000,
0093         .VGAprogdata        = (1 << 19) | (0x100 << 9) | 0x180,
0094         .VCAprogdata        = (2 << 19) | (0x07 << 9) | 0x3f,
0095         .FILTune        = 0x145 /* 2.70 V */
0096     },
0097 };
0098 
0099 /*
0100  * Various tuner defaults need to be established for a given frequency kHz.
0101  * fixme: The bounds on the bands do not match the doc in real life.
0102  * fixme: Some of them have been moved, other might need adjustment.
0103  */
0104 static struct cx24123_bandselect_val {
0105     u32 freq_low;
0106     u32 freq_high;
0107     u32 VCOdivider;
0108     u32 progdata;
0109 } cx24123_bandselect_vals[] =
0110 {
0111     /* band 1 */
0112     {
0113         .freq_low   = 950000,
0114         .freq_high  = 1074999,
0115         .VCOdivider = 4,
0116         .progdata   = (0 << 19) | (0 << 9) | 0x40,
0117     },
0118 
0119     /* band 2 */
0120     {
0121         .freq_low   = 1075000,
0122         .freq_high  = 1177999,
0123         .VCOdivider = 4,
0124         .progdata   = (0 << 19) | (0 << 9) | 0x80,
0125     },
0126 
0127     /* band 3 */
0128     {
0129         .freq_low   = 1178000,
0130         .freq_high  = 1295999,
0131         .VCOdivider = 2,
0132         .progdata   = (0 << 19) | (1 << 9) | 0x01,
0133     },
0134 
0135     /* band 4 */
0136     {
0137         .freq_low   = 1296000,
0138         .freq_high  = 1431999,
0139         .VCOdivider = 2,
0140         .progdata   = (0 << 19) | (1 << 9) | 0x02,
0141     },
0142 
0143     /* band 5 */
0144     {
0145         .freq_low   = 1432000,
0146         .freq_high  = 1575999,
0147         .VCOdivider = 2,
0148         .progdata   = (0 << 19) | (1 << 9) | 0x04,
0149     },
0150 
0151     /* band 6 */
0152     {
0153         .freq_low   = 1576000,
0154         .freq_high  = 1717999,
0155         .VCOdivider = 2,
0156         .progdata   = (0 << 19) | (1 << 9) | 0x08,
0157     },
0158 
0159     /* band 7 */
0160     {
0161         .freq_low   = 1718000,
0162         .freq_high  = 1855999,
0163         .VCOdivider = 2,
0164         .progdata   = (0 << 19) | (1 << 9) | 0x10,
0165     },
0166 
0167     /* band 8 */
0168     {
0169         .freq_low   = 1856000,
0170         .freq_high  = 2035999,
0171         .VCOdivider = 2,
0172         .progdata   = (0 << 19) | (1 << 9) | 0x20,
0173     },
0174 
0175     /* band 9 */
0176     {
0177         .freq_low   = 2036000,
0178         .freq_high  = 2150000,
0179         .VCOdivider = 2,
0180         .progdata   = (0 << 19) | (1 << 9) | 0x40,
0181     },
0182 };
0183 
0184 static struct {
0185     u8 reg;
0186     u8 data;
0187 } cx24123_regdata[] =
0188 {
0189     {0x00, 0x03}, /* Reset system */
0190     {0x00, 0x00}, /* Clear reset */
0191     {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */
0192     {0x04, 0x10}, /* MPEG */
0193     {0x05, 0x04}, /* MPEG */
0194     {0x06, 0x31}, /* MPEG (default) */
0195     {0x0b, 0x00}, /* Freq search start point (default) */
0196     {0x0c, 0x00}, /* Demodulator sample gain (default) */
0197     {0x0d, 0x7f}, /* Force driver to shift until the maximum (+-10 MHz) */
0198     {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */
0199     {0x0f, 0xfe}, /* FEC search mask (all supported codes) */
0200     {0x10, 0x01}, /* Default search inversion, no repeat (default) */
0201     {0x16, 0x00}, /* Enable reading of frequency */
0202     {0x17, 0x01}, /* Enable EsNO Ready Counter */
0203     {0x1c, 0x80}, /* Enable error counter */
0204     {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */
0205     {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */
0206     {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */
0207     {0x29, 0x00}, /* DiSEqC LNB_DC off */
0208     {0x2a, 0xb0}, /* DiSEqC Parameters (default) */
0209     {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */
0210     {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */
0211     {0x2d, 0x00},
0212     {0x2e, 0x00},
0213     {0x2f, 0x00},
0214     {0x30, 0x00},
0215     {0x31, 0x00},
0216     {0x32, 0x8c}, /* DiSEqC Parameters (default) */
0217     {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */
0218     {0x34, 0x00},
0219     {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */
0220     {0x36, 0x02}, /* DiSEqC Parameters (default) */
0221     {0x37, 0x3a}, /* DiSEqC Parameters (default) */
0222     {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */
0223     {0x44, 0x00}, /* Constellation (default) */
0224     {0x45, 0x00}, /* Symbol count (default) */
0225     {0x46, 0x0d}, /* Symbol rate estimator on (default) */
0226     {0x56, 0xc1}, /* Error Counter = Viterbi BER */
0227     {0x57, 0xff}, /* Error Counter Window (default) */
0228     {0x5c, 0x20}, /* Acquisition AFC Expiration window (default is 0x10) */
0229     {0x67, 0x83}, /* Non-DCII symbol clock */
0230 };
0231 
0232 static int cx24123_i2c_writereg(struct cx24123_state *state,
0233     u8 i2c_addr, int reg, int data)
0234 {
0235     u8 buf[] = { reg, data };
0236     struct i2c_msg msg = {
0237         .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
0238     };
0239     int err;
0240 
0241     /* printk(KERN_DEBUG "wr(%02x): %02x %02x\n", i2c_addr, reg, data); */
0242 
0243     err = i2c_transfer(state->i2c, &msg, 1);
0244     if (err != 1) {
0245         printk("%s: writereg error(err == %i, reg == 0x%02x, data == 0x%02x)\n",
0246                __func__, err, reg, data);
0247         return err;
0248     }
0249 
0250     return 0;
0251 }
0252 
0253 static int cx24123_i2c_readreg(struct cx24123_state *state, u8 i2c_addr, u8 reg)
0254 {
0255     int ret;
0256     u8 b = 0;
0257     struct i2c_msg msg[] = {
0258         { .addr = i2c_addr, .flags = 0, .buf = &reg, .len = 1 },
0259         { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &b, .len = 1 }
0260     };
0261 
0262     ret = i2c_transfer(state->i2c, msg, 2);
0263 
0264     if (ret != 2) {
0265         err("%s: reg=0x%x (error=%d)\n", __func__, reg, ret);
0266         return ret;
0267     }
0268 
0269     /* printk(KERN_DEBUG "rd(%02x): %02x %02x\n", i2c_addr, reg, b); */
0270 
0271     return b;
0272 }
0273 
0274 #define cx24123_readreg(state, reg) \
0275     cx24123_i2c_readreg(state, state->config->demod_address, reg)
0276 #define cx24123_writereg(state, reg, val) \
0277     cx24123_i2c_writereg(state, state->config->demod_address, reg, val)
0278 
0279 static int cx24123_set_inversion(struct cx24123_state *state,
0280                  enum fe_spectral_inversion inversion)
0281 {
0282     u8 nom_reg = cx24123_readreg(state, 0x0e);
0283     u8 auto_reg = cx24123_readreg(state, 0x10);
0284 
0285     switch (inversion) {
0286     case INVERSION_OFF:
0287         dprintk("inversion off\n");
0288         cx24123_writereg(state, 0x0e, nom_reg & ~0x80);
0289         cx24123_writereg(state, 0x10, auto_reg | 0x80);
0290         break;
0291     case INVERSION_ON:
0292         dprintk("inversion on\n");
0293         cx24123_writereg(state, 0x0e, nom_reg | 0x80);
0294         cx24123_writereg(state, 0x10, auto_reg | 0x80);
0295         break;
0296     case INVERSION_AUTO:
0297         dprintk("inversion auto\n");
0298         cx24123_writereg(state, 0x10, auto_reg & ~0x80);
0299         break;
0300     default:
0301         return -EINVAL;
0302     }
0303 
0304     return 0;
0305 }
0306 
0307 static int cx24123_get_inversion(struct cx24123_state *state,
0308                  enum fe_spectral_inversion *inversion)
0309 {
0310     u8 val;
0311 
0312     val = cx24123_readreg(state, 0x1b) >> 7;
0313 
0314     if (val == 0) {
0315         dprintk("read inversion off\n");
0316         *inversion = INVERSION_OFF;
0317     } else {
0318         dprintk("read inversion on\n");
0319         *inversion = INVERSION_ON;
0320     }
0321 
0322     return 0;
0323 }
0324 
0325 static int cx24123_set_fec(struct cx24123_state *state, enum fe_code_rate fec)
0326 {
0327     u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07;
0328 
0329     if (((int)fec < FEC_NONE) || (fec > FEC_AUTO))
0330         fec = FEC_AUTO;
0331 
0332     /* Set the soft decision threshold */
0333     if (fec == FEC_1_2)
0334         cx24123_writereg(state, 0x43,
0335             cx24123_readreg(state, 0x43) | 0x01);
0336     else
0337         cx24123_writereg(state, 0x43,
0338             cx24123_readreg(state, 0x43) & ~0x01);
0339 
0340     switch (fec) {
0341     case FEC_1_2:
0342         dprintk("set FEC to 1/2\n");
0343         cx24123_writereg(state, 0x0e, nom_reg | 0x01);
0344         cx24123_writereg(state, 0x0f, 0x02);
0345         break;
0346     case FEC_2_3:
0347         dprintk("set FEC to 2/3\n");
0348         cx24123_writereg(state, 0x0e, nom_reg | 0x02);
0349         cx24123_writereg(state, 0x0f, 0x04);
0350         break;
0351     case FEC_3_4:
0352         dprintk("set FEC to 3/4\n");
0353         cx24123_writereg(state, 0x0e, nom_reg | 0x03);
0354         cx24123_writereg(state, 0x0f, 0x08);
0355         break;
0356     case FEC_4_5:
0357         dprintk("set FEC to 4/5\n");
0358         cx24123_writereg(state, 0x0e, nom_reg | 0x04);
0359         cx24123_writereg(state, 0x0f, 0x10);
0360         break;
0361     case FEC_5_6:
0362         dprintk("set FEC to 5/6\n");
0363         cx24123_writereg(state, 0x0e, nom_reg | 0x05);
0364         cx24123_writereg(state, 0x0f, 0x20);
0365         break;
0366     case FEC_6_7:
0367         dprintk("set FEC to 6/7\n");
0368         cx24123_writereg(state, 0x0e, nom_reg | 0x06);
0369         cx24123_writereg(state, 0x0f, 0x40);
0370         break;
0371     case FEC_7_8:
0372         dprintk("set FEC to 7/8\n");
0373         cx24123_writereg(state, 0x0e, nom_reg | 0x07);
0374         cx24123_writereg(state, 0x0f, 0x80);
0375         break;
0376     case FEC_AUTO:
0377         dprintk("set FEC to auto\n");
0378         cx24123_writereg(state, 0x0f, 0xfe);
0379         break;
0380     default:
0381         return -EOPNOTSUPP;
0382     }
0383 
0384     return 0;
0385 }
0386 
0387 static int cx24123_get_fec(struct cx24123_state *state, enum fe_code_rate *fec)
0388 {
0389     int ret;
0390 
0391     ret = cx24123_readreg(state, 0x1b);
0392     if (ret < 0)
0393         return ret;
0394     ret = ret & 0x07;
0395 
0396     switch (ret) {
0397     case 1:
0398         *fec = FEC_1_2;
0399         break;
0400     case 2:
0401         *fec = FEC_2_3;
0402         break;
0403     case 3:
0404         *fec = FEC_3_4;
0405         break;
0406     case 4:
0407         *fec = FEC_4_5;
0408         break;
0409     case 5:
0410         *fec = FEC_5_6;
0411         break;
0412     case 6:
0413         *fec = FEC_6_7;
0414         break;
0415     case 7:
0416         *fec = FEC_7_8;
0417         break;
0418     default:
0419         /* this can happen when there's no lock */
0420         *fec = FEC_NONE;
0421     }
0422 
0423     return 0;
0424 }
0425 
0426 /* Approximation of closest integer of log2(a/b). It actually gives the
0427    lowest integer i such that 2^i >= round(a/b) */
0428 static u32 cx24123_int_log2(u32 a, u32 b)
0429 {
0430     u32 exp, nearest = 0;
0431     u32 div = a / b;
0432     if (a % b >= b / 2)
0433         ++div;
0434     if (div < (1UL << 31)) {
0435         for (exp = 1; div > exp; nearest++)
0436             exp += exp;
0437     }
0438     return nearest;
0439 }
0440 
0441 static int cx24123_set_symbolrate(struct cx24123_state *state, u32 srate)
0442 {
0443     u64 tmp;
0444     u32 sample_rate, ratio, sample_gain;
0445     u8 pll_mult;
0446 
0447     /*  check if symbol rate is within limits */
0448     if ((srate > state->frontend.ops.info.symbol_rate_max) ||
0449         (srate < state->frontend.ops.info.symbol_rate_min))
0450         return -EOPNOTSUPP;
0451 
0452     /* choose the sampling rate high enough for the required operation,
0453        while optimizing the power consumed by the demodulator */
0454     if (srate < (XTAL*2)/2)
0455         pll_mult = 2;
0456     else if (srate < (XTAL*3)/2)
0457         pll_mult = 3;
0458     else if (srate < (XTAL*4)/2)
0459         pll_mult = 4;
0460     else if (srate < (XTAL*5)/2)
0461         pll_mult = 5;
0462     else if (srate < (XTAL*6)/2)
0463         pll_mult = 6;
0464     else if (srate < (XTAL*7)/2)
0465         pll_mult = 7;
0466     else if (srate < (XTAL*8)/2)
0467         pll_mult = 8;
0468     else
0469         pll_mult = 9;
0470 
0471 
0472     sample_rate = pll_mult * XTAL;
0473 
0474     /* SYSSymbolRate[21:0] = (srate << 23) / sample_rate */
0475 
0476     tmp = ((u64)srate) << 23;
0477     do_div(tmp, sample_rate);
0478     ratio = (u32) tmp;
0479 
0480     cx24123_writereg(state, 0x01, pll_mult * 6);
0481 
0482     cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f);
0483     cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff);
0484     cx24123_writereg(state, 0x0a, ratio & 0xff);
0485 
0486     /* also set the demodulator sample gain */
0487     sample_gain = cx24123_int_log2(sample_rate, srate);
0488     tmp = cx24123_readreg(state, 0x0c) & ~0xe0;
0489     cx24123_writereg(state, 0x0c, tmp | sample_gain << 5);
0490 
0491     dprintk("srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n",
0492         srate, ratio, sample_rate, sample_gain);
0493 
0494     return 0;
0495 }
0496 
0497 /*
0498  * Based on the required frequency and symbolrate, the tuner AGC has
0499  * to be configured and the correct band selected.
0500  * Calculate those values.
0501  */
0502 static int cx24123_pll_calculate(struct dvb_frontend *fe)
0503 {
0504     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0505     struct cx24123_state *state = fe->demodulator_priv;
0506     u32 ndiv = 0, adiv = 0, vco_div = 0;
0507     int i = 0;
0508     int pump = 2;
0509     int band = 0;
0510     int num_bands = ARRAY_SIZE(cx24123_bandselect_vals);
0511     struct cx24123_bandselect_val *bsv = NULL;
0512     struct cx24123_AGC_val *agcv = NULL;
0513 
0514     /* Defaults for low freq, low rate */
0515     state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
0516     state->VGAarg = cx24123_AGC_vals[0].VGAprogdata;
0517     state->bandselectarg = cx24123_bandselect_vals[0].progdata;
0518     vco_div = cx24123_bandselect_vals[0].VCOdivider;
0519 
0520     /* For the given symbol rate, determine the VCA, VGA and
0521      * FILTUNE programming bits */
0522     for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++) {
0523         agcv = &cx24123_AGC_vals[i];
0524         if ((agcv->symbolrate_low <= p->symbol_rate) &&
0525             (agcv->symbolrate_high >= p->symbol_rate)) {
0526             state->VCAarg = agcv->VCAprogdata;
0527             state->VGAarg = agcv->VGAprogdata;
0528             state->FILTune = agcv->FILTune;
0529         }
0530     }
0531 
0532     /* determine the band to use */
0533     if (force_band < 1 || force_band > num_bands) {
0534         for (i = 0; i < num_bands; i++) {
0535             bsv = &cx24123_bandselect_vals[i];
0536             if ((bsv->freq_low <= p->frequency) &&
0537                 (bsv->freq_high >= p->frequency))
0538                 band = i;
0539         }
0540     } else
0541         band = force_band - 1;
0542 
0543     state->bandselectarg = cx24123_bandselect_vals[band].progdata;
0544     vco_div = cx24123_bandselect_vals[band].VCOdivider;
0545 
0546     /* determine the charge pump current */
0547     if (p->frequency < (cx24123_bandselect_vals[band].freq_low +
0548         cx24123_bandselect_vals[band].freq_high) / 2)
0549         pump = 0x01;
0550     else
0551         pump = 0x02;
0552 
0553     /* Determine the N/A dividers for the requested lband freq (in kHz). */
0554     /* Note: the reference divider R=10, frequency is in KHz,
0555      * XTAL is in Hz */
0556     ndiv = (((p->frequency * vco_div * 10) /
0557         (2 * XTAL / 1000)) / 32) & 0x1ff;
0558     adiv = (((p->frequency * vco_div * 10) /
0559         (2 * XTAL / 1000)) % 32) & 0x1f;
0560 
0561     if (adiv == 0 && ndiv > 0)
0562         ndiv--;
0563 
0564     /* control bits 11, refdiv 11, charge pump polarity 1,
0565      * charge pump current, ndiv, adiv */
0566     state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) |
0567         (pump << 14) | (ndiv << 5) | adiv;
0568 
0569     return 0;
0570 }
0571 
0572 /*
0573  * Tuner data is 21 bits long, must be left-aligned in data.
0574  * Tuner cx24109 is written through a dedicated 3wire interface
0575  * on the demod chip.
0576  */
0577 static int cx24123_pll_writereg(struct dvb_frontend *fe, u32 data)
0578 {
0579     struct cx24123_state *state = fe->demodulator_priv;
0580     unsigned long timeout;
0581 
0582     dprintk("pll writereg called, data=0x%08x\n", data);
0583 
0584     /* align the 21 bytes into to bit23 boundary */
0585     data = data << 3;
0586 
0587     /* Reset the demod pll word length to 0x15 bits */
0588     cx24123_writereg(state, 0x21, 0x15);
0589 
0590     /* write the msb 8 bits, wait for the send to be completed */
0591     timeout = jiffies + msecs_to_jiffies(40);
0592     cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
0593     while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
0594         if (time_after(jiffies, timeout)) {
0595             err("%s:  demodulator is not responding, "\
0596                 "possibly hung, aborting.\n", __func__);
0597             return -EREMOTEIO;
0598         }
0599         msleep(10);
0600     }
0601 
0602     /* send another 8 bytes, wait for the send to be completed */
0603     timeout = jiffies + msecs_to_jiffies(40);
0604     cx24123_writereg(state, 0x22, (data >> 8) & 0xff);
0605     while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
0606         if (time_after(jiffies, timeout)) {
0607             err("%s:  demodulator is not responding, "\
0608                 "possibly hung, aborting.\n", __func__);
0609             return -EREMOTEIO;
0610         }
0611         msleep(10);
0612     }
0613 
0614     /* send the lower 5 bits of this byte, padded with 3 LBB,
0615      * wait for the send to be completed */
0616     timeout = jiffies + msecs_to_jiffies(40);
0617     cx24123_writereg(state, 0x22, (data) & 0xff);
0618     while ((cx24123_readreg(state, 0x20) & 0x80)) {
0619         if (time_after(jiffies, timeout)) {
0620             err("%s:  demodulator is not responding," \
0621                 "possibly hung, aborting.\n", __func__);
0622             return -EREMOTEIO;
0623         }
0624         msleep(10);
0625     }
0626 
0627     /* Trigger the demod to configure the tuner */
0628     cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2);
0629     cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd);
0630 
0631     return 0;
0632 }
0633 
0634 static int cx24123_pll_tune(struct dvb_frontend *fe)
0635 {
0636     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0637     struct cx24123_state *state = fe->demodulator_priv;
0638     u8 val;
0639 
0640     dprintk("frequency=%i\n", p->frequency);
0641 
0642     if (cx24123_pll_calculate(fe) != 0) {
0643         err("%s: cx24123_pll_calculate failed\n", __func__);
0644         return -EINVAL;
0645     }
0646 
0647     /* Write the new VCO/VGA */
0648     cx24123_pll_writereg(fe, state->VCAarg);
0649     cx24123_pll_writereg(fe, state->VGAarg);
0650 
0651     /* Write the new bandselect and pll args */
0652     cx24123_pll_writereg(fe, state->bandselectarg);
0653     cx24123_pll_writereg(fe, state->pllarg);
0654 
0655     /* set the FILTUNE voltage */
0656     val = cx24123_readreg(state, 0x28) & ~0x3;
0657     cx24123_writereg(state, 0x27, state->FILTune >> 2);
0658     cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3));
0659 
0660     dprintk("pll tune VCA=%d, band=%d, pll=%d\n", state->VCAarg,
0661             state->bandselectarg, state->pllarg);
0662 
0663     return 0;
0664 }
0665 
0666 
0667 /*
0668  * 0x23:
0669  *    [7:7] = BTI enabled
0670  *    [6:6] = I2C repeater enabled
0671  *    [5:5] = I2C repeater start
0672  *    [0:0] = BTI start
0673  */
0674 
0675 /* mode == 1 -> i2c-repeater, 0 -> bti */
0676 static int cx24123_repeater_mode(struct cx24123_state *state, u8 mode, u8 start)
0677 {
0678     u8 r = cx24123_readreg(state, 0x23) & 0x1e;
0679     if (mode)
0680         r |= (1 << 6) | (start << 5);
0681     else
0682         r |= (1 << 7) | (start);
0683     return cx24123_writereg(state, 0x23, r);
0684 }
0685 
0686 static int cx24123_initfe(struct dvb_frontend *fe)
0687 {
0688     struct cx24123_state *state = fe->demodulator_priv;
0689     int i;
0690 
0691     dprintk("init frontend\n");
0692 
0693     /* Configure the demod to a good set of defaults */
0694     for (i = 0; i < ARRAY_SIZE(cx24123_regdata); i++)
0695         cx24123_writereg(state, cx24123_regdata[i].reg,
0696             cx24123_regdata[i].data);
0697 
0698     /* Set the LNB polarity */
0699     if (state->config->lnb_polarity)
0700         cx24123_writereg(state, 0x32,
0701             cx24123_readreg(state, 0x32) | 0x02);
0702 
0703     if (state->config->dont_use_pll)
0704         cx24123_repeater_mode(state, 1, 0);
0705 
0706     return 0;
0707 }
0708 
0709 static int cx24123_set_voltage(struct dvb_frontend *fe,
0710                    enum fe_sec_voltage voltage)
0711 {
0712     struct cx24123_state *state = fe->demodulator_priv;
0713     u8 val;
0714 
0715     val = cx24123_readreg(state, 0x29) & ~0x40;
0716 
0717     switch (voltage) {
0718     case SEC_VOLTAGE_13:
0719         dprintk("setting voltage 13V\n");
0720         return cx24123_writereg(state, 0x29, val & 0x7f);
0721     case SEC_VOLTAGE_18:
0722         dprintk("setting voltage 18V\n");
0723         return cx24123_writereg(state, 0x29, val | 0x80);
0724     case SEC_VOLTAGE_OFF:
0725         /* already handled in cx88-dvb */
0726         return 0;
0727     default:
0728         return -EINVAL;
0729     }
0730 
0731     return 0;
0732 }
0733 
0734 /* wait for diseqc queue to become ready (or timeout) */
0735 static void cx24123_wait_for_diseqc(struct cx24123_state *state)
0736 {
0737     unsigned long timeout = jiffies + msecs_to_jiffies(200);
0738     while (!(cx24123_readreg(state, 0x29) & 0x40)) {
0739         if (time_after(jiffies, timeout)) {
0740             err("%s: diseqc queue not ready, " \
0741                 "command may be lost.\n", __func__);
0742             break;
0743         }
0744         msleep(10);
0745     }
0746 }
0747 
0748 static int cx24123_send_diseqc_msg(struct dvb_frontend *fe,
0749     struct dvb_diseqc_master_cmd *cmd)
0750 {
0751     struct cx24123_state *state = fe->demodulator_priv;
0752     int i, val, tone;
0753 
0754     dprintk("\n");
0755 
0756     /* stop continuous tone if enabled */
0757     tone = cx24123_readreg(state, 0x29);
0758     if (tone & 0x10)
0759         cx24123_writereg(state, 0x29, tone & ~0x50);
0760 
0761     /* wait for diseqc queue ready */
0762     cx24123_wait_for_diseqc(state);
0763 
0764     /* select tone mode */
0765     cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
0766 
0767     for (i = 0; i < cmd->msg_len; i++)
0768         cx24123_writereg(state, 0x2C + i, cmd->msg[i]);
0769 
0770     val = cx24123_readreg(state, 0x29);
0771     cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) |
0772         ((cmd->msg_len-3) & 3));
0773 
0774     /* wait for diseqc message to finish sending */
0775     cx24123_wait_for_diseqc(state);
0776 
0777     /* restart continuous tone if enabled */
0778     if (tone & 0x10)
0779         cx24123_writereg(state, 0x29, tone & ~0x40);
0780 
0781     return 0;
0782 }
0783 
0784 static int cx24123_diseqc_send_burst(struct dvb_frontend *fe,
0785                      enum fe_sec_mini_cmd burst)
0786 {
0787     struct cx24123_state *state = fe->demodulator_priv;
0788     int val, tone;
0789 
0790     dprintk("\n");
0791 
0792     /* stop continuous tone if enabled */
0793     tone = cx24123_readreg(state, 0x29);
0794     if (tone & 0x10)
0795         cx24123_writereg(state, 0x29, tone & ~0x50);
0796 
0797     /* wait for diseqc queue ready */
0798     cx24123_wait_for_diseqc(state);
0799 
0800     /* select tone mode */
0801     cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4);
0802     msleep(30);
0803     val = cx24123_readreg(state, 0x29);
0804     if (burst == SEC_MINI_A)
0805         cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00));
0806     else if (burst == SEC_MINI_B)
0807         cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08));
0808     else
0809         return -EINVAL;
0810 
0811     cx24123_wait_for_diseqc(state);
0812     cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
0813 
0814     /* restart continuous tone if enabled */
0815     if (tone & 0x10)
0816         cx24123_writereg(state, 0x29, tone & ~0x40);
0817 
0818     return 0;
0819 }
0820 
0821 static int cx24123_read_status(struct dvb_frontend *fe, enum fe_status *status)
0822 {
0823     struct cx24123_state *state = fe->demodulator_priv;
0824     int sync = cx24123_readreg(state, 0x14);
0825 
0826     *status = 0;
0827     if (state->config->dont_use_pll) {
0828         u32 tun_status = 0;
0829         if (fe->ops.tuner_ops.get_status)
0830             fe->ops.tuner_ops.get_status(fe, &tun_status);
0831         if (tun_status & TUNER_STATUS_LOCKED)
0832             *status |= FE_HAS_SIGNAL;
0833     } else {
0834         int lock = cx24123_readreg(state, 0x20);
0835         if (lock & 0x01)
0836             *status |= FE_HAS_SIGNAL;
0837     }
0838 
0839     if (sync & 0x02)
0840         *status |= FE_HAS_CARRIER;  /* Phase locked */
0841     if (sync & 0x04)
0842         *status |= FE_HAS_VITERBI;
0843 
0844     /* Reed-Solomon Status */
0845     if (sync & 0x08)
0846         *status |= FE_HAS_SYNC;
0847     if (sync & 0x80)
0848         *status |= FE_HAS_LOCK;     /*Full Sync */
0849 
0850     return 0;
0851 }
0852 
0853 /*
0854  * Configured to return the measurement of errors in blocks,
0855  * because no UCBLOCKS value is available, so this value doubles up
0856  * to satisfy both measurements.
0857  */
0858 static int cx24123_read_ber(struct dvb_frontend *fe, u32 *ber)
0859 {
0860     struct cx24123_state *state = fe->demodulator_priv;
0861 
0862     /* The true bit error rate is this value divided by
0863        the window size (set as 256 * 255) */
0864     *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) |
0865         (cx24123_readreg(state, 0x1d) << 8 |
0866          cx24123_readreg(state, 0x1e));
0867 
0868     dprintk("BER = %d\n", *ber);
0869 
0870     return 0;
0871 }
0872 
0873 static int cx24123_read_signal_strength(struct dvb_frontend *fe,
0874     u16 *signal_strength)
0875 {
0876     struct cx24123_state *state = fe->demodulator_priv;
0877 
0878     /* larger = better */
0879     *signal_strength = cx24123_readreg(state, 0x3b) << 8;
0880 
0881     dprintk("Signal strength = %d\n", *signal_strength);
0882 
0883     return 0;
0884 }
0885 
0886 static int cx24123_read_snr(struct dvb_frontend *fe, u16 *snr)
0887 {
0888     struct cx24123_state *state = fe->demodulator_priv;
0889 
0890     /* Inverted raw Es/N0 count, totally bogus but better than the
0891        BER threshold. */
0892     *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) |
0893              (u16)cx24123_readreg(state, 0x19));
0894 
0895     dprintk("read S/N index = %d\n", *snr);
0896 
0897     return 0;
0898 }
0899 
0900 static int cx24123_set_frontend(struct dvb_frontend *fe)
0901 {
0902     struct cx24123_state *state = fe->demodulator_priv;
0903     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0904 
0905     dprintk("\n");
0906 
0907     if (state->config->set_ts_params)
0908         state->config->set_ts_params(fe, 0);
0909 
0910     state->currentfreq = p->frequency;
0911     state->currentsymbolrate = p->symbol_rate;
0912 
0913     cx24123_set_inversion(state, p->inversion);
0914     cx24123_set_fec(state, p->fec_inner);
0915     cx24123_set_symbolrate(state, p->symbol_rate);
0916 
0917     if (!state->config->dont_use_pll)
0918         cx24123_pll_tune(fe);
0919     else if (fe->ops.tuner_ops.set_params)
0920         fe->ops.tuner_ops.set_params(fe);
0921     else
0922         err("it seems I don't have a tuner...");
0923 
0924     /* Enable automatic acquisition and reset cycle */
0925     cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
0926     cx24123_writereg(state, 0x00, 0x10);
0927     cx24123_writereg(state, 0x00, 0);
0928 
0929     if (state->config->agc_callback)
0930         state->config->agc_callback(fe);
0931 
0932     return 0;
0933 }
0934 
0935 static int cx24123_get_frontend(struct dvb_frontend *fe,
0936                 struct dtv_frontend_properties *p)
0937 {
0938     struct cx24123_state *state = fe->demodulator_priv;
0939 
0940     dprintk("\n");
0941 
0942     if (cx24123_get_inversion(state, &p->inversion) != 0) {
0943         err("%s: Failed to get inversion status\n", __func__);
0944         return -EREMOTEIO;
0945     }
0946     if (cx24123_get_fec(state, &p->fec_inner) != 0) {
0947         err("%s: Failed to get fec status\n", __func__);
0948         return -EREMOTEIO;
0949     }
0950     p->frequency = state->currentfreq;
0951     p->symbol_rate = state->currentsymbolrate;
0952 
0953     return 0;
0954 }
0955 
0956 static int cx24123_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
0957 {
0958     struct cx24123_state *state = fe->demodulator_priv;
0959     u8 val;
0960 
0961     /* wait for diseqc queue ready */
0962     cx24123_wait_for_diseqc(state);
0963 
0964     val = cx24123_readreg(state, 0x29) & ~0x40;
0965 
0966     switch (tone) {
0967     case SEC_TONE_ON:
0968         dprintk("setting tone on\n");
0969         return cx24123_writereg(state, 0x29, val | 0x10);
0970     case SEC_TONE_OFF:
0971         dprintk("setting tone off\n");
0972         return cx24123_writereg(state, 0x29, val & 0xef);
0973     default:
0974         err("CASE reached default with tone=%d\n", tone);
0975         return -EINVAL;
0976     }
0977 
0978     return 0;
0979 }
0980 
0981 static int cx24123_tune(struct dvb_frontend *fe,
0982             bool re_tune,
0983             unsigned int mode_flags,
0984             unsigned int *delay,
0985             enum fe_status *status)
0986 {
0987     int retval = 0;
0988 
0989     if (re_tune)
0990         retval = cx24123_set_frontend(fe);
0991 
0992     if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
0993         cx24123_read_status(fe, status);
0994     *delay = HZ/10;
0995 
0996     return retval;
0997 }
0998 
0999 static enum dvbfe_algo cx24123_get_algo(struct dvb_frontend *fe)
1000 {
1001     return DVBFE_ALGO_HW;
1002 }
1003 
1004 static void cx24123_release(struct dvb_frontend *fe)
1005 {
1006     struct cx24123_state *state = fe->demodulator_priv;
1007     dprintk("\n");
1008     i2c_del_adapter(&state->tuner_i2c_adapter);
1009     kfree(state);
1010 }
1011 
1012 static int cx24123_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap,
1013     struct i2c_msg msg[], int num)
1014 {
1015     struct cx24123_state *state = i2c_get_adapdata(i2c_adap);
1016     /* this repeater closes after the first stop */
1017     cx24123_repeater_mode(state, 1, 1);
1018     return i2c_transfer(state->i2c, msg, num);
1019 }
1020 
1021 static u32 cx24123_tuner_i2c_func(struct i2c_adapter *adapter)
1022 {
1023     return I2C_FUNC_I2C;
1024 }
1025 
1026 static const struct i2c_algorithm cx24123_tuner_i2c_algo = {
1027     .master_xfer   = cx24123_tuner_i2c_tuner_xfer,
1028     .functionality = cx24123_tuner_i2c_func,
1029 };
1030 
1031 struct i2c_adapter *
1032     cx24123_get_tuner_i2c_adapter(struct dvb_frontend *fe)
1033 {
1034     struct cx24123_state *state = fe->demodulator_priv;
1035     return &state->tuner_i2c_adapter;
1036 }
1037 EXPORT_SYMBOL(cx24123_get_tuner_i2c_adapter);
1038 
1039 static const struct dvb_frontend_ops cx24123_ops;
1040 
1041 struct dvb_frontend *cx24123_attach(const struct cx24123_config *config,
1042                     struct i2c_adapter *i2c)
1043 {
1044     /* allocate memory for the internal state */
1045     struct cx24123_state *state =
1046         kzalloc(sizeof(struct cx24123_state), GFP_KERNEL);
1047 
1048     dprintk("\n");
1049     if (state == NULL) {
1050         err("Unable to kzalloc\n");
1051         goto error;
1052     }
1053 
1054     /* setup the state */
1055     state->config = config;
1056     state->i2c = i2c;
1057 
1058     /* check if the demod is there */
1059     state->demod_rev = cx24123_readreg(state, 0x00);
1060     switch (state->demod_rev) {
1061     case 0xe1:
1062         info("detected CX24123C\n");
1063         break;
1064     case 0xd1:
1065         info("detected CX24123\n");
1066         break;
1067     default:
1068         err("wrong demod revision: %x\n", state->demod_rev);
1069         goto error;
1070     }
1071 
1072     /* create dvb_frontend */
1073     memcpy(&state->frontend.ops, &cx24123_ops,
1074         sizeof(struct dvb_frontend_ops));
1075     state->frontend.demodulator_priv = state;
1076 
1077     /* create tuner i2c adapter */
1078     if (config->dont_use_pll)
1079         cx24123_repeater_mode(state, 1, 0);
1080 
1081     strscpy(state->tuner_i2c_adapter.name, "CX24123 tuner I2C bus",
1082         sizeof(state->tuner_i2c_adapter.name));
1083     state->tuner_i2c_adapter.algo      = &cx24123_tuner_i2c_algo;
1084     state->tuner_i2c_adapter.algo_data = NULL;
1085     state->tuner_i2c_adapter.dev.parent = i2c->dev.parent;
1086     i2c_set_adapdata(&state->tuner_i2c_adapter, state);
1087     if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
1088         err("tuner i2c bus could not be initialized\n");
1089         goto error;
1090     }
1091 
1092     return &state->frontend;
1093 
1094 error:
1095     kfree(state);
1096 
1097     return NULL;
1098 }
1099 EXPORT_SYMBOL(cx24123_attach);
1100 
1101 static const struct dvb_frontend_ops cx24123_ops = {
1102     .delsys = { SYS_DVBS },
1103     .info = {
1104         .name = "Conexant CX24123/CX24109",
1105         .frequency_min_hz =  950 * MHz,
1106         .frequency_max_hz = 2150 * MHz,
1107         .frequency_stepsize_hz = 1011 * kHz,
1108         .frequency_tolerance_hz = 5 * MHz,
1109         .symbol_rate_min = 1000000,
1110         .symbol_rate_max = 45000000,
1111         .caps = FE_CAN_INVERSION_AUTO |
1112             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1113             FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1114             FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1115             FE_CAN_QPSK | FE_CAN_RECOVER
1116     },
1117 
1118     .release = cx24123_release,
1119 
1120     .init = cx24123_initfe,
1121     .set_frontend = cx24123_set_frontend,
1122     .get_frontend = cx24123_get_frontend,
1123     .read_status = cx24123_read_status,
1124     .read_ber = cx24123_read_ber,
1125     .read_signal_strength = cx24123_read_signal_strength,
1126     .read_snr = cx24123_read_snr,
1127     .diseqc_send_master_cmd = cx24123_send_diseqc_msg,
1128     .diseqc_send_burst = cx24123_diseqc_send_burst,
1129     .set_tone = cx24123_set_tone,
1130     .set_voltage = cx24123_set_voltage,
1131     .tune = cx24123_tune,
1132     .get_frontend_algo = cx24123_get_algo,
1133 };
1134 
1135 MODULE_DESCRIPTION("DVB Frontend module for Conexant " \
1136     "CX24123/CX24109/CX24113 hardware");
1137 MODULE_AUTHOR("Steven Toth");
1138 MODULE_LICENSE("GPL");
1139
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