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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Support for the Broadcom BCM3510 ATSC demodulator (1st generation Air2PC)
0004  *
0005  *  Copyright (C) 2001-5, B2C2 inc.
0006  *
0007  *  GPL/Linux driver written by Patrick Boettcher <patrick.boettcher@posteo.de>
0008  */
0009 #ifndef __BCM3510_PRIV_H__
0010 #define __BCM3510_PRIV_H__
0011 
0012 #define PACKED __attribute__((packed))
0013 
0014 #undef err
0015 #define err(format, arg...)  printk(KERN_ERR     "bcm3510: " format "\n" , ## arg)
0016 #undef info
0017 #define info(format, arg...) printk(KERN_INFO    "bcm3510: " format "\n" , ## arg)
0018 #undef warn
0019 #define warn(format, arg...) printk(KERN_WARNING "bcm3510: " format "\n" , ## arg)
0020 
0021 
0022 #define PANASONIC_FIRST_IF_BASE_IN_KHz  1407500
0023 #define BCM3510_SYMBOL_RATE             5381000
0024 
0025 typedef union {
0026     u8 raw;
0027 
0028     struct {
0029         u8 CTL   :8;
0030     } TSTCTL_2e;
0031 
0032     u8 LDCERC_4e;
0033     u8 LDUERC_4f;
0034     u8 LD_BER0_65;
0035     u8 LD_BER1_66;
0036     u8 LD_BER2_67;
0037     u8 LD_BER3_68;
0038 
0039     struct {
0040         u8 RESET :1;
0041         u8 IDLE  :1;
0042         u8 STOP  :1;
0043         u8 HIRQ0 :1;
0044         u8 HIRQ1 :1;
0045         u8 na0   :1;
0046         u8 HABAV :1;
0047         u8 na1   :1;
0048     } HCTL1_a0;
0049 
0050     struct {
0051         u8 na0    :1;
0052         u8 IDLMSK :1;
0053         u8 STMSK  :1;
0054         u8 I0MSK  :1;
0055         u8 I1MSK  :1;
0056         u8 na1    :1;
0057         u8 HABMSK :1;
0058         u8 na2    :1;
0059     } HCTLMSK_a1;
0060 
0061     struct {
0062         u8 RESET  :1;
0063         u8 IDLE   :1;
0064         u8 STOP   :1;
0065         u8 RUN    :1;
0066         u8 HABAV  :1;
0067         u8 MEMAV  :1;
0068         u8 ALDONE :1;
0069         u8 REIRQ  :1;
0070     } APSTAT1_a2;
0071 
0072     struct {
0073         u8 RSTMSK :1;
0074         u8 IMSK   :1;
0075         u8 SMSK   :1;
0076         u8 RMSK   :1;
0077         u8 HABMSK :1;
0078         u8 MAVMSK :1;
0079         u8 ALDMSK :1;
0080         u8 REMSK  :1;
0081     } APMSK1_a3;
0082 
0083     u8 APSTAT2_a4;
0084     u8 APMSK2_a5;
0085 
0086     struct {
0087         u8 HABADR :7;
0088         u8 na     :1;
0089     } HABADR_a6;
0090 
0091     u8 HABDATA_a7;
0092 
0093     struct {
0094         u8 HABR   :1;
0095         u8 LDHABR :1;
0096         u8 APMSK  :1;
0097         u8 HMSK   :1;
0098         u8 LDMSK  :1;
0099         u8 na     :3;
0100     } HABSTAT_a8;
0101 
0102     u8 MADRH_a9;
0103     u8 MADRL_aa;
0104     u8 MDATA_ab;
0105 
0106     struct {
0107 #define JDEC_WAIT_AT_RAM      0x7
0108 #define JDEC_EEPROM_LOAD_WAIT 0x4
0109         u8 JDEC   :3;
0110         u8 na     :5;
0111     } JDEC_ca;
0112 
0113     struct {
0114         u8 REV   :4;
0115         u8 LAYER :4;
0116     } REVID_e0;
0117 
0118     struct {
0119         u8 unk0   :1;
0120         u8 CNTCTL :1;
0121         u8 BITCNT :1;
0122         u8 unk1   :1;
0123         u8 RESYNC :1;
0124         u8 unk2   :3;
0125     } BERCTL_fa;
0126 
0127     struct {
0128         u8 CSEL0  :1;
0129         u8 CLKED0 :1;
0130         u8 CSEL1  :1;
0131         u8 CLKED1 :1;
0132         u8 CLKLEV :1;
0133         u8 SPIVAR :1;
0134         u8 na     :2;
0135     } TUNSET_fc;
0136 
0137     struct {
0138         u8 CLK    :1;
0139         u8 DATA   :1;
0140         u8 CS0    :1;
0141         u8 CS1    :1;
0142         u8 AGCSEL :1;
0143         u8 na0    :1;
0144         u8 TUNSEL :1;
0145         u8 na1    :1;
0146     } TUNCTL_fd;
0147 
0148     u8 TUNSEL0_fe;
0149     u8 TUNSEL1_ff;
0150 
0151 } bcm3510_register_value;
0152 
0153 /* HAB commands */
0154 
0155 /* version */
0156 #define CMD_GET_VERSION_INFO   0x3D
0157 #define MSGID_GET_VERSION_INFO 0x15
0158 struct bcm3510_hab_cmd_get_version_info {
0159     u8 microcode_version;
0160     u8 script_version;
0161     u8 config_version;
0162     u8 demod_version;
0163 } PACKED;
0164 
0165 #define BCM3510_DEF_MICROCODE_VERSION 0x0E
0166 #define BCM3510_DEF_SCRIPT_VERSION    0x06
0167 #define BCM3510_DEF_CONFIG_VERSION    0x01
0168 #define BCM3510_DEF_DEMOD_VERSION     0xB1
0169 
0170 /* acquire */
0171 #define CMD_ACQUIRE            0x38
0172 
0173 #define MSGID_EXT_TUNER_ACQUIRE 0x0A
0174 struct bcm3510_hab_cmd_ext_acquire {
0175     struct {
0176         u8 MODE      :4;
0177         u8 BW        :1;
0178         u8 FA        :1;
0179         u8 NTSCSWEEP :1;
0180         u8 OFFSET    :1;
0181     } PACKED ACQUIRE0; /* control_byte */
0182 
0183     struct {
0184         u8 IF_FREQ  :3;
0185         u8 zero0    :1;
0186         u8 SYM_RATE :3;
0187         u8 zero1    :1;
0188     } PACKED ACQUIRE1; /* sym_if */
0189 
0190     u8 IF_OFFSET0;   /* IF_Offset_10hz */
0191     u8 IF_OFFSET1;
0192     u8 SYM_OFFSET0;  /* SymbolRateOffset */
0193     u8 SYM_OFFSET1;
0194     u8 NTSC_OFFSET0; /* NTSC_Offset_10hz */
0195     u8 NTSC_OFFSET1;
0196 } PACKED;
0197 
0198 #define MSGID_INT_TUNER_ACQUIRE 0x0B
0199 struct bcm3510_hab_cmd_int_acquire {
0200     struct {
0201         u8 MODE      :4;
0202         u8 BW        :1;
0203         u8 FA        :1;
0204         u8 NTSCSWEEP :1;
0205         u8 OFFSET    :1;
0206     } PACKED ACQUIRE0; /* control_byte */
0207 
0208     struct {
0209         u8 IF_FREQ  :3;
0210         u8 zero0    :1;
0211         u8 SYM_RATE :3;
0212         u8 zero1    :1;
0213     } PACKED ACQUIRE1; /* sym_if */
0214 
0215     u8 TUNER_FREQ0;
0216     u8 TUNER_FREQ1;
0217     u8 TUNER_FREQ2;
0218     u8 TUNER_FREQ3;
0219     u8 IF_OFFSET0;   /* IF_Offset_10hz */
0220     u8 IF_OFFSET1;
0221     u8 SYM_OFFSET0;  /* SymbolRateOffset */
0222     u8 SYM_OFFSET1;
0223     u8 NTSC_OFFSET0; /* NTSC_Offset_10hz */
0224     u8 NTSC_OFFSET1;
0225 } PACKED;
0226 
0227 /* modes */
0228 #define BCM3510_QAM16           =   0x01
0229 #define BCM3510_QAM32           =   0x02
0230 #define BCM3510_QAM64           =   0x03
0231 #define BCM3510_QAM128          =   0x04
0232 #define BCM3510_QAM256          =   0x05
0233 #define BCM3510_8VSB            =   0x0B
0234 #define BCM3510_16VSB           =   0x0D
0235 
0236 /* IF_FREQS */
0237 #define BCM3510_IF_TERRESTRIAL 0x0
0238 #define BCM3510_IF_CABLE       0x1
0239 #define BCM3510_IF_USE_CMD     0x7
0240 
0241 /* SYM_RATE */
0242 #define BCM3510_SR_8VSB        0x0 /* 5381119 s/sec */
0243 #define BCM3510_SR_256QAM      0x1 /* 5360537 s/sec */
0244 #define BCM3510_SR_16QAM       0x2 /* 5056971 s/sec */
0245 #define BCM3510_SR_MISC        0x3 /* 5000000 s/sec */
0246 #define BCM3510_SR_USE_CMD     0x7
0247 
0248 /* special symbol rate */
0249 #define CMD_SET_VALUE_NOT_LISTED  0x2d
0250 #define MSGID_SET_SYMBOL_RATE_NOT_LISTED 0x0c
0251 struct bcm3510_hab_cmd_set_sr_not_listed {
0252     u8 HOST_SYM_RATE0;
0253     u8 HOST_SYM_RATE1;
0254     u8 HOST_SYM_RATE2;
0255     u8 HOST_SYM_RATE3;
0256 } PACKED;
0257 
0258 /* special IF */
0259 #define MSGID_SET_IF_FREQ_NOT_LISTED 0x0d
0260 struct bcm3510_hab_cmd_set_if_freq_not_listed {
0261     u8 HOST_IF_FREQ0;
0262     u8 HOST_IF_FREQ1;
0263     u8 HOST_IF_FREQ2;
0264     u8 HOST_IF_FREQ3;
0265 } PACKED;
0266 
0267 /* auto reacquire */
0268 #define CMD_AUTO_PARAM       0x2a
0269 #define MSGID_AUTO_REACQUIRE 0x0e
0270 struct bcm3510_hab_cmd_auto_reacquire {
0271     u8 ACQ    :1; /* on/off*/
0272     u8 unused :7;
0273 } PACKED;
0274 
0275 #define MSGID_SET_RF_AGC_SEL 0x12
0276 struct bcm3510_hab_cmd_set_agc {
0277     u8 LVL    :1;
0278     u8 unused :6;
0279     u8 SEL    :1;
0280 } PACKED;
0281 
0282 #define MSGID_SET_AUTO_INVERSION 0x14
0283 struct bcm3510_hab_cmd_auto_inversion {
0284     u8 AI     :1;
0285     u8 unused :7;
0286 } PACKED;
0287 
0288 
0289 /* bert control */
0290 #define CMD_STATE_CONTROL  0x12
0291 #define MSGID_BERT_CONTROL 0x0e
0292 #define MSGID_BERT_SET     0xfa
0293 struct bcm3510_hab_cmd_bert_control {
0294     u8 BE     :1;
0295     u8 unused :7;
0296 } PACKED;
0297 
0298 #define MSGID_TRI_STATE 0x2e
0299 struct bcm3510_hab_cmd_tri_state {
0300     u8 RE :1; /* a/d ram port pins */
0301     u8 PE :1; /* baud clock pin */
0302     u8 AC :1; /* a/d clock pin */
0303     u8 BE :1; /* baud clock pin */
0304     u8 unused :4;
0305 } PACKED;
0306 
0307 
0308 /* tune */
0309 #define CMD_TUNE   0x38
0310 #define MSGID_TUNE 0x16
0311 struct bcm3510_hab_cmd_tune_ctrl_data_pair {
0312     struct {
0313 #define BITS_8 0x07
0314 #define BITS_7 0x06
0315 #define BITS_6 0x05
0316 #define BITS_5 0x04
0317 #define BITS_4 0x03
0318 #define BITS_3 0x02
0319 #define BITS_2 0x01
0320 #define BITS_1 0x00
0321         u8 size    :3;
0322         u8 unk     :2;
0323         u8 clk_off :1;
0324         u8 cs0     :1;
0325         u8 cs1     :1;
0326 
0327     } PACKED ctrl;
0328 
0329     u8 data;
0330 } PACKED;
0331 
0332 struct bcm3510_hab_cmd_tune {
0333     u8 length;
0334     u8 clock_width;
0335     u8 misc;
0336     u8 TUNCTL_state;
0337 
0338     struct bcm3510_hab_cmd_tune_ctrl_data_pair ctl_dat[16];
0339 } PACKED;
0340 
0341 #define CMD_STATUS    0x38
0342 #define MSGID_STATUS1 0x08
0343 struct bcm3510_hab_cmd_status1 {
0344     struct {
0345         u8 EQ_MODE       :4;
0346         u8 reserved      :2;
0347         u8 QRE           :1; /* if QSE and the spectrum is inversed */
0348         u8 QSE           :1; /* automatic spectral inversion */
0349     } PACKED STATUS0;
0350 
0351     struct {
0352         u8 RECEIVER_LOCK :1;
0353         u8 FEC_LOCK      :1;
0354         u8 OUT_PLL_LOCK  :1;
0355         u8 reserved      :5;
0356     } PACKED STATUS1;
0357 
0358     struct {
0359         u8 reserved      :2;
0360         u8 BW            :1;
0361         u8 NTE           :1; /* NTSC filter sweep enabled */
0362         u8 AQI           :1; /* currently acquiring */
0363         u8 FA            :1; /* fast acquisition */
0364         u8 ARI           :1; /* auto reacquire */
0365         u8 TI            :1; /* programming the tuner */
0366     } PACKED STATUS2;
0367     u8 STATUS3;
0368     u8 SNR_EST0;
0369     u8 SNR_EST1;
0370     u8 TUNER_FREQ0;
0371     u8 TUNER_FREQ1;
0372     u8 TUNER_FREQ2;
0373     u8 TUNER_FREQ3;
0374     u8 SYM_RATE0;
0375     u8 SYM_RATE1;
0376     u8 SYM_RATE2;
0377     u8 SYM_RATE3;
0378     u8 SYM_OFFSET0;
0379     u8 SYM_OFFSET1;
0380     u8 SYM_ERROR0;
0381     u8 SYM_ERROR1;
0382     u8 IF_FREQ0;
0383     u8 IF_FREQ1;
0384     u8 IF_FREQ2;
0385     u8 IF_FREQ3;
0386     u8 IF_OFFSET0;
0387     u8 IF_OFFSET1;
0388     u8 IF_ERROR0;
0389     u8 IF_ERROR1;
0390     u8 NTSC_FILTER0;
0391     u8 NTSC_FILTER1;
0392     u8 NTSC_FILTER2;
0393     u8 NTSC_FILTER3;
0394     u8 NTSC_OFFSET0;
0395     u8 NTSC_OFFSET1;
0396     u8 NTSC_ERROR0;
0397     u8 NTSC_ERROR1;
0398     u8 INT_AGC_LEVEL0;
0399     u8 INT_AGC_LEVEL1;
0400     u8 EXT_AGC_LEVEL0;
0401     u8 EXT_AGC_LEVEL1;
0402 } PACKED;
0403 
0404 #define MSGID_STATUS2 0x14
0405 struct bcm3510_hab_cmd_status2 {
0406     struct {
0407         u8 EQ_MODE  :4;
0408         u8 reserved :2;
0409         u8 QRE      :1;
0410         u8 QSR      :1;
0411     } PACKED STATUS0;
0412     struct {
0413         u8 RL       :1;
0414         u8 FL       :1;
0415         u8 OL       :1;
0416         u8 reserved :5;
0417     } PACKED STATUS1;
0418     u8 SYMBOL_RATE0;
0419     u8 SYMBOL_RATE1;
0420     u8 SYMBOL_RATE2;
0421     u8 SYMBOL_RATE3;
0422     u8 LDCERC0;
0423     u8 LDCERC1;
0424     u8 LDCERC2;
0425     u8 LDCERC3;
0426     u8 LDUERC0;
0427     u8 LDUERC1;
0428     u8 LDUERC2;
0429     u8 LDUERC3;
0430     u8 LDBER0;
0431     u8 LDBER1;
0432     u8 LDBER2;
0433     u8 LDBER3;
0434     struct {
0435         u8 MODE_TYPE :4; /* acquire mode 0 */
0436         u8 reservd   :4;
0437     } MODE_TYPE;
0438     u8 SNR_EST0;
0439     u8 SNR_EST1;
0440     u8 SIGNAL;
0441 } PACKED;
0442 
0443 #define CMD_SET_RF_BW_NOT_LISTED   0x3f
0444 #define MSGID_SET_RF_BW_NOT_LISTED 0x11
0445 /* TODO */
0446 
0447 #endif
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